1/* 2 * U-boot - Configuration file for BlackStamp board 3 * Configuration by Ben Matthews for UR LLE using bf533-stamp.h 4 * as a template 5 * See http://blackfin.uclinux.org/gf/project/blackstamp/ 6 */ 7 8#ifndef __CONFIG_BLACKSTAMP_H__ 9#define __CONFIG_BLACKSTAMP_H__ 10 11#include <asm/config-pre.h> 12 13/* 14 * Debugging: Set these options if you're having problems 15 */ 16/* 17 * #define CONFIG_DEBUG_EARLY_SERIAL 18 * #define DEBUG 19 * #define CONFIG_DEBUG_DUMP 20 * #define CONFIG_DEBUG_DUMP_SYMS 21*/ 22#define CONFIG_PANIC_HANG 0 23 24/* CPU Options 25 * Be sure to set the Silicon Revision Correctly 26 */ 27#define CONFIG_BFIN_CPU bf532-0.5 28#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER 29 30/* 31 * Board settings 32 */ 33#define CONFIG_SMC91111 1 34#define CONFIG_SMC91111_BASE 0x20300300 35 36/* FLASH/ETHERNET uses the same address range 37 * Depending on what you have the CPLD doing 38 * this probably isn't needed 39 */ 40#define SHARED_RESOURCES 1 41 42/* Is I2C bit-banged? */ 43#undef CONFIG_SOFT_I2 44 45/* 46 * Clock Settings 47 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV 48 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV 49 */ 50/* CONFIG_CLKIN_HZ is any value in Hz */ 51#define CONFIG_CLKIN_HZ 25000000 52/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ 53/* 1 = CLKIN / 2 */ 54#define CONFIG_CLKIN_HALF 0 55/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ 56/* 1 = bypass PLL */ 57#define CONFIG_PLL_BYPASS 0 58/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ 59/* Values can range from 0-63 (where 0 means 64) */ 60#define CONFIG_VCO_MULT 16 61/* CCLK_DIV controls the core clock divider */ 62/* Values can be 1, 2, 4, or 8 ONLY */ 63#define CONFIG_CCLK_DIV 1 64/* SCLK_DIV controls the system clock divider */ 65/* Values can range from 1-15 */ 66#define CONFIG_SCLK_DIV 3 67 68/* 69 * Network settings 70 */ 71 72#ifdef CONFIG_SMC91111 73#define CONFIG_IPADDR 192.168.0.15 74#define CONFIG_NETMASK 255.255.255.0 75#define CONFIG_GATEWAYIP 192.168.0.1 76#define CONFIG_SERVERIP 192.168.0.2 77#define CONFIG_HOSTNAME blackstamp 78#define CONFIG_ROOTPATH "/checkout/uClinux-dist/romfs" 79#define CONFIG_SYS_AUTOLOAD "no" 80 81/* To remove hardcoding and enable MAC storage in EEPROM */ 82/* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */ 83#endif 84 85#define CONFIG_ENV_IS_IN_SPI_FLASH 86#define CONFIG_ENV_OFFSET 0x40000 87#define CONFIG_ENV_SIZE 0x2000 88#define CONFIG_ENV_SECT_SIZE 0x40000 89 90/* 91 * SDRAM settings & memory map 92 */ 93 94#define CONFIG_MEM_SIZE 64 /* 128, 64, 32, 16 */ 95#define CONFIG_MEM_ADD_WDTH 10 /* 8, 9, 10, 11 */ 96 97#define CONFIG_SYS_MONITOR_LEN (256 << 10) 98#define CONFIG_SYS_MALLOC_LEN (384 << 10) 99 100/* 101 * Command settings 102 */ 103 104#define CONFIG_SYS_LONGHELP 1 105#define CONFIG_CMDLINE_EDITING 1 106#define CONFIG_AUTO_COMPLETE 1 107#define CONFIG_ENV_OVERWRITE 1 108 109#include <config_cmd_default.h> 110 111#ifdef CONFIG_SMC91111 112# define CONFIG_CMD_DHCP 113# define CONFIG_CMD_PING 114#else 115# undef CONFIG_CMD_NET 116#endif 117 118#ifdef CONFIG_SOFT_I2C 119# define CONFIG_CMD_I2C 120#endif 121 122#define CONFIG_CMD_BOOTLDR 123#define CONFIG_CMD_CACHE 124#define CONFIG_CMD_CPLBINFO 125#define CONFIG_CMD_DATE 126#define CONFIG_CMD_SF 127#define CONFIG_CMD_ELF 128 129#define CONFIG_BOOTDELAY 5 130#define CONFIG_BOOTCOMMAND "run ramboot" 131#define CONFIG_BOOTARGS \ 132 "root=/dev/mtdblock0 rw " \ 133 "clkin_hz=" MK_STR(CONFIG_CLKIN_HZ) " " \ 134 "earlyprintk=" \ 135 "serial," \ 136 "uart" MK_STR(CONFIG_UART_CONSOLE) "," \ 137 MK_STR(CONFIG_BAUDRATE) " " \ 138 "console=ttyBF0," MK_STR(CONFIG_BAUDRATE) 139 140#if defined(CONFIG_CMD_NET) 141# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) 142# define UBOOT_ENV_FILE "u-boot.bin" 143# else 144# define UBOOT_ENV_FILE "u-boot.ldr" 145# endif 146# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) 147# ifdef CONFIG_SPI 148# define UBOOT_ENV_UPDATE \ 149 "eeprom write $(loadaddr) 0x0 $(filesize)" 150# else 151# define UBOOT_ENV_UPDATE \ 152 "sf probe " MK_STR(BFIN_BOOT_SPI_SSEL) ";" \ 153 "sf erase 0 0x40000;" \ 154 "sf write $(loadaddr) 0 $(filesize)" 155# endif 156# else 157# define UBOOT_ENV_UPDATE \ 158 "protect off 0x20000000 0x2003FFFF;" \ 159 "erase 0x20000000 0x2003FFFF;" \ 160 "cp.b $(loadaddr) 0x20000000 $(filesize)" 161# endif 162# define NETWORK_ENV_SETTINGS \ 163 "ubootfile=" UBOOT_ENV_FILE "\0" \ 164 "update=" \ 165 "tftp $(loadaddr) $(ubootfile);" \ 166 UBOOT_ENV_UPDATE \ 167 "\0" \ 168 "addip=set bootargs $(bootargs) " \ 169 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):" \ 170 "$(hostname):eth0:off" \ 171 "\0" \ 172 "ramargs=set bootargs " CONFIG_BOOTARGS "\0" \ 173 "ramboot=" \ 174 "tftp $(loadaddr) uImage;" \ 175 "run ramargs;" \ 176 "run addip;" \ 177 "bootm" \ 178 "\0" \ 179 "nfsargs=set bootargs " \ 180 "root=/dev/nfs rw " \ 181 "nfsroot=$(serverip):$(rootpath),tcp,nfsvers=3" \ 182 "\0" \ 183 "nfsboot=" \ 184 "tftp $(loadaddr) vmImage;" \ 185 "run nfsargs;" \ 186 "run addip;" \ 187 "bootm" \ 188 "\0" 189#else 190# define NETWORK_ENV_SETTINGS 191#endif 192 193/* 194 * Console settings 195 */ 196#define CONFIG_BAUDRATE 57600 197#define CONFIG_LOADS_ECHO 1 198#define CONFIG_UART_CONSOLE 0 199 200/* 201 * I2C settings 202 * By default PF2 is used as SDA and PF3 as SCL on the Stamp board 203 * Located on the expansion connector on pins 86/85 204 * Note these pins are arbitrarily chosen because we aren't using 205 * them yet. You can (and probably should) change these values! 206 */ 207#ifdef CONFIG_SOFT_I2C 208#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF9 209#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF8 210#define CONFIG_SYS_I2C_SPEED 50000 211#define CONFIG_SYS_I2C_SLAVE 0xFE 212#endif 213 214/* 215 * Miscellaneous configurable options 216 */ 217#define CONFIG_RTC_BFIN 1 218 219/* 220 * Serial Flash Infomation 221 */ 222#define CONFIG_BFIN_SPI 223/* For the M25P64 SCK Should be Kept < 15Mhz */ 224#define CONFIG_ENV_SPI_MAX_HZ 15000000 225#define CONFIG_SF_DEFAULT_SPEED 15000000 226#define CONFIG_SPI_FLASH 227#define CONFIG_SPI_FLASH_STMICRO 228 229/* 230 * FLASH organization and environment definitions 231 */ 232 233#define CONFIG_EBIU_AMGCTL_VAL 0xFF 234#define CONFIG_EBIU_AMBCTL0_VAL 0xBBC3BBC3 235#define CONFIG_EBIU_AMBCTL1_VAL 0x99B39983 236#define CONFIG_EBIU_SDRRC_VAL 0x268 237#define CONFIG_EBIU_SDGCTL_VAL 0x911109 238 239/* Even though Rev C boards have Parallel Flash 240 * We aren't supporting it. Newer versions of the 241 * hardware don't support Parallel Flash at all. 242 */ 243#define CONFIG_SYS_NO_FLASH 244#undef CONFIG_CMD_IMLS 245#undef CONFIG_CMD_JFFS2 246#undef CONFIG_CMD_FLASH 247 248#endif 249