LXR uboot/include/configs/canyonlands.h

   1/*
   2 * (C) Copyright 2008
   3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4 *
   5 * This program is free software; you can redistribute it and/or
   6 * modify it under the terms of the GNU General Public License as
   7 * published by the Free Software Foundation; either version 2 of
   8 * the License, or (at your option) any later version.
   9 *
  10 * This program is distributed in the hope that it will be useful,
  11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 * GNU General Public License for more details.
  14 *
  15 * You should have received a copy of the GNU General Public License
  16 * along with this program; if not, write to the Free Software
  17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18 * MA 02111-1307 USA
  19 */
  20
  21/************************************************************************
  22 * canyonlands.h - configuration for Canyonlands (460EX)
  23 ***********************************************************************/
  24#ifndef __CONFIG_H
  25#define __CONFIG_H
  26
  27/*-----------------------------------------------------------------------
  28 * High Level Configuration Options
  29 *----------------------------------------------------------------------*/
  30/*
  31 * This config file is used for Canyonlands (460EX) Glacier (460GT)
  32 * and Arches dual (460GT)
  33 */
  34#ifdef CONFIG_CANYONLANDS
  35#define CONFIG_460EX            1       /* Specific PPC460EX            */
  36#define CONFIG_HOSTNAME         canyonlands
  37#else
  38#define CONFIG_460GT            1       /* Specific PPC460GT            */
  39#ifdef CONFIG_GLACIER
  40#define CONFIG_HOSTNAME         glacier
  41#else
  42#define CONFIG_HOSTNAME         arches
  43#define CONFIG_USE_NETDEV       eth1
  44#define CONFIG_BD_NUM_CPUS      2
  45#endif
  46#endif
  47
  48#define CONFIG_440              1
  49#define CONFIG_4xx              1       /* ... PPC4xx family */
  50
  51#ifndef CONFIG_SYS_TEXT_BASE
  52#define CONFIG_SYS_TEXT_BASE    0xFFF80000
  53#endif
  54
  55/*
  56 * Include common defines/options for all AMCC eval boards
  57 */
  58#include "amcc-common.h"
  59
  60#define CONFIG_SYS_CLK_FREQ     66666667        /* external freq to pll */
  61
  62#define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_early_init_f */
  63#define CONFIG_BOARD_EARLY_INIT_R       1       /* Call board_early_init_r */
  64#define CONFIG_MISC_INIT_R              1       /* Call misc_init_r */
  65#define CONFIG_BOARD_TYPES              1       /* support board types */
  66
  67/*-----------------------------------------------------------------------
  68 * Base addresses -- Note these are effective addresses where the
  69 * actual resources get mapped (not physical addresses)
  70 *----------------------------------------------------------------------*/
  71#define CONFIG_SYS_PCI_MEMBASE          0x80000000      /* mapped PCI memory    */
  72#define CONFIG_SYS_PCI_BASE             0xd0000000      /* internal PCI regs    */
  73#define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
  74
  75#define CONFIG_SYS_PCIE_MEMBASE 0xb0000000      /* mapped PCIe memory   */
  76#define CONFIG_SYS_PCIE_MEMSIZE 0x08000000      /* smallest incr for PCIe port */
  77#define CONFIG_SYS_PCIE_BASE            0xc4000000      /* PCIe UTL regs */
  78
  79#define CONFIG_SYS_PCIE0_CFGBASE        0xc0000000
  80#define CONFIG_SYS_PCIE1_CFGBASE        0xc1000000
  81#define CONFIG_SYS_PCIE0_XCFGBASE       0xc3000000
  82#define CONFIG_SYS_PCIE1_XCFGBASE       0xc3001000
  83
  84/*
  85 * BCSR bits as defined in the Canyonlands board user manual.
  86 */
  87#define BCSR_USBCTRL_OTG_RST    0x32
  88#define BCSR_USBCTRL_HOST_RST   0x01
  89#define BCSR_SELECT_PCIE        0x10
  90
  91#define CONFIG_SYS_PCIE0_UTLBASE        0xc08010000ULL  /* 36bit physical addr  */
  92
  93/* base address of inbound PCIe window */
  94#define CONFIG_SYS_PCIE_INBOUND_BASE    0x000000000ULL  /* 36bit physical addr  */
  95
  96/* EBC stuff */
  97#if !defined(CONFIG_ARCHES)
  98#define CONFIG_SYS_BCSR_BASE            0xE1000000
  99#define CONFIG_SYS_FLASH_BASE           0xFC000000      /* later mapped to this addr */
 100#define CONFIG_SYS_FLASH_SIZE           (64 << 20)
 101#else
 102#define CONFIG_SYS_FPGA_BASE            0xE1000000
 103#define CONFIG_SYS_CPLD_ADDR            (CONFIG_SYS_FPGA_BASE + 0x00080000)
 104#define CONFIG_SYS_CPLD_DATA            (CONFIG_SYS_FPGA_BASE + 0x00080002)
 105#define CONFIG_SYS_FLASH_BASE           0xFE000000      /* later mapped to this addr  */
 106#define CONFIG_SYS_FLASH_SIZE           (32 << 20)
 107#endif
 108
 109#define CONFIG_SYS_NAND_ADDR            0xE0000000
 110#define CONFIG_SYS_BOOT_BASE_ADDR       0xFF000000      /* EBC Boot Space: 0xFF000000 */
 111#define CONFIG_SYS_FLASH_BASE_PHYS_H    0x4
 112#define CONFIG_SYS_FLASH_BASE_PHYS_L    0xCC000000
 113#define CONFIG_SYS_FLASH_BASE_PHYS      (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) |    \
 114                                         (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
 115
 116#define CONFIG_SYS_OCM_BASE             0xE3000000      /* OCM: 64k             */
 117#define CONFIG_SYS_SRAM_BASE            0xE8000000      /* SRAM: 256k           */
 118#define CONFIG_SYS_SRAM_SIZE            (256 << 10)
 119#define CONFIG_SYS_LOCAL_CONF_REGS      0xEF000000
 120
 121#define CONFIG_SYS_AHB_BASE             0xE2000000      /* internal AHB peripherals     */
 122
 123/*-----------------------------------------------------------------------
 124 * Initial RAM & stack pointer (placed in OCM)
 125 *----------------------------------------------------------------------*/
 126#define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_BASE     /* OCM                  */
 127#define CONFIG_SYS_INIT_RAM_SIZE        (4 << 10)
 128#define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 129#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 130
 131/*-----------------------------------------------------------------------
 132 * Serial Port
 133 *----------------------------------------------------------------------*/
 134#define CONFIG_CONS_INDEX       1       /* Use UART0                    */
 135
 136/*-----------------------------------------------------------------------
 137 * Environment
 138 *----------------------------------------------------------------------*/
 139/*
 140 * Define here the location of the environment variables (FLASH).
 141 */
 142#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 143#define CONFIG_ENV_IS_IN_FLASH  1       /* use FLASH for environment vars */
 144#define CONFIG_SYS_NOR_CS               0       /* NOR chip connected to CSx */
 145#define CONFIG_SYS_NAND_CS              3       /* NAND chip connected to CSx */
 146#else
 147#define CONFIG_ENV_IS_IN_NAND   1       /* use NAND for environment vars  */
 148#define CONFIG_SYS_NOR_CS               3       /* NOR chip connected to CSx */
 149#define CONFIG_SYS_NAND_CS              0       /* NAND chip connected to CSx */
 150#define CONFIG_ENV_IS_EMBEDDED  1       /* use embedded environment */
 151#endif
 152
 153/*
 154 * IPL (Initial Program Loader, integrated inside CPU)
 155 * Will load first 4k from NAND (SPL) into cache and execute it from there.
 156 *
 157 * SPL (Secondary Program Loader)
 158 * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
 159 * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
 160 * controller and the NAND controller so that the special U-Boot image can be
 161 * loaded from NAND to SDRAM.
 162 *
 163 * NUB (NAND U-Boot)
 164 * This NAND U-Boot (NUB) is a special U-Boot version which can be started
 165 * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
 166 *
 167 * On 440EPx the SPL is copied to SDRAM before the NAND controller is
 168 * set up. While still running from cache, I experienced problems accessing
 169 * the NAND controller. sr - 2006-08-25
 170 *
 171 * This is the first official implementation of booting from 2k page sized
 172 * NAND devices (e.g. Micron 29F2G08AA 256Mbit * 8)
 173 */
 174#define CONFIG_SYS_NAND_BOOT_SPL_SRC    0xfffff000      /* SPL location               */
 175#define CONFIG_SYS_NAND_BOOT_SPL_SIZE   (4 << 10)       /* SPL size                   */
 176#define CONFIG_SYS_NAND_BOOT_SPL_DST    (CONFIG_SYS_OCM_BASE + (12 << 10)) /* Copy SPL here  */
 177#define CONFIG_SYS_NAND_U_BOOT_DST      0x01000000      /* Load NUB to this addr      */
 178#define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST      /* Start NUB from     */
 179                                                        /*   this addr        */
 180#define CONFIG_SYS_NAND_BOOT_SPL_DELTA  (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
 181
 182/*
 183 * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
 184 */
 185#define CONFIG_SYS_NAND_U_BOOT_OFFS     (128 << 10)     /* Offset to RAM U-Boot image */
 186#define CONFIG_SYS_NAND_U_BOOT_SIZE     (1 << 20)       /* Size of RAM U-Boot image   */
 187
 188/*
 189 * Now the NAND chip has to be defined (no autodetection used!)
 190 */
 191#define CONFIG_SYS_NAND_PAGE_SIZE       (2 << 10)       /* NAND chip page size        */
 192#define CONFIG_SYS_NAND_BLOCK_SIZE      (128 << 10)     /* NAND chip block size       */
 193#define CONFIG_SYS_NAND_PAGE_COUNT      (CONFIG_SYS_NAND_BLOCK_SIZE / CONFIG_SYS_NAND_PAGE_SIZE)
 194                                                /* NAND chip page count       */
 195#define CONFIG_SYS_NAND_BAD_BLOCK_POS   0               /* Location of bad block marker*/
 196#define CONFIG_SYS_NAND_5_ADDR_CYCLE                    /* Fifth addr used (<=128MB)  */
 197
 198#define CONFIG_SYS_NAND_ECCSIZE 256
 199#define CONFIG_SYS_NAND_ECCBYTES        3
 200#define CONFIG_SYS_NAND_OOBSIZE 64
 201#define CONFIG_SYS_NAND_ECCPOS          {40, 41, 42, 43, 44, 45, 46, 47, \
 202                                 48, 49, 50, 51, 52, 53, 54, 55, \
 203                                 56, 57, 58, 59, 60, 61, 62, 63}
 204
 205#ifdef CONFIG_ENV_IS_IN_NAND
 206/*
 207 * For NAND booting the environment is embedded in the U-Boot image. Please take
 208 * look at the file board/amcc/canyonlands/u-boot-nand.lds for details.
 209 */
 210#define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 211#define CONFIG_ENV_OFFSET               (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
 212#define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
 213#endif
 214
 215/*-----------------------------------------------------------------------
 216 * FLASH related
 217 *----------------------------------------------------------------------*/
 218#define CONFIG_SYS_FLASH_CFI                    /* The flash is CFI compatible  */
 219#define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver        */
 220#define CONFIG_SYS_FLASH_CFI_AMD_RESET  1       /* Use AMD (Spansion) reset cmd */
 221
 222#define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
 223#define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 224#define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip    */
 225
 226#define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 227#define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 228
 229#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
 230#define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 231
 232#ifdef CONFIG_ENV_IS_IN_FLASH
 233#define CONFIG_ENV_SECT_SIZE    0x20000         /* size of one complete sector  */
 234#define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 235#define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
 236
 237/* Address and size of Redundant Environment Sector     */
 238#define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
 239#define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 240#endif /* CONFIG_ENV_IS_IN_FLASH */
 241
 242/*-----------------------------------------------------------------------
 243 * NAND-FLASH related
 244 *----------------------------------------------------------------------*/
 245#define CONFIG_SYS_MAX_NAND_DEVICE      1
 246#define CONFIG_SYS_NAND_BASE            (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
 247#define CONFIG_SYS_NAND_SELECT_DEVICE  1        /* nand driver supports mutipl. chips   */
 248
 249/*------------------------------------------------------------------------------
 250 * DDR SDRAM
 251 *----------------------------------------------------------------------------*/
 252#if !defined(CONFIG_NAND_U_BOOT)
 253#if !defined(CONFIG_ARCHES)
 254/*
 255 * NAND booting U-Boot version uses a fixed initialization, since the whole
 256 * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot
 257 * code.
 258 */
 259#define CONFIG_SPD_EEPROM       1       /* Use SPD EEPROM for setup     */
 260#define SPD_EEPROM_ADDRESS      {0x50, 0x51}    /* SPD i2c spd addresses*/
 261#define CONFIG_DDR_ECC          1       /* with ECC support             */
 262#define CONFIG_DDR_RQDC_FIXED   0x80000038 /* fixed value for RQDC      */
 263
 264#else /* defined(CONFIG_ARCHES) */
 265
 266#define CONFIG_AUTOCALIB        "silent\0"      /* default is non-verbose    */
 267
 268#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION       /* IBM DDR autocalibration   */
 269#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION        /* dynamic DDR autocal debug */
 270#undef CONFIG_PPC4xx_DDR_METHOD_A
 271
 272/* DDR1/2 SDRAM Device Control Register Data Values */
 273/* Memory Queue */
 274#define CONFIG_SYS_SDRAM_R0BAS          0x0000f000
 275#define CONFIG_SYS_SDRAM_R1BAS          0x00000000
 276#define CONFIG_SYS_SDRAM_R2BAS          0x00000000
 277#define CONFIG_SYS_SDRAM_R3BAS          0x00000000
 278#define CONFIG_SYS_SDRAM_PLBADDULL      0x00000000
 279#define CONFIG_SYS_SDRAM_PLBADDUHB      0x00000008
 280#define CONFIG_SYS_SDRAM_CONF1LL        0x00001080
 281#define CONFIG_SYS_SDRAM_CONF1HB        0x00001080
 282#define CONFIG_SYS_SDRAM_CONFPATHB      0x10a68000
 283
 284/* SDRAM Controller */
 285#define CONFIG_SYS_SDRAM0_MB0CF         0x00000701
 286#define CONFIG_SYS_SDRAM0_MB1CF         0x00000000
 287#define CONFIG_SYS_SDRAM0_MB2CF         0x00000000
 288#define CONFIG_SYS_SDRAM0_MB3CF         0x00000000
 289#define CONFIG_SYS_SDRAM0_MCOPT1        0x05322000
 290#define CONFIG_SYS_SDRAM0_MCOPT2        0x00000000
 291#define CONFIG_SYS_SDRAM0_MODT0         0x01000000
 292#define CONFIG_SYS_SDRAM0_MODT1         0x00000000
 293#define CONFIG_SYS_SDRAM0_MODT2         0x00000000
 294#define CONFIG_SYS_SDRAM0_MODT3         0x00000000
 295#define CONFIG_SYS_SDRAM0_CODT          0x00800021
 296#define CONFIG_SYS_SDRAM0_RTR           0x06180000
 297#define CONFIG_SYS_SDRAM0_INITPLR0      0xb5380000
 298#define CONFIG_SYS_SDRAM0_INITPLR1      0x82100400
 299#define CONFIG_SYS_SDRAM0_INITPLR2      0x80820000
 300#define CONFIG_SYS_SDRAM0_INITPLR3      0x80830000
 301#define CONFIG_SYS_SDRAM0_INITPLR4      0x80810040
 302#define CONFIG_SYS_SDRAM0_INITPLR5      0x80800532
 303#define CONFIG_SYS_SDRAM0_INITPLR6      0x82100400
 304#define CONFIG_SYS_SDRAM0_INITPLR7      0x8a080000
 305#define CONFIG_SYS_SDRAM0_INITPLR8      0x8a080000
 306#define CONFIG_SYS_SDRAM0_INITPLR9      0x8a080000
 307#define CONFIG_SYS_SDRAM0_INITPLR10     0x8a080000
 308#define CONFIG_SYS_SDRAM0_INITPLR11     0x80000432
 309#define CONFIG_SYS_SDRAM0_INITPLR12     0x808103c0
 310#define CONFIG_SYS_SDRAM0_INITPLR13     0x80810040
 311#define CONFIG_SYS_SDRAM0_INITPLR14     0x00000000
 312#define CONFIG_SYS_SDRAM0_INITPLR15     0x00000000
 313#define CONFIG_SYS_SDRAM0_RQDC          0x80000038
 314#define CONFIG_SYS_SDRAM0_RFDC          0x00000257
 315#define CONFIG_SYS_SDRAM0_RDCC          0x40000000
 316#define CONFIG_SYS_SDRAM0_DLCR          0x03000091
 317#define CONFIG_SYS_SDRAM0_CLKTR         0x40000000
 318#define CONFIG_SYS_SDRAM0_WRDTR         0x82000823
 319#define CONFIG_SYS_SDRAM0_SDTR1         0x80201000
 320#define CONFIG_SYS_SDRAM0_SDTR2         0x42204243
 321#define CONFIG_SYS_SDRAM0_SDTR3         0x090c0d1a
 322#define CONFIG_SYS_SDRAM0_MMODE         0x00000432
 323#define CONFIG_SYS_SDRAM0_MEMODE        0x00000004
 324#endif  /* !defined(CONFIG_ARCHES) */
 325#endif  /* !defined(CONFIG_NAND_U_BOOT) */
 326
 327#define CONFIG_SYS_MBYTES_SDRAM 512     /* 512MB                        */
 328
 329/*-----------------------------------------------------------------------
 330 * I2C
 331 *----------------------------------------------------------------------*/
 332#define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed                    */
 333
 334#define CONFIG_SYS_I2C_MULTI_EEPROMS
 335#define CONFIG_SYS_I2C_EEPROM_ADDR              (0xa8>>1)
 336#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 337#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 338#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 339
 340/* I2C bootstrap EEPROM */
 341#if defined(CONFIG_ARCHES)
 342#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR       0x54
 343#else
 344#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR       0x52
 345#endif
 346#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET     0
 347#define CONFIG_4xx_CONFIG_BLOCKSIZE             16
 348
 349/* I2C SYSMON (LM75, AD7414 is almost compatible)                       */
 350#define CONFIG_DTT_LM75         1               /* ON Semi's LM75       */
 351#define CONFIG_DTT_AD7414       1               /* use AD7414           */
 352#define CONFIG_DTT_SENSORS      {0}             /* Sensor addresses     */
 353#define CONFIG_SYS_DTT_MAX_TEMP 70
 354#define CONFIG_SYS_DTT_LOW_TEMP -30
 355#define CONFIG_SYS_DTT_HYSTERESIS       3
 356
 357#if defined(CONFIG_ARCHES)
 358#define CONFIG_SYS_I2C_DTT_ADDR 0x4a            /* AD7414 I2C address   */
 359#endif
 360
 361#if !defined(CONFIG_ARCHES)
 362/* RTC configuration */
 363#define CONFIG_RTC_M41T62       1
 364#define CONFIG_SYS_I2C_RTC_ADDR 0x68
 365#endif
 366
 367/*-----------------------------------------------------------------------
 368 * Ethernet
 369 *----------------------------------------------------------------------*/
 370#define CONFIG_IBM_EMAC4_V4     1
 371
 372#define CONFIG_HAS_ETH0
 373#define CONFIG_HAS_ETH1
 374
 375#if !defined(CONFIG_ARCHES)
 376#define CONFIG_PHY_ADDR         0       /* PHY address, See schematics  */
 377#define CONFIG_PHY1_ADDR        1
 378/* Only Glacier (460GT) has 4 EMAC interfaces */
 379#ifdef CONFIG_460GT
 380#define CONFIG_PHY2_ADDR        2
 381#define CONFIG_PHY3_ADDR        3
 382#define CONFIG_HAS_ETH2
 383#define CONFIG_HAS_ETH3
 384#endif
 385
 386#else /* defined(CONFIG_ARCHES) */
 387
 388#define CONFIG_FIXED_PHY        0xFFFFFFFF
 389#define CONFIG_PHY_ADDR         CONFIG_FIXED_PHY
 390#define CONFIG_PHY1_ADDR        0
 391#define CONFIG_PHY2_ADDR        1
 392#define CONFIG_HAS_ETH2
 393
 394#define CONFIG_SYS_FIXED_PHY_PORT(devnum, speed, duplex) \
 395                {devnum, speed, duplex}
 396#define CONFIG_SYS_FIXED_PHY_PORTS \
 397                CONFIG_SYS_FIXED_PHY_PORT(0, 1000, FULL)
 398
 399#define CONFIG_M88E1112_PHY
 400
 401/*
 402 * For the GPCS_PHYx_ADDR PHY address, choose some PHY address not
 403 * used by CONFIG_PHYx_ADDR
 404 */
 405#define CONFIG_GPCS_PHY_ADDR    0xA
 406#define CONFIG_GPCS_PHY1_ADDR   0xB
 407#define CONFIG_GPCS_PHY2_ADDR   0xC
 408#endif  /* !defined(CONFIG_ARCHES) */
 409
 410#define CONFIG_PHY_RESET        1       /* reset phy upon startup       */
 411#define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 412#define CONFIG_PHY_DYNAMIC_ANEG 1
 413
 414/*-----------------------------------------------------------------------
 415 * USB-OHCI
 416 *----------------------------------------------------------------------*/
 417/* Only Canyonlands (460EX) has USB */
 418#ifdef CONFIG_460EX
 419#define CONFIG_USB_OHCI_NEW
 420#define CONFIG_USB_STORAGE
 421#undef CONFIG_SYS_OHCI_BE_CONTROLLER            /* 460EX has little endian descriptors  */
 422#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS /* 460EX has little endian register     */
 423#define CONFIG_SYS_OHCI_USE_NPS         /* force NoPowerSwitching mode          */
 424#define CONFIG_SYS_USB_OHCI_REGS_BASE   (CONFIG_SYS_AHB_BASE | 0xd0000)
 425#define CONFIG_SYS_USB_OHCI_SLOT_NAME   "ppc440"
 426#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
 427#define CONFIG_SYS_USB_OHCI_BOARD_INIT
 428#endif
 429
 430/*
 431 * Default environment variables
 432 */
 433#if !defined(CONFIG_ARCHES)
 434#define CONFIG_EXTRA_ENV_SETTINGS                                       \
 435        CONFIG_AMCC_DEF_ENV                                             \
 436        CONFIG_AMCC_DEF_ENV_POWERPC                                     \
 437        CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
 438        CONFIG_AMCC_DEF_ENV_NAND_UPD                                    \
 439        "kernel_addr=fc000000\0"                                        \
 440        "fdt_addr=fc1e0000\0"                                           \
 441        "ramdisk_addr=fc200000\0"                                       \
 442        "pciconfighost=1\0"                                             \
 443        "pcie_mode=RP:RP\0"                                             \
 444        ""
 445#else /* defined(CONFIG_ARCHES) */
 446#define CONFIG_EXTRA_ENV_SETTINGS                                       \
 447        CONFIG_AMCC_DEF_ENV                                             \
 448        CONFIG_AMCC_DEF_ENV_POWERPC                                     \
 449        CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
 450        "kernel_addr=fe000000\0"                                        \
 451        "fdt_addr=fe1e0000\0"                                           \
 452        "ramdisk_addr=fe200000\0"                                       \
 453        "pciconfighost=1\0"                                             \
 454        "pcie_mode=RP:RP\0"                                             \
 455        "ethprime=ppc_4xx_eth1\0"                                       \
 456        ""
 457#endif  /* !defined(CONFIG_ARCHES) */
 458
 459/*
 460 * Commands additional to the ones defined in amcc-common.h
 461 */
 462#define CONFIG_CMD_CHIP_CONFIG
 463#if defined(CONFIG_ARCHES)
 464#define CONFIG_CMD_DTT
 465#define CONFIG_CMD_PCI
 466#define CONFIG_CMD_SDRAM
 467#elif defined(CONFIG_CANYONLANDS)
 468#define CONFIG_CMD_DATE
 469#define CONFIG_CMD_DTT
 470#define CONFIG_CMD_EXT2
 471#define CONFIG_CMD_FAT
 472#define CONFIG_CMD_NAND
 473#define CONFIG_CMD_PCI
 474#define CONFIG_CMD_SATA
 475#define CONFIG_CMD_SDRAM
 476#define CONFIG_CMD_SNTP
 477#define CONFIG_CMD_USB
 478#elif defined(CONFIG_GLACIER)
 479#define CONFIG_CMD_DATE
 480#define CONFIG_CMD_DTT
 481#define CONFIG_CMD_NAND
 482#define CONFIG_CMD_PCI
 483#define CONFIG_CMD_SDRAM
 484#define CONFIG_CMD_SNTP
 485#else
 486#error "board type not defined"
 487#endif
 488
 489/* Partitions */
 490#define CONFIG_MAC_PARTITION
 491#define CONFIG_DOS_PARTITION
 492#define CONFIG_ISO_PARTITION
 493
 494/*-----------------------------------------------------------------------
 495 * PCI stuff
 496 *----------------------------------------------------------------------*/
 497/* General PCI */
 498#define CONFIG_PCI                      /* include pci support          */
 499#define CONFIG_PCI_PNP                  /* do pci plug-and-play   */
 500#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 501#define CONFIG_PCI_CONFIG_HOST_BRIDGE
 502
 503/* Board-specific PCI */
 504#define CONFIG_SYS_PCI_TARGET_INIT              /* let board init pci target    */
 505#undef  CONFIG_SYS_PCI_MASTER_INIT
 506
 507#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014   /* IBM                          */
 508#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe   /* Whatever                     */
 509
 510#ifdef CONFIG_460GT
 511#if defined(CONFIG_ARCHES)
 512/*-----------------------------------------------------------------------
 513 * RapidIO I/O and Registers
 514 *----------------------------------------------------------------------*/
 515#define CONFIG_RAPIDIO
 516#define CONFIG_SYS_460GT_SRIO_ERRATA_1
 517
 518#define SRGPL0_REG_BAR          0x0000000DAA000000ull   /*  16MB */
 519#define SRGPL0_CFG_BAR          0x0000000DAB000000ull   /*  16MB */
 520#define SRGPL0_MNT_BAR          0x0000000DAC000000ull   /*  16MB */
 521#define SRGPL0_MSG_BAR          0x0000000DAD000000ull   /*  16MB */
 522#define SRGPL0_OUT_BAR          0x0000000DB0000000ull   /* 256MB */
 523
 524#define CONFIG_SYS_SRGPL0_REG_BAR       0xAA000000              /*  16MB */
 525#define CONFIG_SYS_SRGPL0_CFG_BAR       0xAB000000              /*  16MB */
 526#define CONFIG_SYS_SRGPL0_MNT_BAR       0xAC000000              /*  16MB */
 527#define CONFIG_SYS_SRGPL0_MSG_BAR       0xAD000000              /*  16MB */
 528
 529#define CONFIG_SYS_I2ODMA_BASE          0xCF000000
 530#define CONFIG_SYS_I2ODMA_PHYS_ADDR     0x0000000400100000ull
 531
 532#define CONFIG_PPC4XX_RAPIDIO_PROMISCUOUS_MODE
 533#undef CONFIG_PPC4XX_RAPIDIO_DEBUG
 534#undef CONFIG_PPC4XX_RAPIDIO_IN_BAR_USE_OCM
 535#define CONFIG_PPC4XX_RAPIDIO_USE_HB_PLB
 536#undef CONFIG_PPC4XX_RAPIDIO_LOOPBACK
 537#endif /* CONFIG_ARCHES */
 538#endif /* CONFIG_460GT */
 539
 540/*
 541 * SATA driver setup
 542 */
 543#ifdef CONFIG_CMD_SATA
 544#define CONFIG_SATA_DWC
 545#define CONFIG_LIBATA
 546#define SATA_BASE_ADDR          0xe20d1000      /* PPC460EX SATA Base Address */
 547#define SATA_DMA_REG_ADDR       0xe20d0800      /* PPC460EX SATA Base Address */
 548#define CONFIG_SYS_SATA_MAX_DEVICE      1       /* SATA MAX DEVICE */
 549/* Convert sectorsize to wordsize */
 550#define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2)
 551#endif
 552
 553/*-----------------------------------------------------------------------
 554 * External Bus Controller (EBC) Setup
 555 *----------------------------------------------------------------------*/
 556
 557/*
 558 * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
 559 * boot EBC mapping only supports a maximum of 16MBytes
 560 * (4.ff00.0000 - 4.ffff.ffff).
 561 * To solve this problem, the FLASH has to get remapped to another
 562 * EBC address which accepts bigger regions:
 563 *
 564 * 0xfc00.0000 -> 4.cc00.0000
 565 *
 566 * Arches has 32MBytes of NOR FLASH (Spansion 29GL256), it will be
 567 * remapped to:
 568 *
 569 * 0xfe00.0000 -> 4.ce00.0000
 570 */
 571
 572#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
 573/* Memory Bank 3 (NOR-FLASH) initialization                                     */
 574#define CONFIG_SYS_EBC_PB3AP            0x10055e00
 575#define CONFIG_SYS_EBC_PB3CR            (CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000)
 576
 577/* Memory Bank 0 (NAND-FLASH) initialization                                            */
 578#define CONFIG_SYS_EBC_PB0AP            0x018003c0
 579#define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/
 580#else
 581/* Memory Bank 0 (NOR-FLASH) initialization                                     */
 582#define CONFIG_SYS_EBC_PB0AP            0x10055e00
 583#define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000)
 584
 585#if !defined(CONFIG_ARCHES)
 586/* Memory Bank 3 (NAND-FLASH) initialization                                            */
 587#define CONFIG_SYS_EBC_PB3AP            0x018003c0
 588#define CONFIG_SYS_EBC_PB3CR            (CONFIG_SYS_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/
 589#endif
 590#endif  /*defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
 591
 592#if !defined(CONFIG_ARCHES)
 593/* Memory Bank 2 (CPLD) initialization                                          */
 594#define CONFIG_SYS_EBC_PB2AP            0x00804240
 595#define CONFIG_SYS_EBC_PB2CR            (CONFIG_SYS_BCSR_BASE | 0x18000) /* BAS=CPLD,BS=1M,BU=RW,BW=32bit */
 596
 597#else /* defined(CONFIG_ARCHES) */
 598
 599/* Memory Bank 1 (FPGA) initialization  */
 600#define CONFIG_SYS_EBC_PB1AP            0x7f8ffe80
 601#define CONFIG_SYS_EBC_PB1CR            (CONFIG_SYS_FPGA_BASE | 0x3a000) /* BAS=FPGA,BS=2MB,BU=R/W,BW=16bit*/
 602#endif  /* !defined(CONFIG_ARCHES) */
 603
 604#define CONFIG_SYS_EBC_CFG              0xbfc00000
 605
 606/*
 607 * Arches doesn't use PerCS3 but GPIO43, so let's configure the GPIO
 608 * pin multiplexing correctly
 609 */
 610#if defined(CONFIG_ARCHES)
 611#define GPIO43_USE              GPIO_SEL        /* On Arches this pin is used as GPIO */
 612#else
 613#define GPIO43_USE              GPIO_ALT1       /* On Glacier this pin is used as ALT1 -> PerCS3 */
 614#endif
 615
 616/*
 617 * PPC4xx GPIO Configuration
 618 */
 619#ifdef CONFIG_460EX
 620/* 460EX: Use USB configuration */
 621#define CONFIG_SYS_4xx_GPIO_TABLE { /*    Out             GPIO  Alternate1      Alternate2      Alternate3 */ \
 622{                                                                                       \
 623/* GPIO Core 0 */                                                                       \
 624{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0)      USB2HostD(0)    */      \
 625{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1)      USB2HostD(1)    */      \
 626{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2)      USB2HostD(2)    */      \
 627{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3)      USB2HostD(3)    */      \
 628{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4)      USB2HostD(4)    */      \
 629{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5)      USB2HostD(5)    */      \
 630{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6)      USB2HostD(6)    */      \
 631{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7)      USB2HostD(7)    */      \
 632{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0)      USB2OTGD(0)     */      \
 633{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1)      USB2OTGD(1)     */      \
 634{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2)     USB2OTGD(2)     */      \
 635{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3)     USB2OTGD(3)     */      \
 636{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4)     USB2OTGD(4)     */      \
 637{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5)     USB2OTGD(5)     */      \
 638{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6)     USB2OTGD(6)     */      \
 639{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7)     USB2OTGD(7)     */      \
 640{GPIO0_BASE, GPIO_IN , GPIO_SEL,  GPIO_OUT_0}, /* GPIO16 GMC1TxER       USB2HostStop    */      \
 641{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD         USB2HostNext    */      \
 642{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER       USB2HostDir     */      \
 643{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO19 GMC1TxEN       USB2OTGStop     */      \
 644{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS        USB2OTGNext     */      \
 645{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV       USB2OTGDir      */      \
 646{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY                          */      \
 647{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN                          */      \
 648{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN                          */      \
 649{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE                          */      \
 650{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE                          */      \
 651{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0)                         */      \
 652{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1)                         */      \
 653{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2)                         */      \
 654{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0        DMAReq2         IRQ(7)*/ \
 655{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1        DMAAck2         IRQ(8)*/ \
 656},                                                                                      \
 657{                                                                                       \
 658/* GPIO Core 1 */                                                                       \
 659{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2        EOT2/TC2        IRQ(9)*/ \
 660{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3        DMAReq3         IRQ(4)*/ \
 661{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N    UART1_DSR_CTS_N UART2_SOUT*/ \
 662{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
 663{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3       UART3_SIN*/ \
 664{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N    EOT3/TC3        UART3_SOUT*/ \
 665{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N    UART1_SOUT      */      \
 666{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N     UART1_SIN       */      \
 667{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3)                         */      \
 668{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1)                          */      \
 669{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2)                          */      \
 670{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3)          DMAReq1         IRQ(10)*/ \
 671{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4)          DMAAck1         IRQ(11)*/ \
 672{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5)          EOT/TC1         IRQ(12)*/ \
 673{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5)     DMAReq0         IRQ(13)*/ \
 674{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6)     DMAAck0         IRQ(14)*/ \
 675{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7)     EOT/TC0         IRQ(15)*/ \
 676{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49  Unselect via TraceSelect Bit  */      \
 677{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit  */      \
 678{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit  */      \
 679{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit  */      \
 680{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit  */      \
 681{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit  */      \
 682{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55  Unselect via TraceSelect Bit  */      \
 683{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit  */      \
 684{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57  Unselect via TraceSelect Bit  */      \
 685{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit  */      \
 686{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit  */      \
 687{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit  */      \
 688{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit  */      \
 689{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit  */      \
 690{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit  */      \
 691}                                                                                       \
 692}
 693#else
 694/* 460GT: Use EMAC2+3 configuration */
 695#define CONFIG_SYS_4xx_GPIO_TABLE { /*    Out             GPIO  Alternate1      Alternate2      Alternate3 */ \
 696{                                                                                       \
 697/* GPIO Core 0 */                                                                       \
 698{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0)      USB2HostD(0)    */      \
 699{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1)      USB2HostD(1)    */      \
 700{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2)      USB2HostD(2)    */      \
 701{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3)      USB2HostD(3)    */      \
 702{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4)      USB2HostD(4)    */      \
 703{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5)      USB2HostD(5)    */      \
 704{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6)      USB2HostD(6)    */      \
 705{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7)      USB2HostD(7)    */      \
 706{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0)      USB2OTGD(0)     */      \
 707{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1)      USB2OTGD(1)     */      \
 708{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2)     USB2OTGD(2)     */      \
 709{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3)     USB2OTGD(3)     */      \
 710{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4)     USB2OTGD(4)     */      \
 711{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5)     USB2OTGD(5)     */      \
 712{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6)     USB2OTGD(6)     */      \
 713{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7)     USB2OTGD(7)     */      \
 714{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMC1TxER       USB2HostStop    */      \
 715{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD         USB2HostNext    */      \
 716{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER       USB2HostDir     */      \
 717{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMC1TxEN       USB2OTGStop     */      \
 718{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS        USB2OTGNext     */      \
 719{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV       USB2OTGDir      */      \
 720{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY                          */      \
 721{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN                          */      \
 722{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN                          */      \
 723{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE                          */      \
 724{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE                          */      \
 725{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0)                         */      \
 726{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1)                         */      \
 727{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2)                         */      \
 728{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0        DMAReq2         IRQ(7)*/ \
 729{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1        DMAAck2         IRQ(8)*/ \
 730},                                                                                      \
 731{                                                                                       \
 732/* GPIO Core 1 */                                                                       \
 733{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2        EOT2/TC2        IRQ(9)*/ \
 734{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3        DMAReq3         IRQ(4)*/ \
 735{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N    UART1_DSR_CTS_N UART2_SOUT*/ \
 736{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
 737{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3       UART3_SIN*/ \
 738{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N    EOT3/TC3        UART3_SOUT*/ \
 739{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N    UART1_SOUT      */      \
 740{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N     UART1_SIN       */      \
 741{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3)                         */      \
 742{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1)                          */      \
 743{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2)                          */      \
 744{GPIO1_BASE, GPIO_OUT, GPIO43_USE, GPIO_OUT_0},/* GPIO43 CS(3)          DMAReq1         IRQ(10)*/ \
 745{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4)          DMAAck1         IRQ(11)*/ \
 746{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5)          EOT/TC1         IRQ(12)*/ \
 747{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5)     DMAReq0         IRQ(13)*/ \
 748{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6)     DMAAck0         IRQ(14)*/ \
 749{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7)     EOT/TC0         IRQ(15)*/ \
 750{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49  Unselect via TraceSelect Bit  */      \
 751{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit  */      \
 752{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit  */      \
 753{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit  */      \
 754{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit  */      \
 755{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit  */      \
 756{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55  Unselect via TraceSelect Bit  */      \
 757{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit  */      \
 758{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57  Unselect via TraceSelect Bit  */      \
 759{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit  */      \
 760{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit  */      \
 761{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit  */      \
 762{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit  */      \
 763{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit  */      \
 764{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit  */      \
 765}                                                                                       \
 766}
 767#endif
 768
 769#endif  /* __CONFIG_H */
 770