1/* 2 * (C) Copyright 2003 3 * Martin Winistoerfer, martinwinistoerfer@gmx.ch. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, 21 */ 22 23/* 24 * File: cmi_mpc5xx.h 25 * 26 * Discription: Config header file for cmi 27 * board using an MPC5xx CPU 28 * 29 */ 30 31#ifndef __CONFIG_H 32#define __CONFIG_H 33 34/* 35 * High Level Configuration Options 36 */ 37 38#define CONFIG_MPC555 1 /* This is an MPC555 CPU */ 39#define CONFIG_CMI 1 /* Using the customized cmi board */ 40 41#define CONFIG_SYS_TEXT_BASE 0x02000000 /* Boot from flash at location 0x00000000 */ 42 43/* Serial Console Configuration */ 44#define CONFIG_5xx_CONS_SCI1 45#undef CONFIG_5xx_CONS_SCI2 46 47#define CONFIG_BAUDRATE 57600 48 49 50/* 51 * BOOTP options 52 */ 53#define CONFIG_BOOTP_BOOTFILESIZE 54#define CONFIG_BOOTP_BOOTPATH 55#define CONFIG_BOOTP_GATEWAY 56#define CONFIG_BOOTP_HOSTNAME 57 58 59/* 60 * Command line configuration. 61 */ 62#include <config_cmd_default.h> 63 64#undef CONFIG_CMD_NET /* disabeled - causes compile errors */ 65#undef CONFIG_CMD_NFS 66 67#define CONFIG_CMD_MEMORY 68#define CONFIG_CMD_LOADB 69#define CONFIG_CMD_REGINFO 70#define CONFIG_CMD_FLASH 71#define CONFIG_CMD_LOADS 72#define CONFIG_CMD_ASKENV 73#define CONFIG_CMD_BDI 74#define CONFIG_CMD_CONSOLE 75#define CONFIG_CMD_SAVEENV 76#define CONFIG_CMD_RUN 77#define CONFIG_CMD_IMI 78 79 80#if 0 81#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ 82#else 83#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 84#endif 85#define CONFIG_BOOTCOMMAND "go 02034004" /* autoboot command */ 86 87#define CONFIG_BOOTARGS "" /* Assuming OS Image in 4 flash sector at offset 4004 */ 88 89#define CONFIG_WATCHDOG /* turn on platform specific watchdog */ 90 91#define CONFIG_STATUS_LED 1 /* Enable status led */ 92 93#define CONFIG_LOADS_ECHO 1 /* Echo on for serial download */ 94 95/* 96 * Miscellaneous configurable options 97 */ 98 99#define CONFIG_SYS_LONGHELP /* undef to save memory */ 100#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 101#if defined(CONFIG_CMD_KGDB) 102#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 103#else 104#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 105#endif 106#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 107#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 108#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 109 110#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ 111#define CONFIG_SYS_MEMTEST_END 0x000fa000 /* 1 MB in SRAM */ 112 113#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 114 115#define CONFIG_SYS_HZ 1000 /* Decrementer freq: 1 ms ticks */ 116 117#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 1250000 } 118 119 120/* 121 * Low Level Configuration Settings 122 */ 123 124/* 125 * Internal Memory Mapped (This is not the IMMR content) 126 */ 127#define CONFIG_SYS_IMMR 0x01000000 /* Physical start adress of internal memory map */ 128 129/* 130 * Definitions for initial stack pointer and data area 131 */ 132#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */ 133#define CONFIG_SYS_INIT_RAM_SIZE (CONFIG_SYS_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */ 134#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_RAM_ADDR) - GENERATED_GBL_DATA_SIZE) /* Offset from the beginning of ram */ 135#define CONFIG_SYS_INIT_SP_ADDR 0x013fa000 /* Physical start adress of inital stack */ 136 137/* 138 * Start addresses for the final memory configuration 139 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 140 */ 141#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */ 142#define CONFIG_SYS_FLASH_BASE 0x02000000 /* External flash */ 143#define PLD_BASE 0x03000000 /* PLD */ 144#define ANYBUS_BASE 0x03010000 /* Anybus Module */ 145 146#define CONFIG_SYS_RESET_ADRESS 0x01000000 /* Adress which causes reset */ 147#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* CONFIG_SYS_TEXT_BASE is defined in the board config.mk file. */ 148 /* This adress is given to the linker with -Ttext to */ 149 /* locate the text section at this adress. */ 150#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ 151#define CONFIG_SYS_MALLOC_LEN (64 << 10) /* Reserve 128 kB for malloc() */ 152 153/* 154 * For booting Linux, the board info and command line data 155 * have to be in the first 8 MB of memory, since this is 156 * the maximum mapped by the Linux kernel during initialization. 157 */ 158#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 159 160 161/*----------------------------------------------------------------------- 162 * FLASH organization 163 *----------------------------------------------------------------------- 164 * 165 */ 166 167#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of memory banks */ 168#define CONFIG_SYS_MAX_FLASH_SECT 64 /* Max number of sectors on one chip */ 169#define CONFIG_SYS_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */ 170#define CONFIG_SYS_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */ 171#define CONFIG_SYS_FLASH_PROTECTION 1 /* Physically section protection on */ 172 173#define CONFIG_ENV_IS_IN_FLASH 1 174 175#ifdef CONFIG_ENV_IS_IN_FLASH 176#define CONFIG_ENV_OFFSET 0x00020000 /* Environment starts at this adress */ 177#define CONFIG_ENV_SIZE 0x00010000 /* Set whole sector as env */ 178#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ 179#endif 180 181/*----------------------------------------------------------------------- 182 * SYPCR - System Protection Control 183 * SYPCR can only be written once after reset! 184 *----------------------------------------------------------------------- 185 * SW Watchdog freeze 186 */ 187#if defined(CONFIG_WATCHDOG) 188#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 189 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 190#else 191#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 192 SYPCR_SWP) 193#endif /* CONFIG_WATCHDOG */ 194 195/*----------------------------------------------------------------------- 196 * TBSCR - Time Base Status and Control 197 *----------------------------------------------------------------------- 198 * Clear Reference Interrupt Status, Timebase freezing enabled 199 */ 200#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 201 202/*----------------------------------------------------------------------- 203 * PISCR - Periodic Interrupt Status and Control 204 *----------------------------------------------------------------------- 205 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 206 */ 207#define CONFIG_SYS_PISCR (PISCR_PITF) 208 209/*----------------------------------------------------------------------- 210 * SCCR - System Clock and reset Control Register 211 *----------------------------------------------------------------------- 212 * Set clock output, timebase and RTC source and divider, 213 * power management and some other internal clocks 214 */ 215#define SCCR_MASK SCCR_EBDF00 216#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_RTDIV | SCCR_RTSEL | \ 217 SCCR_COM00 | SCCR_DFNL000 | SCCR_DFNH000) 218 219/*----------------------------------------------------------------------- 220 * SIUMCR - SIU Module Configuration 221 *----------------------------------------------------------------------- 222 * Data show cycle 223 */ 224#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00) /* Disable data show cycle */ 225 226/*----------------------------------------------------------------------- 227 * PLPRCR - PLL, Low-Power, and Reset Control Register 228 *----------------------------------------------------------------------- 229 * Set all bits to 40 Mhz 230 * 231 */ 232#define CONFIG_SYS_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */ 233#define CONFIG_SYS_PLPRCR (PLPRCR_MF_9 | PLPRCR_DIVF_0) 234 235 236/*----------------------------------------------------------------------- 237 * UMCR - UIMB Module Configuration Register 238 *----------------------------------------------------------------------- 239 * 240 */ 241#define CONFIG_SYS_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */ 242 243/*----------------------------------------------------------------------- 244 * ICTRL - I-Bus Support Control Register 245 */ 246#define CONFIG_SYS_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */ 247 248/*----------------------------------------------------------------------- 249 * USIU - Memory Controller Register 250 *----------------------------------------------------------------------- 251 */ 252 253#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_V | BR_BI | BR_PS_16) 254#define CONFIG_SYS_OR0_PRELIM (OR_ADDR_MK_FF | OR_SCY_3) 255#define CONFIG_SYS_BR1_PRELIM (ANYBUS_BASE) 256#define CONFIG_SYS_OR1_PRELIM (OR_ADDR_MK_FFFF | OR_SCY_1 | OR_ETHR) 257#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_SDRAM_BASE | BR_V | BR_PS_32) 258#define CONFIG_SYS_OR2_PRELIM (OR_ADDR_MK_FF) 259#define CONFIG_SYS_BR3_PRELIM (PLD_BASE | BR_V | BR_BI | BR_LBDIR | BR_PS_8) 260#define CONFIG_SYS_OR3_PRELIM (OR_ADDR_MK_FF | OR_TRLX | OR_BSCY | OR_SCY_8 | \ 261 OR_ACS_10 | OR_ETHR | OR_CSNT) 262 263#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* We don't realign the flash */ 264 265/*----------------------------------------------------------------------- 266 * DER - Timer Decrementer 267 *----------------------------------------------------------------------- 268 * Initialise to zero 269 */ 270#define CONFIG_SYS_DER 0x00000000 271 272#endif /* __CONFIG_H */ 273