1/* 2 * (C) Copyright 2005 3 * Thomas.Lange@corelatus.se 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* 25 * This file contains the configuration parameters for the gth2 board. 26 */ 27 28#ifndef __CONFIG_H 29#define __CONFIG_H 30 31#define CONFIG_MIPS32 1 /* MIPS32 CPU core */ 32#define CONFIG_GTH2 1 33#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */ 34 35#define CONFIG_SOC_AU1000 1 36 37#define CONFIG_MISC_INIT_R 1 38 39#define CONFIG_ETHADDR DE:AD:BE:EF:01:02 /* Ethernet address */ 40 41#define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */ 42 43#define CONFIG_ENV_OVERWRITE 1 /* Allow change of ethernet address */ 44 45#define CONFIG_BOOT_RETRY_TIME 5 /* Retry boot in 5 secs */ 46 47#define CONFIG_RESET_TO_RETRY 1 /* If timeout waiting for command, perform a reset */ 48 49#define CONFIG_BAUDRATE 115200 50 51/* valid baudrates */ 52#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 53 54/* Only interrupt boot if space is pressed */ 55/* If a long serial cable is connected but */ 56/* other end is dead, garbage will be read */ 57#define CONFIG_AUTOBOOT_KEYED 1 58#define CONFIG_AUTOBOOT_PROMPT \ 59 "Press space to abort autoboot in %d second\n", bootdelay 60#define CONFIG_AUTOBOOT_DELAY_STR "d" 61#define CONFIG_AUTOBOOT_STOP_STR " " 62 63#define CONFIG_TIMESTAMP /* Print image info with timestamp */ 64#define CONFIG_BOOTARGS "panic=1" 65 66#define CONFIG_EXTRA_ENV_SETTINGS \ 67 "addmisc=setenv bootargs $(bootargs) " \ 68 "ethaddr=$(ethaddr) \0" \ 69 "netboot=bootp;run addmisc;bootm\0" \ 70 "" 71 72/* Boot from Compact flash partition 2 as default */ 73#define CONFIG_BOOTCOMMAND "ide reset;disk 0x81000000 0:2;run addmisc;bootm" 74 75 76/* 77 * BOOTP options 78 */ 79#define CONFIG_BOOTP_BOOTFILESIZE 80#define CONFIG_BOOTP_BOOTPATH 81#define CONFIG_BOOTP_GATEWAY 82#define CONFIG_BOOTP_HOSTNAME 83 84 85/* 86 * Command line configuration. 87 */ 88#include <config_cmd_default.h> 89 90#define CONFIG_CMD_IDE 91#define CONFIG_CMD_DHCP 92 93#undef CONFIG_CMD_BDI 94#undef CONFIG_CMD_BEDBUG 95#undef CONFIG_CMD_ELF 96#undef CONFIG_CMD_FAT 97#undef CONFIG_CMD_FLASH 98#undef CONFIG_CMD_FPGA 99#undef CONFIG_CMD_LOADB 100#undef CONFIG_CMD_LOADS 101#undef CONFIG_CMD_MII 102#undef CONFIG_CMD_NFS 103#undef CONFIG_CMD_SAVEENV 104#undef CONFIG_CMD_SOURCE 105 106 107/* 108 * Miscellaneous configurable options 109 */ 110#define CONFIG_SYS_LONGHELP /* undef to save memory */ 111#define CONFIG_SYS_PROMPT "GTH2 # " /* Monitor Command Prompt */ 112#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 113#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 114#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/ 115 116#define CONFIG_SYS_MALLOC_LEN 128*1024 117 118#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024 119 120#define CONFIG_SYS_MHZ 500 121 122#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) 123 124#define CONFIG_SYS_HZ 1000 125 126#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */ 127 128#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */ 129 130#define CONFIG_SYS_MEMTEST_START 0x80100000 131#define CONFIG_SYS_MEMTEST_END 0x83000000 132 133#define CONFIG_HW_WATCHDOG 1 134 135/*----------------------------------------------------------------------- 136 * FLASH and environment organization 137 */ 138#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 139#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ 140 141#define PHYS_FLASH 0xbfc00000 /* Flash Bank #1 */ 142 143/* The following #defines are needed to get flash environment right */ 144#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 145#define CONFIG_SYS_MONITOR_LEN (192 << 10) 146 147#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 148 149/* We boot from this flash, selected with dip switch */ 150#define CONFIG_SYS_FLASH_BASE PHYS_FLASH 151 152/* timeout values are in ticks */ 153#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */ 154#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */ 155 156#define CONFIG_ENV_IS_NOWHERE 1 157 158/* Address and size of Primary Environment Sector */ 159#define CONFIG_ENV_ADDR 0xB0030000 160#define CONFIG_ENV_SIZE 0x10000 161 162#define CONFIG_FLASH_16BIT 163 164#define CONFIG_NR_DRAM_BANKS 2 165 166 167#define CONFIG_MEMSIZE_IN_BYTES 168 169/*---ATA PCMCIA ------------------------------------*/ 170#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */ 171 172#define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000 173#define CONFIG_SYS_PCMCIA_IO_BASE 0x28000000 174#define CONFIG_SYS_PCMCIA_ATTR_BASE 0x30000000 175 176#define CONFIG_PCMCIA_SLOT_A 177 178#define CONFIG_ATAPI 1 179#define CONFIG_MAC_PARTITION 1 180 181/* We run CF in "true ide" mode or a harddrive via pcmcia */ 182#define CONFIG_IDE_PCMCIA 1 183 184/* We only support one slot for now */ 185#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 186#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 187 188#undef CONFIG_IDE_LED /* LED for ide not supported */ 189#undef CONFIG_IDE_RESET /* reset for ide not supported */ 190 191#define CONFIG_SYS_ATA_IDE0_OFFSET 0 192 193#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_IO_BASE 194 195/* Offset for data I/O */ 196#define CONFIG_SYS_ATA_DATA_OFFSET 0 197 198/* Offset for normal register accesses */ 199#define CONFIG_SYS_ATA_REG_OFFSET 0 200 201/* Offset for alternate registers */ 202#define CONFIG_SYS_ATA_ALT_OFFSET 0x0200 203 204/*----------------------------------------------------------------------- 205 * Cache Configuration 206 */ 207#define CONFIG_SYS_DCACHE_SIZE 16384 208#define CONFIG_SYS_ICACHE_SIZE 16384 209#define CONFIG_SYS_CACHELINE_SIZE 32 210 211#define GPIO_CACONFIG (1<<0) 212#define GPIO_DPACONFIG (1<<6) 213#define GPIO_ERESET (1<<11) 214#define GPIO_EEDQ (1<<17) 215#define GPIO_WDI (1<<18) 216#define GPIO_RJ1LY (1<<22) 217#define GPIO_RJ1LG (1<<23) 218#define GPIO_LEDCLK (1<<29) 219#define GPIO_LEDD (1<<30) 220#define GPIO_CPU_LED (1<<31) 221 222#endif /* __CONFIG_H */ 223