1/* 2 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> 3 * 4 * (C) Copyright 2009 Freescale Semiconductor, Inc. 5 * 6 * Configuration settings for the MX51-3Stack Freescale board. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24#ifndef __CONFIG_H 25#define __CONFIG_H 26 27 28#define CONFIG_MX51 /* in a mx51 */ 29#define CONFIG_SYS_TEXT_BASE 0x97800000 30 31#include <asm/arch/imx-regs.h> 32 33#define CONFIG_SYS_MX5_HCLK 24000000 34#define CONFIG_SYS_MX5_CLK32 32768 35#define CONFIG_DISPLAY_CPUINFO 36#define CONFIG_DISPLAY_BOARDINFO 37 38#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 39#define CONFIG_SETUP_MEMORY_TAGS 40#define CONFIG_INITRD_TAG 41#define CONFIG_BOARD_LATE_INIT 42 43#ifndef MACH_TYPE_TTC_VISION2 44#define MACH_TYPE_TTC_VISION2 2775 45#endif 46#define CONFIG_MACH_TYPE MACH_TYPE_TTC_VISION2 47 48/* 49 * Size of malloc() pool 50 */ 51#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 52 53/* 54 * Hardware drivers 55 */ 56#define CONFIG_MXC_UART 57#define CONFIG_MXC_UART_BASE UART3_BASE 58#define CONFIG_MXC_GPIO 59#define CONFIG_MXC_SPI 60#define CONFIG_HW_WATCHDOG 61 62 /* 63 * SPI Configs 64 * */ 65#define CONFIG_FSL_SF 66#define CONFIG_CMD_SF 67 68#define CONFIG_SPI_FLASH 69#define CONFIG_SPI_FLASH_STMICRO 70 71/* 72 * Use gpio 4 pin 25 as chip select for SPI flash 73 * This corresponds to gpio 121 74 */ 75#define CONFIG_SF_DEFAULT_CS (1 | (121 << 8)) 76#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 77#define CONFIG_SF_DEFAULT_SPEED 25000000 78 79#define CONFIG_ENV_SPI_CS (1 | (121 << 8)) 80#define CONFIG_ENV_SPI_BUS 0 81#define CONFIG_ENV_SPI_MAX_HZ 25000000 82#define CONFIG_ENV_SPI_MODE SPI_MODE_0 83 84#define CONFIG_ENV_OFFSET (6 * 64 * 1024) 85#define CONFIG_ENV_SECT_SIZE (1 * 64 * 1024) 86#define CONFIG_ENV_SIZE (4 * 1024) 87 88#define CONFIG_FSL_ENV_IN_SF 89#define CONFIG_ENV_IS_IN_SPI_FLASH 90 91/* PMIC Controller */ 92#define CONFIG_PMIC 93#define CONFIG_PMIC_SPI 94#define CONFIG_PMIC_FSL 95#define CONFIG_FSL_PMIC_BUS 0 96#define CONFIG_FSL_PMIC_CS 0 97#define CONFIG_FSL_PMIC_CLK 2500000 98#define CONFIG_FSL_PMIC_MODE SPI_MODE_0 99#define CONFIG_FSL_PMIC_BITLEN 32 100#define CONFIG_RTC_MC13XXX 101 102/* 103 * MMC Configs 104 */ 105#define CONFIG_FSL_ESDHC 106#ifdef CONFIG_FSL_ESDHC 107#define CONFIG_SYS_FSL_ESDHC_ADDR (0x70004000) 108#define CONFIG_SYS_FSL_ESDHC_NUM 1 109 110#define CONFIG_MMC 111 112#define CONFIG_CMD_MMC 113#define CONFIG_GENERIC_MMC 114#define CONFIG_CMD_FAT 115#define CONFIG_DOS_PARTITION 116#endif 117 118#define CONFIG_CMD_DATE 119 120/* 121 * Eth Configs 122 */ 123#define CONFIG_HAS_ETH1 124#define CONFIG_MII 125 126#define CONFIG_FEC_MXC 127#define IMX_FEC_BASE FEC_BASE_ADDR 128#define CONFIG_FEC_MXC_PHYADDR 0x1F 129 130#define CONFIG_CMD_PING 131#define CONFIG_CMD_MII 132#define CONFIG_CMD_NET 133 134/* allow to overwrite serial and ethaddr */ 135#define CONFIG_ENV_OVERWRITE 136#define CONFIG_CONS_INDEX 3 137#define CONFIG_BAUDRATE 115200 138 139/*********************************************************** 140 * Command definition 141 ***********************************************************/ 142 143#include <config_cmd_default.h> 144 145#define CONFIG_CMD_SPI 146#undef CONFIG_CMD_IMLS 147 148#define CONFIG_BOOTDELAY 3 149 150#define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */ 151 152#define CONFIG_EXTRA_ENV_SETTINGS \ 153 "netdev=eth0\0" \ 154 "loadaddr=0x90800000\0" 155 156/* 157 * Miscellaneous configurable options 158 */ 159#define CONFIG_SYS_LONGHELP 160#define CONFIG_SYS_PROMPT "Vision II U-boot > " 161#define CONFIG_AUTO_COMPLETE 162#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 163 164/* Print Buffer Size */ 165#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 166 sizeof(CONFIG_SYS_PROMPT) + 16) 167#define CONFIG_SYS_MAXARGS 64 /* max number of command args */ 168#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 169 170#define CONFIG_SYS_MEMTEST_START 0x90000000 171#define CONFIG_SYS_MEMTEST_END 0x10000 172 173#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 174 175#define CONFIG_SYS_HZ 1000 176#define CONFIG_CMDLINE_EDITING 177#define CONFIG_SYS_HUSH_PARSER 178 179/* 180 * Physical Memory Map 181 */ 182#define CONFIG_NR_DRAM_BANKS 2 183#define PHYS_SDRAM_1 CSD0_BASE_ADDR 184#define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024) 185#define PHYS_SDRAM_2 CSD1_BASE_ADDR 186#define PHYS_SDRAM_2_SIZE (256 * 1024 * 1024) 187#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 188#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 189#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 190 191#define CONFIG_SYS_INIT_SP_OFFSET \ 192 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 193#define CONFIG_SYS_INIT_SP_ADDR \ 194 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 195 196#define CONFIG_BOARD_EARLY_INIT_F 197 198/* 166 MHz DDR RAM */ 199#define CONFIG_SYS_DDR_CLKSEL 0 200#define CONFIG_SYS_CLKTL_CBCDR 0x19239100 201 202#define CONFIG_SYS_NO_FLASH 203 204/* 205 * Framebuffer and LCD 206 */ 207#define CONFIG_PREBOOT 208#define CONFIG_VIDEO 209#define CONFIG_VIDEO_IPUV3 210#define CONFIG_CFB_CONSOLE 211#define CONFIG_VGA_AS_SINGLE_DEVICE 212#define CONFIG_SYS_CONSOLE_IS_IN_ENV 213#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 214#define CONFIG_VIDEO_BMP_RLE8 215#define CONFIG_SPLASH_SCREEN 216#define CONFIG_CMD_BMP 217#define CONFIG_BMP_16BPP 218#define CONFIG_IPUV3_CLK 133000000 219 220#endif /* __CONFIG_H */ 221