LXR uboot/include/configs/zeus.h

   1/*
   2 * (C) Copyright 2007
   3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24/************************************************************************
  25 * zeus.h - configuration for Zeus board
  26 ***********************************************************************/
  27#ifndef __CONFIG_H
  28#define __CONFIG_H
  29
  30/*-----------------------------------------------------------------------
  31 * High Level Configuration Options
  32 *----------------------------------------------------------------------*/
  33#define CONFIG_ZEUS             1               /* Board is Zeus        */
  34#define CONFIG_4xx              1               /* ... PPC4xx family    */
  35#define CONFIG_405EP            1               /* Specifc 405EP support*/
  36
  37#define CONFIG_SYS_TEXT_BASE    0xFFFC0000
  38
  39#define CONFIG_SYS_CLK_FREQ     33000000 /* external frequency to pll   */
  40
  41#define CONFIG_BOARD_EARLY_INIT_F 1             /* Call board_early_init_f */
  42#define CONFIG_MISC_INIT_R      1               /* Call misc_init_r     */
  43
  44#define PLLMR0_DEFAULT          PLLMR0_333_111_55_111
  45#define PLLMR1_DEFAULT          PLLMR1_333_111_55_111
  46
  47#define CONFIG_ENV_IS_IN_FLASH     1    /* use FLASH for environment vars       */
  48
  49#define CONFIG_OVERWRITE_ETHADDR_ONCE   1
  50
  51#define CONFIG_PPC4xx_EMAC
  52#define CONFIG_MII              1       /* MII PHY management           */
  53#define CONFIG_PHY_ADDR         0x01    /* PHY address                  */
  54#define CONFIG_HAS_ETH1         1
  55#define CONFIG_PHY1_ADDR        0x11    /* EMAC1 PHY address            */
  56#define CONFIG_SYS_RX_ETH_BUFFER        16      /* Number of ethernet rx buffers & descriptors */
  57#define CONFIG_PHY_RESET        1
  58#define CONFIG_PHY_RESET_DELAY  300     /* PHY RESET recovery delay     */
  59
  60/*
  61 * BOOTP options
  62 */
  63#define CONFIG_BOOTP_BOOTFILESIZE
  64#define CONFIG_BOOTP_BOOTPATH
  65#define CONFIG_BOOTP_GATEWAY
  66#define CONFIG_BOOTP_HOSTNAME
  67
  68/*
  69 * Command line configuration.
  70 */
  71#include <config_cmd_default.h>
  72
  73#define CONFIG_CMD_ASKENV
  74#define CONFIG_CMD_CACHE
  75#define CONFIG_CMD_DHCP
  76#define CONFIG_CMD_DIAG
  77#define CONFIG_CMD_EEPROM
  78#define CONFIG_CMD_ELF
  79#define CONFIG_CMD_I2C
  80#define CONFIG_CMD_IRQ
  81#define CONFIG_CMD_MII
  82#define CONFIG_CMD_NET
  83#define CONFIG_CMD_NFS
  84#define CONFIG_CMD_PING
  85#define CONFIG_CMD_REGINFO
  86
  87/* POST support */
  88#define CONFIG_POST             (CONFIG_SYS_POST_MEMORY   | \
  89                                 CONFIG_SYS_POST_CPU       | \
  90                                 CONFIG_SYS_POST_CACHE     | \
  91                                 CONFIG_SYS_POST_UART      | \
  92                                 CONFIG_SYS_POST_ETHER)
  93
  94#define CONFIG_SYS_POST_ETHER_EXT_LOOPBACK      /* eth POST using ext loopack connector */
  95
  96/* Define here the base-addresses of the UARTs to test in POST */
  97#define CONFIG_SYS_POST_UART_TABLE      { CONFIG_SYS_NS16550_COM1 }
  98
  99#define CONFIG_LOGBUFFER
 100#define CONFIG_SYS_POST_CACHE_ADDR      0x00800000 /* free virtual address      */
 101
 102#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
 103
 104#undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 105
 106/*-----------------------------------------------------------------------
 107 * SDRAM
 108 *----------------------------------------------------------------------*/
 109/*
 110 * SDRAM configuration (please see cpu/ppc/sdram.[ch])
 111 */
 112#define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0 */
 113#define CONFIG_SDRAM_BANK1      1       /* init onboard SDRAM bank 1 */
 114
 115/* SDRAM timings used in datasheet */
 116#define CONFIG_SYS_SDRAM_CL            3        /* CAS latency */
 117#define CONFIG_SYS_SDRAM_tRP           20       /* PRECHARGE command period */
 118#define CONFIG_SYS_SDRAM_tRC           66       /* ACTIVE-to-ACTIVE command period */
 119#define CONFIG_SYS_SDRAM_tRCD          20       /* ACTIVE-to-READ delay */
 120#define CONFIG_SYS_SDRAM_tRFC           66      /* Auto refresh period */
 121
 122/*-----------------------------------------------------------------------
 123 * Serial Port
 124 *----------------------------------------------------------------------*/
 125#define CONFIG_CONS_INDEX       1
 126#define CONFIG_SYS_NS16550
 127#define CONFIG_SYS_NS16550_SERIAL
 128#define CONFIG_SYS_NS16550_REG_SIZE     1
 129#define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 130#undef  CONFIG_SYS_EXT_SERIAL_CLOCK                     /* external serial clock */
 131#define CONFIG_SYS_BASE_BAUD    691200
 132#define CONFIG_BAUDRATE         115200
 133#define CONFIG_SERIAL_MULTI
 134
 135#define CONFIG_SYS_BAUDRATE_TABLE  \
 136    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
 137
 138/*-----------------------------------------------------------------------
 139 * Miscellaneous configurable options
 140 *----------------------------------------------------------------------*/
 141#define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 142#define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt       */
 143#if defined(CONFIG_CMD_KGDB)
 144#define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size      */
 145#else
 146#define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size      */
 147#endif
 148#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 149#define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 150#define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size  */
 151
 152#define CONFIG_SYS_MEMTEST_START        0x0400000 /* memtest works on           */
 153#define CONFIG_SYS_MEMTEST_END          0x0C00000 /* 4 ... 12 MB in DRAM        */
 154
 155#define CONFIG_SYS_LOAD_ADDR            0x100000  /* default load address       */
 156#define CONFIG_SYS_EXTBDINFO            1       /* To use extended board_into (bd_t) */
 157
 158#define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 159
 160#define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 161#define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 162
 163#define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 164#define CONFIG_LOOPW            1       /* enable loopw command         */
 165#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 166#define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 167#define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 168
 169/*-----------------------------------------------------------------------
 170 * I2C
 171 *----------------------------------------------------------------------*/
 172#define CONFIG_HARD_I2C         1               /* I2C with hardware support    */
 173#undef  CONFIG_SOFT_I2C                         /* I2C bit-banged               */
 174#define CONFIG_PPC4XX_I2C               /* use PPC4xx driver            */
 175#define CONFIG_SYS_I2C_SPEED            400000          /* I2C speed and slave address  */
 176#define CONFIG_SYS_I2C_SLAVE            0x7F
 177
 178/* these are for the ST M24C02 2kbit serial i2c eeprom */
 179#define CONFIG_SYS_I2C_EEPROM_ADDR      0x50            /* base address */
 180#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1               /* bytes of address */
 181/* mask of address bits that overflow into the "EEPROM chip address"    */
 182#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 183
 184#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3       /* 8 byte write page size */
 185#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* and takes up to 10 msec */
 186
 187/*
 188 * The layout of the I2C EEPROM, used for bootstrap setup and for board-
 189 * specific values, like ethaddr... that can be restored via the sw-reset
 190 * button
 191 */
 192#define FACTORY_RESET_I2C_EEPROM        0x50
 193#define FACTORY_RESET_ENV_OFFS          0x80
 194#define FACTORY_RESET_ENV_SIZE          0x80
 195
 196/*-----------------------------------------------------------------------
 197 * Start addresses for the final memory configuration
 198 * (Set up by the startup code)
 199 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 200 */
 201#define CONFIG_SYS_SDRAM_BASE           0x00000000
 202#define CONFIG_SYS_FLASH_BASE           0xFF000000
 203#define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Monitor   */
 204#define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserve 128 kB for malloc()  */
 205#define CONFIG_SYS_MONITOR_BASE (-CONFIG_SYS_MONITOR_LEN)
 206
 207/*
 208 * For booting Linux, the board info and command line data
 209 * have to be in the first 8 MB of memory, since this is
 210 * the maximum mapped by the Linux kernel during initialization.
 211 */
 212#define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 213
 214/*-----------------------------------------------------------------------
 215 * FLASH organization
 216 */
 217#define CONFIG_SYS_FLASH_CFI                            /* The flash is CFI compatible  */
 218#define CONFIG_FLASH_CFI_DRIVER                 /* Use common CFI driver        */
 219
 220#define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 221
 222#define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 223#define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip    */
 224
 225#define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 226#define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 227
 228#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
 229#define CONFIG_SYS_FLASH_PROTECTION     1       /* use hardware flash protection        */
 230
 231#define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 232#define CONFIG_SYS_FLASH_QUIET_TEST     1       /* don't warn upon unknown flash        */
 233
 234#ifdef CONFIG_ENV_IS_IN_FLASH
 235#define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector          */
 236#define CONFIG_ENV_ADDR         ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
 237#define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector     */
 238
 239/* Address and size of Redundant Environment Sector     */
 240#define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 241#define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 242#endif
 243
 244/*-----------------------------------------------------------------------
 245 * Definitions for initial stack pointer and data area (in data cache)
 246 */
 247/* use on chip memory (OCM) for temperary stack until sdram is tested */
 248#define CONFIG_SYS_TEMP_STACK_OCM       1
 249
 250/* On Chip Memory location */
 251#define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 252#define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 253#define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* inside of OCM               */
 254#define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM    */
 255
 256#define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 257/* reserve some memory for POST and BOOT limit info */
 258#define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_GBL_DATA_OFFSET - 16)
 259
 260/* extra data in OCM */
 261#define CONFIG_SYS_POST_MAGIC           \
 262                (CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_GBL_DATA_OFFSET - 8)
 263#define CONFIG_SYS_POST_VAL             \
 264                (CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_GBL_DATA_OFFSET - 12)
 265
 266/*-----------------------------------------------------------------------
 267 * External Bus Controller (EBC) Setup
 268 */
 269
 270/* Memory Bank 0 (Flash 16M) initialization                                     */
 271#define CONFIG_SYS_EBC_PB0AP            0x05815600
 272#define CONFIG_SYS_EBC_PB0CR            0xFF09A000  /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit  */
 273
 274/*-----------------------------------------------------------------------
 275 * Definitions for GPIO setup (PPC405EP specific)
 276 *
 277 * GPIO0[0]     - External Bus Controller BLAST output
 278 * GPIO0[1-9]   - Instruction trace outputs
 279 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
 280 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
 281 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
 282 * GPIO0[24-27] - UART0 control signal inputs/outputs
 283 * GPIO0[28-29] - UART1 data signal input/output
 284 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
 285 */
 286#define CONFIG_SYS_GPIO0_OSRL           0x15555550      /* Chip selects */
 287#define CONFIG_SYS_GPIO0_OSRH           0x00000110      /* UART_DTR-pin 27 alt out */
 288#define CONFIG_SYS_GPIO0_ISR1L          0x10000041      /* Pin 2, 12 is input */
 289#define CONFIG_SYS_GPIO0_ISR1H          0x15505440      /* OUT: LEDs 22/23; IN: pin12,2, NVALID# */
 290#define CONFIG_SYS_GPIO0_TSRL           0x00000000
 291#define CONFIG_SYS_GPIO0_TSRH           0x00000000
 292#define CONFIG_SYS_GPIO0_TCR            0xBFF68317      /* 3-state OUT: 22/23/29; 12,2 is not 3-state */
 293#define CONFIG_SYS_GPIO0_ODR            0x00000000
 294
 295#define CONFIG_SYS_GPIO_SW_RESET        1
 296#define CONFIG_SYS_GPIO_ZEUS_PE 12
 297#define CONFIG_SYS_GPIO_LED_RED 22
 298#define CONFIG_SYS_GPIO_LED_GREEN       23
 299
 300/* Time in milli-seconds */
 301#define CONFIG_SYS_TIME_POST            5000
 302#define CONFIG_SYS_TIME_FACTORY_RESET   10000
 303
 304#if defined(CONFIG_CMD_KGDB)
 305#define CONFIG_KGDB_BAUDRATE    230400          /* speed to run kgdb serial port */
 306#define CONFIG_KGDB_SER_INDEX   2               /* which serial port to use */
 307#endif
 308
 309/*
 310 * Pass open firmware flat tree
 311 */
 312#define CONFIG_OF_LIBFDT
 313#define CONFIG_OF_BOARD_SETUP
 314
 315/* ENVIRONMENT VARS */
 316
 317#define CONFIG_PREBOOT          "echo;echo Welcome to Bulletendpoints board v1.1;echo"
 318#define CONFIG_IPADDR           192.168.1.10
 319#define CONFIG_SERVERIP         192.168.1.100
 320#define CONFIG_GATEWAYIP        192.168.1.100
 321#define CONFIG_ETHADDR          50:00:00:00:06:00
 322#define CONFIG_ETH1ADDR         50:00:00:00:06:01
 323#if 0
 324#define CONFIG_BOOTDELAY        -1      /* autoboot disabled        */
 325#else
 326#define CONFIG_BOOTDELAY        3       /* autoboot after 5 seconds */
 327#endif
 328
 329#define CONFIG_EXTRA_ENV_SETTINGS                                       \
 330        "logversion=2\0"                                                \
 331        "hostname=zeus\0"                                               \
 332        "netdev=eth0\0"                                                 \
 333        "ethact=ppc_4xx_eth0\0"                                         \
 334        "netmask=255.255.255.0\0"                                       \
 335        "ramdisk_size=50000\0"                                          \
 336        "nfsargs=setenv bootargs root=/dev/nfs rw"                      \
 337                " nfsroot=${serverip}:${rootpath}\0"                    \
 338        "ramargs=setenv bootargs root=/dev/ram rw"                      \
 339                " ramdisk_size=${ramdisk_size}\0"                       \
 340        "addip=setenv bootargs ${bootargs} "                            \
 341                "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 342                ":${hostname}:${netdev}:off panic=1\0"                  \
 343        "addtty=setenv bootargs ${bootargs} console=ttyS0,"             \
 344                "${baudrate}\0"                                         \
 345        "net_nfs=tftp ${kernel_mem_addr} ${file_kernel};"               \
 346                "run nfsargs addip addtty;bootm\0"                      \
 347        "net_ram=tftp ${kernel_mem_addr} ${file_kernel};"               \
 348                "tftp ${ramdisk_mem_addr} ${file_fs};"                  \
 349                "run ramargs addip addtty;"                             \
 350                "bootm ${kernel_mem_addr} ${ramdisk_mem_addr}\0"        \
 351        "rootpath=/target_fs/zeus\0"                                    \
 352        "kernel_fl_addr=ff000000\0"                                     \
 353        "kernel_mem_addr=200000\0"                                      \
 354        "ramdisk_fl_addr=ff300000\0"                                    \
 355        "ramdisk_mem_addr=4000000\0"                                    \
 356        "uboot_fl_addr=fffc0000\0"                                      \
 357        "uboot_mem_addr=100000\0"                                       \
 358        "file_uboot=/zeus/u-boot.bin\0"                                 \
 359        "tftp_uboot=tftp 100000 ${file_uboot}\0"                        \
 360        "update_uboot=protect off fffc0000 ffffffff;"                   \
 361                "era fffc0000 ffffffff;cp.b 100000 fffc0000 40000;"     \
 362                "protect on fffc0000 ffffffff\0"                        \
 363        "upd_uboot=run tftp_uboot;run update_uboot\0"                   \
 364        "file_kernel=/zeus/uImage_ba\0"                                 \
 365        "tftp_kernel=tftp 100000 ${file_kernel}\0"                      \
 366        "update_kernel=protect off ff000000 ff17ffff;"                  \
 367                "era ff000000 ff17ffff;cp.b 100000 ff000000 180000\0"   \
 368        "upd_kernel=run tftp_kernel;run update_kernel\0"                \
 369        "file_fs=/zeus/rootfs_ba.img\0"                                 \
 370        "tftp_fs=tftp 100000 ${file_fs}\0"                              \
 371        "update_fs=protect off ff300000 ff87ffff;era ff300000 ff87ffff;"\
 372                "cp.b 100000 ff300000 580000\0"                         \
 373        "upd_fs=run tftp_fs;run update_fs\0"                            \
 374        "bootcmd=chkreset;run ramargs addip addtty addmisc;"            \
 375                "bootm ${kernel_fl_addr} ${ramdisk_fl_addr}\0"          \
 376        ""
 377
 378#endif  /* __CONFIG_H */
 379