1/* 2 * (C) Copyright 2001 3 * Denis Peter, MPL AG Switzerland 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 * 23 * 24 * Most of these definitions are derived from 25 * linux/drivers/scsi/sym53c8xx_defs.h 26 * 27 */ 28 29#ifndef _SYM53C8XX_DEFS_H 30#define _SYM53C8XX_DEFS_H 31 32 33#define SCNTL0 0x00 /* full arb., ena parity, par->ATN */ 34 35#define SCNTL1 0x01 /* no reset */ 36 #define ISCON 0x10 /* connected to scsi */ 37 #define CRST 0x08 /* force reset */ 38 #define IARB 0x02 /* immediate arbitration */ 39 40#define SCNTL2 0x02 /* no disconnect expected */ 41 #define SDU 0x80 /* cmd: disconnect will raise error */ 42 #define CHM 0x40 /* sta: chained mode */ 43 #define WSS 0x08 /* sta: wide scsi send [W]*/ 44 #define WSR 0x01 /* sta: wide scsi received [W]*/ 45 46#define SCNTL3 0x03 /* cnf system clock dependent */ 47 #define EWS 0x08 /* cmd: enable wide scsi [W]*/ 48 #define ULTRA 0x80 /* cmd: ULTRA enable */ 49 /* bits 0-2, 7 rsvd for C1010 */ 50 51#define SCID 0x04 /* cnf host adapter scsi address */ 52 #define RRE 0x40 /* r/w:e enable response to resel. */ 53 #define SRE 0x20 /* r/w:e enable response to select */ 54 55#define SXFER 0x05 /* ### Sync speed and count */ 56 /* bits 6-7 rsvd for C1010 */ 57 58#define SDID 0x06 /* ### Destination-ID */ 59 60#define GPREG 0x07 /* ??? IO-Pins */ 61 62#define SFBR 0x08 /* ### First byte in phase */ 63 64#define SOCL 0x09 65 #define CREQ 0x80 /* r/w: SCSI-REQ */ 66 #define CACK 0x40 /* r/w: SCSI-ACK */ 67 #define CBSY 0x20 /* r/w: SCSI-BSY */ 68 #define CSEL 0x10 /* r/w: SCSI-SEL */ 69 #define CATN 0x08 /* r/w: SCSI-ATN */ 70 #define CMSG 0x04 /* r/w: SCSI-MSG */ 71 #define CC_D 0x02 /* r/w: SCSI-C_D */ 72 #define CI_O 0x01 /* r/w: SCSI-I_O */ 73 74#define SSID 0x0a 75 76#define SBCL 0x0b 77 78#define DSTAT 0x0c 79 #define DFE 0x80 /* sta: dma fifo empty */ 80 #define MDPE 0x40 /* int: master data parity error */ 81 #define BF 0x20 /* int: script: bus fault */ 82 #define ABRT 0x10 /* int: script: command aborted */ 83 #define SSI 0x08 /* int: script: single step */ 84 #define SIR 0x04 /* int: script: interrupt instruct. */ 85 #define IID 0x01 /* int: script: illegal instruct. */ 86 87#define SSTAT0 0x0d 88 #define ILF 0x80 /* sta: data in SIDL register lsb */ 89 #define ORF 0x40 /* sta: data in SODR register lsb */ 90 #define OLF 0x20 /* sta: data in SODL register lsb */ 91 #define AIP 0x10 /* sta: arbitration in progress */ 92 #define LOA 0x08 /* sta: arbitration lost */ 93 #define WOA 0x04 /* sta: arbitration won */ 94 #define IRST 0x02 /* sta: scsi reset signal */ 95 #define SDP 0x01 /* sta: scsi parity signal */ 96 97#define SSTAT1 0x0e 98 #define FF3210 0xf0 /* sta: bytes in the scsi fifo */ 99 100#define SSTAT2 0x0f 101 #define ILF1 0x80 /* sta: data in SIDL register msb[W]*/ 102 #define ORF1 0x40 /* sta: data in SODR register msb[W]*/ 103 #define OLF1 0x20 /* sta: data in SODL register msb[W]*/ 104 #define DM 0x04 /* sta: DIFFSENS mismatch (895/6 only) */ 105 #define LDSC 0x02 /* sta: disconnect & reconnect */ 106 107#define DSA 0x10 /* --> Base page */ 108#define DSA1 0x11 109#define DSA2 0x12 110#define DSA3 0x13 111 112#define ISTAT 0x14 /* --> Main Command and status */ 113 #define CABRT 0x80 /* cmd: abort current operation */ 114 #define SRST 0x40 /* mod: reset chip */ 115 #define SIGP 0x20 /* r/w: message from host to ncr */ 116 #define SEM 0x10 /* r/w: message between host + ncr */ 117 #define CON 0x08 /* sta: connected to scsi */ 118 #define INTF 0x04 /* sta: int on the fly (reset by wr)*/ 119 #define SIP 0x02 /* sta: scsi-interrupt */ 120 #define DIP 0x01 /* sta: host/script interrupt */ 121 122 123#define CTEST0 0x18 124#define CTEST1 0x19 125#define CTEST2 0x1a 126 #define CSIGP 0x40 127 /* bits 0-2,7 rsvd for C1010 */ 128 129#define CTEST3 0x1b 130 #define FLF 0x08 /* cmd: flush dma fifo */ 131 #define CLF 0x04 /* cmd: clear dma fifo */ 132 #define FM 0x02 /* mod: fetch pin mode */ 133 #define WRIE 0x01 /* mod: write and invalidate enable */ 134 /* bits 4-7 rsvd for C1010 */ 135 136#define DFIFO 0x20 137#define CTEST4 0x21 138 #define BDIS 0x80 /* mod: burst disable */ 139 #define MPEE 0x08 /* mod: master parity error enable */ 140 141#define CTEST5 0x22 142 #define DFS 0x20 /* mod: dma fifo size */ 143 /* bits 0-1, 3-7 rsvd for C1010 */ 144#define CTEST6 0x23 145 146#define DBC 0x24 /* ### Byte count and command */ 147#define DNAD 0x28 /* ### Next command register */ 148#define DSP 0x2c /* --> Script Pointer */ 149#define DSPS 0x30 /* --> Script pointer save/opcode#2 */ 150 151#define SCRATCHA 0x34 /* Temporary register a */ 152#define SCRATCHA1 0x35 153#define SCRATCHA2 0x36 154#define SCRATCHA3 0x37 155 156#define DMODE 0x38 157 #define BL_2 0x80 /* mod: burst length shift value +2 */ 158 #define BL_1 0x40 /* mod: burst length shift value +1 */ 159 #define ERL 0x08 /* mod: enable read line */ 160 #define ERMP 0x04 /* mod: enable read multiple */ 161 #define BOF 0x02 /* mod: burst op code fetch */ 162 #define MAN 0x01 /* mod: manual start */ 163 164#define DIEN 0x39 165#define SBR 0x3a 166 167#define DCNTL 0x3b /* --> Script execution control */ 168 #define CLSE 0x80 /* mod: cache line size enable */ 169 #define PFF 0x40 /* cmd: pre-fetch flush */ 170 #define PFEN 0x20 /* mod: pre-fetch enable */ 171 #define SSM 0x10 /* mod: single step mode */ 172 #define IRQM 0x08 /* mod: irq mode (1 = totem pole !) */ 173 #define STD 0x04 /* cmd: start dma mode */ 174 #define IRQD 0x02 /* mod: irq disable */ 175 #define NOCOM 0x01 /* cmd: protect sfbr while reselect */ 176 /* bits 0-1 rsvd for C1010 */ 177 178#define ADDER 0x3c 179 180#define SIEN 0x40 /* -->: interrupt enable */ 181#define SIST 0x42 /* <--: interrupt status */ 182 #define SBMC 0x1000/* sta: SCSI Bus Mode Change (895/6 only) */ 183 #define STO 0x0400/* sta: timeout (select) */ 184 #define GEN 0x0200/* sta: timeout (general) */ 185 #define HTH 0x0100/* sta: timeout (handshake) */ 186 #define MA 0x80 /* sta: phase mismatch */ 187 #define CMP 0x40 /* sta: arbitration complete */ 188 #define SEL 0x20 /* sta: selected by another device */ 189 #define RSL 0x10 /* sta: reselected by another device*/ 190 #define SGE 0x08 /* sta: gross error (over/underflow)*/ 191 #define UDC 0x04 /* sta: unexpected disconnect */ 192 #define RST 0x02 /* sta: scsi bus reset detected */ 193 #define PAR 0x01 /* sta: scsi parity error */ 194 195#define SLPAR 0x44 196#define SWIDE 0x45 197#define MACNTL 0x46 198#define GPCNTL 0x47 199#define STIME0 0x48 /* cmd: timeout for select&handshake*/ 200#define STIME1 0x49 /* cmd: timeout user defined */ 201#define RESPID 0x4a /* sta: Reselect-IDs */ 202 203#define STEST0 0x4c 204 205#define STEST1 0x4d 206 #define SCLK 0x80 /* Use the PCI clock as SCSI clock */ 207 #define DBLEN 0x08 /* clock doubler running */ 208 #define DBLSEL 0x04 /* clock doubler selected */ 209 210 211#define STEST2 0x4e 212 #define ROF 0x40 /* reset scsi offset (after gross error!) */ 213 #define EXT 0x02 /* extended filtering */ 214 215#define STEST3 0x4f 216 #define TE 0x80 /* c: tolerAnt enable */ 217 #define HSC 0x20 /* c: Halt SCSI Clock */ 218 #define CSF 0x02 /* c: clear scsi fifo */ 219 220#define SIDL 0x50 /* Lowlevel: latched from scsi data */ 221#define STEST4 0x52 222 #define SMODE 0xc0 /* SCSI bus mode (895/6 only) */ 223 #define SMODE_HVD 0x40 /* High Voltage Differential */ 224 #define SMODE_SE 0x80 /* Single Ended */ 225 #define SMODE_LVD 0xc0 /* Low Voltage Differential */ 226 #define LCKFRQ 0x20 /* Frequency Lock (895/6 only) */ 227 /* bits 0-5 rsvd for C1010 */ 228 229#define SODL 0x54 /* Lowlevel: data out to scsi data */ 230 231#define SBDL 0x58 /* Lowlevel: data from scsi data */ 232 233 234/*----------------------------------------------------------- 235** 236** Utility macros for the script. 237** 238**----------------------------------------------------------- 239*/ 240 241#define REG(r) (r) 242 243/*----------------------------------------------------------- 244** 245** SCSI phases 246** 247** DT phases illegal for ncr driver. 248** 249**----------------------------------------------------------- 250*/ 251 252#define SCR_DATA_OUT 0x00000000 253#define SCR_DATA_IN 0x01000000 254#define SCR_COMMAND 0x02000000 255#define SCR_STATUS 0x03000000 256#define SCR_DT_DATA_OUT 0x04000000 257#define SCR_DT_DATA_IN 0x05000000 258#define SCR_MSG_OUT 0x06000000 259#define SCR_MSG_IN 0x07000000 260 261#define SCR_ILG_OUT 0x04000000 262#define SCR_ILG_IN 0x05000000 263 264/*----------------------------------------------------------- 265** 266** Data transfer via SCSI. 267** 268**----------------------------------------------------------- 269** 270** MOVE_ABS (LEN) 271** <<start address>> 272** 273** MOVE_IND (LEN) 274** <<dnad_offset>> 275** 276** MOVE_TBL 277** <<dnad_offset>> 278** 279**----------------------------------------------------------- 280*/ 281 282#define OPC_MOVE 0x08000000 283 284#define SCR_MOVE_ABS(l) ((0x00000000 | OPC_MOVE) | (l)) 285#define SCR_MOVE_IND(l) ((0x20000000 | OPC_MOVE) | (l)) 286#define SCR_MOVE_TBL (0x10000000 | OPC_MOVE) 287 288#define SCR_CHMOV_ABS(l) ((0x00000000) | (l)) 289#define SCR_CHMOV_IND(l) ((0x20000000) | (l)) 290#define SCR_CHMOV_TBL (0x10000000) 291 292 293/*----------------------------------------------------------- 294** 295** Selection 296** 297**----------------------------------------------------------- 298** 299** SEL_ABS | SCR_ID (0..15) [ | REL_JMP] 300** <<alternate_address>> 301** 302** SEL_TBL | << dnad_offset>> [ | REL_JMP] 303** <<alternate_address>> 304** 305**----------------------------------------------------------- 306*/ 307 308#define SCR_SEL_ABS 0x40000000 309#define SCR_SEL_ABS_ATN 0x41000000 310#define SCR_SEL_TBL 0x42000000 311#define SCR_SEL_TBL_ATN 0x43000000 312 313 314#define SCR_JMP_REL 0x04000000 315#define SCR_ID(id) (((unsigned long)(id)) << 16) 316 317/*----------------------------------------------------------- 318** 319** Waiting for Disconnect or Reselect 320** 321**----------------------------------------------------------- 322** 323** WAIT_DISC 324** dummy: <<alternate_address>> 325** 326** WAIT_RESEL 327** <<alternate_address>> 328** 329**----------------------------------------------------------- 330*/ 331 332#define SCR_WAIT_DISC 0x48000000 333#define SCR_WAIT_RESEL 0x50000000 334 335/*----------------------------------------------------------- 336** 337** Bit Set / Reset 338** 339**----------------------------------------------------------- 340** 341** SET (flags {|.. }) 342** 343** CLR (flags {|.. }) 344** 345**----------------------------------------------------------- 346*/ 347 348#define SCR_SET(f) (0x58000000 | (f)) 349#define SCR_CLR(f) (0x60000000 | (f)) 350 351#define SCR_CARRY 0x00000400 352#define SCR_TRG 0x00000200 353#define SCR_ACK 0x00000040 354#define SCR_ATN 0x00000008 355 356 357/*----------------------------------------------------------- 358** 359** Memory to memory move 360** 361**----------------------------------------------------------- 362** 363** COPY (bytecount) 364** << source_address >> 365** << destination_address >> 366** 367** SCR_COPY sets the NO FLUSH option by default. 368** SCR_COPY_F does not set this option. 369** 370** For chips which do not support this option, 371** ncr_copy_and_bind() will remove this bit. 372**----------------------------------------------------------- 373*/ 374 375#define SCR_NO_FLUSH 0x01000000 376 377#define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n)) 378#define SCR_COPY_F(n) (0xc0000000 | (n)) 379 380/*----------------------------------------------------------- 381** 382** Register move and binary operations 383** 384**----------------------------------------------------------- 385** 386** SFBR_REG (reg, op, data) reg = SFBR op data 387** << 0 >> 388** 389** REG_SFBR (reg, op, data) SFBR = reg op data 390** << 0 >> 391** 392** REG_REG (reg, op, data) reg = reg op data 393** << 0 >> 394** 395**----------------------------------------------------------- 396** On 810A, 860, 825A, 875, 895 and 896 chips the content 397** of SFBR register can be used as data (SCR_SFBR_DATA). 398** The 896 has additionnal IO registers starting at 399** offset 0x80. Bit 7 of register offset is stored in 400** bit 7 of the SCRIPTS instruction first DWORD. 401**----------------------------------------------------------- 402*/ 403 404#define SCR_REG_OFS(ofs) ((((ofs) & 0x7f) << 16ul)) /* + ((ofs) & 0x80)) */ 405 406#define SCR_SFBR_REG(reg,op,data) \ 407 (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) 408 409#define SCR_REG_SFBR(reg,op,data) \ 410 (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) 411 412#define SCR_REG_REG(reg,op,data) \ 413 (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) 414 415 416#define SCR_LOAD 0x00000000 417#define SCR_SHL 0x01000000 418#define SCR_OR 0x02000000 419#define SCR_XOR 0x03000000 420#define SCR_AND 0x04000000 421#define SCR_SHR 0x05000000 422#define SCR_ADD 0x06000000 423#define SCR_ADDC 0x07000000 424 425#define SCR_SFBR_DATA (0x00800000>>8ul) /* Use SFBR as data */ 426 427/*----------------------------------------------------------- 428** 429** FROM_REG (reg) SFBR = reg 430** << 0 >> 431** 432** TO_REG (reg) reg = SFBR 433** << 0 >> 434** 435** LOAD_REG (reg, data) reg = <data> 436** << 0 >> 437** 438** LOAD_SFBR(data) SFBR = <data> 439** << 0 >> 440** 441**----------------------------------------------------------- 442*/ 443 444#define SCR_FROM_REG(reg) \ 445 SCR_REG_SFBR(reg,SCR_OR,0) 446 447#define SCR_TO_REG(reg) \ 448 SCR_SFBR_REG(reg,SCR_OR,0) 449 450#define SCR_LOAD_REG(reg,data) \ 451 SCR_REG_REG(reg,SCR_LOAD,data) 452 453#define SCR_LOAD_SFBR(data) \ 454 (SCR_REG_SFBR (gpreg, SCR_LOAD, data)) 455 456/*----------------------------------------------------------- 457** 458** LOAD from memory to register. 459** STORE from register to memory. 460** 461** Only supported by 810A, 860, 825A, 875, 895 and 896. 462** 463**----------------------------------------------------------- 464** 465** LOAD_ABS (LEN) 466** <<start address>> 467** 468** LOAD_REL (LEN) (DSA relative) 469** <<dsa_offset>> 470** 471**----------------------------------------------------------- 472*/ 473 474#define SCR_REG_OFS2(ofs) (((ofs) & 0xff) << 16ul) 475#define SCR_NO_FLUSH2 0x02000000 476#define SCR_DSA_REL2 0x10000000 477 478#define SCR_LOAD_R(reg, how, n) \ 479 (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n)) 480 481#define SCR_STORE_R(reg, how, n) \ 482 (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n)) 483 484#define SCR_LOAD_ABS(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2, n) 485#define SCR_LOAD_REL(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n) 486#define SCR_LOAD_ABS_F(reg, n) SCR_LOAD_R(reg, 0, n) 487#define SCR_LOAD_REL_F(reg, n) SCR_LOAD_R(reg, SCR_DSA_REL2, n) 488 489#define SCR_STORE_ABS(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2, n) 490#define SCR_STORE_REL(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n) 491#define SCR_STORE_ABS_F(reg, n) SCR_STORE_R(reg, 0, n) 492#define SCR_STORE_REL_F(reg, n) SCR_STORE_R(reg, SCR_DSA_REL2, n) 493 494 495/*----------------------------------------------------------- 496** 497** Waiting for Disconnect or Reselect 498** 499**----------------------------------------------------------- 500** 501** JUMP [ | IFTRUE/IFFALSE ( ... ) ] 502** <<address>> 503** 504** JUMPR [ | IFTRUE/IFFALSE ( ... ) ] 505** <<distance>> 506** 507** CALL [ | IFTRUE/IFFALSE ( ... ) ] 508** <<address>> 509** 510** CALLR [ | IFTRUE/IFFALSE ( ... ) ] 511** <<distance>> 512** 513** RETURN [ | IFTRUE/IFFALSE ( ... ) ] 514** <<dummy>> 515** 516** INT [ | IFTRUE/IFFALSE ( ... ) ] 517** <<ident>> 518** 519** INT_FLY [ | IFTRUE/IFFALSE ( ... ) ] 520** <<ident>> 521** 522** Conditions: 523** WHEN (phase) 524** IF (phase) 525** CARRYSET 526** DATA (data, mask) 527** 528**----------------------------------------------------------- 529*/ 530 531#define SCR_NO_OP 0x80000000 532#define SCR_JUMP 0x80080000 533#define SCR_JUMP64 0x80480000 534#define SCR_JUMPR 0x80880000 535#define SCR_CALL 0x88080000 536#define SCR_CALLR 0x88880000 537#define SCR_RETURN 0x90080000 538#define SCR_INT 0x98080000 539#define SCR_INT_FLY 0x98180000 540 541#define IFFALSE(arg) (0x00080000 | (arg)) 542#define IFTRUE(arg) (0x00000000 | (arg)) 543 544#define WHEN(phase) (0x00030000 | (phase)) 545#define IF(phase) (0x00020000 | (phase)) 546 547#define DATA(D) (0x00040000 | ((D) & 0xff)) 548#define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff)) 549 550#define CARRYSET (0x00200000) 551 552 553#define SIR_COMPLETE 0x10000000 554/* script errors */ 555#define SIR_SEL_ATN_NO_MSG_OUT 0x00000001 556#define SIR_CMD_OUT_ILL_PH 0x00000002 557#define SIR_STATUS_ILL_PH 0x00000003 558#define SIR_MSG_RECEIVED 0x00000004 559#define SIR_DATA_IN_ERR 0x00000005 560#define SIR_DATA_OUT_ERR 0x00000006 561#define SIR_SCRIPT_ERROR 0x00000007 562#define SIR_MSG_OUT_NO_CMD 0x00000008 563#define SIR_MSG_OVER7 0x00000009 564/* Fly interrupt */ 565#define INT_ON_FY 0x00000080 566 567/* Hardware errors are defined in scsi.h */ 568 569#define SCSI_IDENTIFY 0xC0 570 571#ifndef TRUE 572#define TRUE 1 573#endif 574#ifndef FALSE 575#define FALSE 0 576#endif 577 578#endif 579