1/* 2 * (C) Copyright 2002 3 * Lineo, Inc. <www.lineo.com> 4 * Bernhard Kuhn <bkuhn@lineo.com> 5 * 6 * (C) Copyright 2002 7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 8 * Marius Groeger <mgroeger@sysgo.de> 9 * 10 * (C) Copyright 2002 11 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 12 * Alex Zuepke <azu@sysgo.de> 13 * 14 * See file CREDITS for list of people who contributed to this 15 * project. 16 * 17 * This program is free software; you can redistribute it and/or 18 * modify it under the terms of the GNU General Public License as 19 * published by the Free Software Foundation; either version 2 of 20 * the License, or (at your option) any later version. 21 * 22 * This program is distributed in the hope that it will be useful, 23 * but WITHOUT ANY WARRANTY; without even the implied warranty of 24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 25 * GNU General Public License for more details. 26 * 27 * You should have received a copy of the GNU General Public License 28 * along with this program; if not, write to the Free Software 29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 30 * MA 02111-1307 USA 31 */ 32 33#include <common.h> 34 35#include <asm/io.h> 36#include <asm/arch/hardware.h> 37#include <asm/arch/at91_tc.h> 38#include <asm/arch/at91_pmc.h> 39 40DECLARE_GLOBAL_DATA_PTR; 41 42/* the number of clocks per CONFIG_SYS_HZ */ 43#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK/CONFIG_SYS_HZ) 44 45int timer_init(void) 46{ 47 at91_tc_t *tc = (at91_tc_t *) ATMEL_BASE_TC; 48 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; 49 50 /* enables TC1.0 clock */ 51 writel(1 << ATMEL_ID_TC0, &pmc->pcer); /* enable clock */ 52 53 writel(0, &tc->bcr); 54 writel(AT91_TC_BMR_TC0XC0S_NONE | AT91_TC_BMR_TC1XC1S_NONE | 55 AT91_TC_BMR_TC2XC2S_NONE , &tc->bmr); 56 57 writel(AT91_TC_CCR_CLKDIS, &tc->tc[0].ccr); 58 /* set to MCLK/2 and restart the timer 59 when the value in TC_RC is reached */ 60 writel(AT91_TC_CMR_TCCLKS_CLOCK1 | AT91_TC_CMR_CPCTRG, &tc->tc[0].cmr); 61 62 writel(0xFFFFFFFF, &tc->tc[0].idr); /* disable interrupts */ 63 writel(TIMER_LOAD_VAL, &tc->tc[0].rc); 64 65 writel(AT91_TC_CCR_SWTRG | AT91_TC_CCR_CLKEN, &tc->tc[0].ccr); 66 gd->lastinc = 0; 67 gd->tbl = 0; 68 69 return 0; 70} 71 72/* 73 * timer without interrupts 74 */ 75ulong get_timer(ulong base) 76{ 77 return get_timer_masked() - base; 78} 79 80void __udelay(unsigned long usec) 81{ 82 udelay_masked(usec); 83} 84 85ulong get_timer_raw(void) 86{ 87 at91_tc_t *tc = (at91_tc_t *) ATMEL_BASE_TC; 88 u32 now; 89 90 now = readl(&tc->tc[0].cv) & 0x0000ffff; 91 92 if (now >= gd->lastinc) { 93 /* normal mode */ 94 gd->tbl += now - gd->lastinc; 95 } else { 96 /* we have an overflow ... */ 97 gd->tbl += now + TIMER_LOAD_VAL - gd->lastinc; 98 } 99 gd->lastinc = now; 100 101 return gd->tbl; 102} 103 104ulong get_timer_masked(void) 105{ 106 return get_timer_raw()/TIMER_LOAD_VAL; 107} 108 109void udelay_masked(unsigned long usec) 110{ 111 u32 tmo; 112 u32 endtime; 113 signed long diff; 114 115 tmo = CONFIG_SYS_HZ_CLOCK / 1000; 116 tmo *= usec; 117 tmo /= 1000; 118 119 endtime = get_timer_raw() + tmo; 120 121 do { 122 u32 now = get_timer_raw(); 123 diff = endtime - now; 124 } while (diff >= 0); 125} 126 127/* 128 * This function is derived from PowerPC code (read timebase as long long). 129 * On ARM it just returns the timer value. 130 */ 131unsigned long long get_ticks(void) 132{ 133 return get_timer(0); 134} 135 136/* 137 * This function is derived from PowerPC code (timebase clock frequency). 138 * On ARM it returns the number of timer ticks per second. 139 */ 140ulong get_tbclk(void) 141{ 142 return CONFIG_SYS_HZ; 143} 144