LXR uboot/arch/arm/cpu/armv7/omap3/clock.c

   1/*
   2 * (C) Copyright 2008
   3 * Texas Instruments, <www.ti.com>
   4 *
   5 * Author :
   6 *      Manikandan Pillai <mani.pillai@ti.com>
   7 *
   8 * Derived from Beagle Board and OMAP3 SDP code by
   9 *      Richard Woodruff <r-woodruff2@ti.com>
  10 *      Syed Mohammed Khasim <khasim@ti.com>
  11 *
  12 * This program is free software; you can redistribute it and/or
  13 * modify it under the terms of the GNU General Public License as
  14 * published by the Free Software Foundation; either version 2 of
  15 * the License, or (at your option) any later version.
  16 *
  17 * This program is distributed in the hope that it will be useful,
  18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20 * GNU General Public License for more details.
  21 *
  22 * You should have received a copy of the GNU General Public License
  23 * along with this program; if not, write to the Free Software
  24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25 * MA 02111-1307 USA
  26 */
  27
  28#include <common.h>
  29#include <asm/io.h>
  30#include <asm/arch/clocks.h>
  31#include <asm/arch/clocks_omap3.h>
  32#include <asm/arch/mem.h>
  33#include <asm/arch/sys_proto.h>
  34#include <environment.h>
  35#include <command.h>
  36
  37/******************************************************************************
  38 * get_sys_clk_speed() - determine reference oscillator speed
  39 *                       based on known 32kHz clock and gptimer.
  40 *****************************************************************************/
  41u32 get_osc_clk_speed(void)
  42{
  43        u32 start, cstart, cend, cdiff, cdiv, val;
  44        struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
  45        struct prm *prm_base = (struct prm *)PRM_BASE;
  46        struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1;
  47        struct s32ktimer *s32k_base = (struct s32ktimer *)SYNC_32KTIMER_BASE;
  48
  49        val = readl(&prm_base->clksrc_ctrl);
  50
  51        if (val & SYSCLKDIV_2)
  52                cdiv = 2;
  53        else
  54                cdiv = 1;
  55
  56        /* enable timer2 */
  57        val = readl(&prcm_base->clksel_wkup) | CLKSEL_GPT1;
  58
  59        /* select sys_clk for GPT1 */
  60        writel(val, &prcm_base->clksel_wkup);
  61
  62        /* Enable I and F Clocks for GPT1 */
  63        val = readl(&prcm_base->iclken_wkup) | EN_GPT1 | EN_32KSYNC;
  64        writel(val, &prcm_base->iclken_wkup);
  65
  66        val = readl(&prcm_base->fclken_wkup) | EN_GPT1;
  67        writel(val, &prcm_base->fclken_wkup);
  68
  69        writel(0, &gpt1_base->tldr);            /* start counting at 0 */
  70        writel(GPT_EN, &gpt1_base->tclr);       /* enable clock */
  71
  72        /* enable 32kHz source, determine sys_clk via gauging */
  73
  74        /* start time in 20 cycles */
  75        start = 20 + readl(&s32k_base->s32k_cr);
  76
  77        /* dead loop till start time */
  78        while (readl(&s32k_base->s32k_cr) < start);
  79
  80        /* get start sys_clk count */
  81        cstart = readl(&gpt1_base->tcrr);
  82
  83        /* wait for 40 cycles */
  84        while (readl(&s32k_base->s32k_cr) < (start + 20)) ;
  85        cend = readl(&gpt1_base->tcrr);         /* get end sys_clk count */
  86        cdiff = cend - cstart;                  /* get elapsed ticks */
  87        cdiff *= cdiv;
  88
  89        /* based on number of ticks assign speed */
  90        if (cdiff > 19000)
  91                return S38_4M;
  92        else if (cdiff > 15200)
  93                return S26M;
  94        else if (cdiff > 13000)
  95                return S24M;
  96        else if (cdiff > 9000)
  97                return S19_2M;
  98        else if (cdiff > 7600)
  99                return S13M;
 100        else
 101                return S12M;
 102}
 103
 104/******************************************************************************
 105 * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on
 106 *                       input oscillator clock frequency.
 107 *****************************************************************************/
 108void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel)
 109{
 110        switch(osc_clk) {
 111        case S38_4M:
 112                *sys_clkin_sel = 4;
 113                break;
 114        case S26M:
 115                *sys_clkin_sel = 3;
 116                break;
 117        case S19_2M:
 118                *sys_clkin_sel = 2;
 119                break;
 120        case S13M:
 121                *sys_clkin_sel = 1;
 122                break;
 123        case S12M:
 124        default:
 125                *sys_clkin_sel = 0;
 126        }
 127}
 128
 129/*
 130 * OMAP34XX/35XX specific functions
 131 */
 132
 133static void dpll3_init_34xx(u32 sil_index, u32 clk_index)
 134{
 135        struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 136        dpll_param *ptr = (dpll_param *) get_core_dpll_param();
 137        void (*f_lock_pll) (u32, u32, u32, u32);
 138        int xip_safe, p0, p1, p2, p3;
 139
 140        xip_safe = is_running_in_sram();
 141
 142        /* Moving to the right sysclk and ES rev base */
 143        ptr = ptr + (3 * clk_index) + sil_index;
 144
 145        if (xip_safe) {
 146                /*
 147                 * CORE DPLL
 148                 * sr32(CM_CLKSEL2_EMU) set override to work when asleep
 149                 */
 150                sr32(&prcm_base->clken_pll, 0, 3, PLL_FAST_RELOCK_BYPASS);
 151                wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen,
 152                                LDELAY);
 153
 154                /*
 155                 * For OMAP3 ES1.0 Errata 1.50, default value directly doesn't
 156                 * work. write another value and then default value.
 157                 */
 158
 159                /* CM_CLKSEL1_EMU[DIV_DPLL3] */
 160                sr32(&prcm_base->clksel1_emu, 16, 5, (CORE_M3X2 + 1)) ;
 161                sr32(&prcm_base->clksel1_emu, 16, 5, CORE_M3X2);
 162
 163                /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
 164                sr32(&prcm_base->clksel1_pll, 27, 5, ptr->m2);
 165
 166                /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
 167                sr32(&prcm_base->clksel1_pll, 16, 11, ptr->m);
 168
 169                /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
 170                sr32(&prcm_base->clksel1_pll, 8, 7, ptr->n);
 171
 172                /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
 173                sr32(&prcm_base->clksel1_pll, 6, 1, 0);
 174
 175                /* SSI */
 176                sr32(&prcm_base->clksel_core, 8, 4, CORE_SSI_DIV);
 177                /* FSUSB */
 178                sr32(&prcm_base->clksel_core, 4, 2, CORE_FUSB_DIV);
 179                /* L4 */
 180                sr32(&prcm_base->clksel_core, 2, 2, CORE_L4_DIV);
 181                /* L3 */
 182                sr32(&prcm_base->clksel_core, 0, 2, CORE_L3_DIV);
 183                /* GFX */
 184                sr32(&prcm_base->clksel_gfx,  0, 3, GFX_DIV);
 185                /* RESET MGR */
 186                sr32(&prcm_base->clksel_wkup, 1, 2, WKUP_RSM);
 187                /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
 188                sr32(&prcm_base->clken_pll,   4, 4, ptr->fsel);
 189                /* LOCK MODE */
 190                sr32(&prcm_base->clken_pll,   0, 3, PLL_LOCK);
 191
 192                wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen,
 193                                LDELAY);
 194        } else if (is_running_in_flash()) {
 195                /*
 196                 * if running from flash, jump to small relocated code
 197                 * area in SRAM.
 198                 */
 199                f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start +
 200                                SRAM_VECT_CODE);
 201
 202                p0 = readl(&prcm_base->clken_pll);
 203                sr32(&p0, 0, 3, PLL_FAST_RELOCK_BYPASS);
 204                /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
 205                sr32(&p0, 4, 4, ptr->fsel);
 206
 207                p1 = readl(&prcm_base->clksel1_pll);
 208                /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
 209                sr32(&p1, 27, 5, ptr->m2);
 210                /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
 211                sr32(&p1, 16, 11, ptr->m);
 212                /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
 213                sr32(&p1, 8, 7, ptr->n);
 214                /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
 215                sr32(&p1, 6, 1, 0);
 216
 217                p2 = readl(&prcm_base->clksel_core);
 218                /* SSI */
 219                sr32(&p2, 8, 4, CORE_SSI_DIV);
 220                /* FSUSB */
 221                sr32(&p2, 4, 2, CORE_FUSB_DIV);
 222                /* L4 */
 223                sr32(&p2, 2, 2, CORE_L4_DIV);
 224                /* L3 */
 225                sr32(&p2, 0, 2, CORE_L3_DIV);
 226
 227                p3 = (u32)&prcm_base->idlest_ckgen;
 228
 229                (*f_lock_pll) (p0, p1, p2, p3);
 230        }
 231}
 232
 233static void dpll4_init_34xx(u32 sil_index, u32 clk_index)
 234{
 235        struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 236        dpll_param *ptr = (dpll_param *) get_per_dpll_param();
 237
 238        /* Moving it to the right sysclk base */
 239        ptr = ptr + clk_index;
 240
 241        /* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */
 242        sr32(&prcm_base->clken_pll, 16, 3, PLL_STOP);
 243        wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);
 244
 245        /*
 246         * Errata 1.50 Workaround for OMAP3 ES1.0 only
 247         * If using default divisors, write default divisor + 1
 248         * and then the actual divisor value
 249         */
 250        /* M6 */
 251        sr32(&prcm_base->clksel1_emu, 24, 5, (PER_M6X2 + 1));
 252        sr32(&prcm_base->clksel1_emu, 24, 5, PER_M6X2);
 253        /* M5 */
 254        sr32(&prcm_base->clksel_cam, 0, 5, (PER_M5X2 + 1));
 255        sr32(&prcm_base->clksel_cam, 0, 5, PER_M5X2);
 256        /* M4 */
 257        sr32(&prcm_base->clksel_dss, 0, 5, (PER_M4X2 + 1));
 258        sr32(&prcm_base->clksel_dss, 0, 5, PER_M4X2);
 259        /* M3 */
 260        sr32(&prcm_base->clksel_dss, 8, 5, (PER_M3X2 + 1));
 261        sr32(&prcm_base->clksel_dss, 8, 5, PER_M3X2);
 262        /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */
 263        sr32(&prcm_base->clksel3_pll, 0, 5, (ptr->m2 + 1));
 264        sr32(&prcm_base->clksel3_pll, 0, 5, ptr->m2);
 265        /* Workaround end */
 266
 267        /* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:18] */
 268        sr32(&prcm_base->clksel2_pll, 8, 11, ptr->m);
 269
 270        /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
 271        sr32(&prcm_base->clksel2_pll, 0, 7, ptr->n);
 272
 273        /* FREQSEL (PERIPH_DPLL_FREQSEL): CM_CLKEN_PLL[20:23] */
 274        sr32(&prcm_base->clken_pll, 20, 4, ptr->fsel);
 275
 276        /* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */
 277        sr32(&prcm_base->clken_pll, 16, 3, PLL_LOCK);
 278        wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
 279}
 280
 281static void dpll5_init_34xx(u32 sil_index, u32 clk_index)
 282{
 283        struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 284        dpll_param *ptr = (dpll_param *) get_per2_dpll_param();
 285
 286        /* Moving it to the right sysclk base */
 287        ptr = ptr + clk_index;
 288
 289        /* PER2 DPLL (DPLL5) */
 290        sr32(&prcm_base->clken2_pll, 0, 3, PLL_STOP);
 291        wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY);
 292        sr32(&prcm_base->clksel5_pll, 0, 5, ptr->m2); /* set M2 (usbtll_fck) */
 293        sr32(&prcm_base->clksel4_pll, 8, 11, ptr->m); /* set m (11-bit multiplier) */
 294        sr32(&prcm_base->clksel4_pll, 0, 7, ptr->n); /* set n (7-bit divider)*/
 295        sr32(&prcm_base->clken_pll, 4, 4, ptr->fsel);   /* FREQSEL */
 296        sr32(&prcm_base->clken2_pll, 0, 3, PLL_LOCK);   /* lock mode */
 297        wait_on_value(1, 1, &prcm_base->idlest2_ckgen, LDELAY);
 298}
 299
 300static void mpu_init_34xx(u32 sil_index, u32 clk_index)
 301{
 302        struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 303        dpll_param *ptr = (dpll_param *) get_mpu_dpll_param();
 304
 305        /* Moving to the right sysclk and ES rev base */
 306        ptr = ptr + (3 * clk_index) + sil_index;
 307
 308        /* MPU DPLL (unlocked already) */
 309
 310        /* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */
 311        sr32(&prcm_base->clksel2_pll_mpu, 0, 5, ptr->m2);
 312
 313        /* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */
 314        sr32(&prcm_base->clksel1_pll_mpu, 8, 11, ptr->m);
 315
 316        /* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */
 317        sr32(&prcm_base->clksel1_pll_mpu, 0, 7, ptr->n);
 318
 319        /* FREQSEL (MPU_DPLL_FREQSEL) : CM_CLKEN_PLL_MPU[4:7] */
 320        sr32(&prcm_base->clken_pll_mpu, 4, 4, ptr->fsel);
 321}
 322
 323static void iva_init_34xx(u32 sil_index, u32 clk_index)
 324{
 325        struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 326        dpll_param *ptr = (dpll_param *) get_iva_dpll_param();
 327
 328        /* Moving to the right sysclk and ES rev base */
 329        ptr = ptr + (3 * clk_index) + sil_index;
 330
 331        /* IVA DPLL */
 332        /* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */
 333        sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_STOP);
 334        wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY);
 335
 336        /* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */
 337        sr32(&prcm_base->clksel2_pll_iva2, 0, 5, ptr->m2);
 338
 339        /* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */
 340        sr32(&prcm_base->clksel1_pll_iva2, 8, 11, ptr->m);
 341
 342        /* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */
 343        sr32(&prcm_base->clksel1_pll_iva2, 0, 7, ptr->n);
 344
 345        /* FREQSEL (IVA2_DPLL_FREQSEL) : CM_CLKEN_PLL_IVA2[4:7] */
 346        sr32(&prcm_base->clken_pll_iva2, 4, 4, ptr->fsel);
 347
 348        /* LOCK MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
 349        sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_LOCK);
 350
 351        wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY);
 352}
 353
 354/*
 355 * OMAP3630 specific functions
 356 */
 357
 358static void dpll3_init_36xx(u32 sil_index, u32 clk_index)
 359{
 360        struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 361        dpll_param *ptr = (dpll_param *) get_36x_core_dpll_param();
 362        void (*f_lock_pll) (u32, u32, u32, u32);
 363        int xip_safe, p0, p1, p2, p3;
 364
 365        xip_safe = is_running_in_sram();
 366
 367        /* Moving it to the right sysclk base */
 368        ptr += clk_index;
 369
 370        if (xip_safe) {
 371                /* CORE DPLL */
 372
 373                /* Select relock bypass: CM_CLKEN_PLL[0:2] */
 374                sr32(&prcm_base->clken_pll, 0, 3, PLL_FAST_RELOCK_BYPASS);
 375                wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen,
 376                                LDELAY);
 377
 378                /* CM_CLKSEL1_EMU[DIV_DPLL3] */
 379                sr32(&prcm_base->clksel1_emu, 16, 5, CORE_M3X2);
 380
 381                /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
 382                sr32(&prcm_base->clksel1_pll, 27, 5, ptr->m2);
 383
 384                /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
 385                sr32(&prcm_base->clksel1_pll, 16, 11, ptr->m);
 386
 387                /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
 388                sr32(&prcm_base->clksel1_pll, 8, 7, ptr->n);
 389
 390                /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
 391                sr32(&prcm_base->clksel1_pll, 6, 1, 0);
 392
 393                /* SSI */
 394                sr32(&prcm_base->clksel_core, 8, 4, CORE_SSI_DIV);
 395                /* FSUSB */
 396                sr32(&prcm_base->clksel_core, 4, 2, CORE_FUSB_DIV);
 397                /* L4 */
 398                sr32(&prcm_base->clksel_core, 2, 2, CORE_L4_DIV);
 399                /* L3 */
 400                sr32(&prcm_base->clksel_core, 0, 2, CORE_L3_DIV);
 401                /* GFX */
 402                sr32(&prcm_base->clksel_gfx,  0, 3, GFX_DIV_36X);
 403                /* RESET MGR */
 404                sr32(&prcm_base->clksel_wkup, 1, 2, WKUP_RSM);
 405                /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
 406                sr32(&prcm_base->clken_pll,   4, 4, ptr->fsel);
 407                /* LOCK MODE */
 408                sr32(&prcm_base->clken_pll,   0, 3, PLL_LOCK);
 409
 410                wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen,
 411                                LDELAY);
 412        } else if (is_running_in_flash()) {
 413                /*
 414                 * if running from flash, jump to small relocated code
 415                 * area in SRAM.
 416                 */
 417                f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start +
 418                                SRAM_VECT_CODE);
 419
 420                p0 = readl(&prcm_base->clken_pll);
 421                sr32(&p0, 0, 3, PLL_FAST_RELOCK_BYPASS);
 422                /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
 423                sr32(&p0, 4, 4, ptr->fsel);
 424
 425                p1 = readl(&prcm_base->clksel1_pll);
 426                /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
 427                sr32(&p1, 27, 5, ptr->m2);
 428                /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
 429                sr32(&p1, 16, 11, ptr->m);
 430                /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
 431                sr32(&p1, 8, 7, ptr->n);
 432                /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
 433                sr32(&p1, 6, 1, 0);
 434
 435                p2 = readl(&prcm_base->clksel_core);
 436                /* SSI */
 437                sr32(&p2, 8, 4, CORE_SSI_DIV);
 438                /* FSUSB */
 439                sr32(&p2, 4, 2, CORE_FUSB_DIV);
 440                /* L4 */
 441                sr32(&p2, 2, 2, CORE_L4_DIV);
 442                /* L3 */
 443                sr32(&p2, 0, 2, CORE_L3_DIV);
 444
 445                p3 = (u32)&prcm_base->idlest_ckgen;
 446
 447                (*f_lock_pll) (p0, p1, p2, p3);
 448        }
 449}
 450
 451static void dpll4_init_36xx(u32 sil_index, u32 clk_index)
 452{
 453        struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 454        struct dpll_per_36x_param *ptr;
 455
 456        ptr = (struct dpll_per_36x_param *)get_36x_per_dpll_param();
 457
 458        /* Moving it to the right sysclk base */
 459        ptr += clk_index;
 460
 461        /* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */
 462        sr32(&prcm_base->clken_pll, 16, 3, PLL_STOP);
 463        wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);
 464
 465        /* M6 (DIV_DPLL4): CM_CLKSEL1_EMU[24:29] */
 466        sr32(&prcm_base->clksel1_emu, 24, 6, ptr->m6);
 467
 468        /* M5 (CLKSEL_CAM): CM_CLKSEL1_EMU[0:5] */
 469        sr32(&prcm_base->clksel_cam, 0, 6, ptr->m5);
 470
 471        /* M4 (CLKSEL_DSS1): CM_CLKSEL_DSS[0:5] */
 472        sr32(&prcm_base->clksel_dss, 0, 6, ptr->m4);
 473
 474        /* M3 (CLKSEL_DSS1): CM_CLKSEL_DSS[8:13] */
 475        sr32(&prcm_base->clksel_dss, 8, 6, ptr->m3);
 476
 477        /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */
 478        sr32(&prcm_base->clksel3_pll, 0, 5, ptr->m2);
 479
 480        /* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:19] */
 481        sr32(&prcm_base->clksel2_pll, 8, 12, ptr->m);
 482
 483        /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
 484        sr32(&prcm_base->clksel2_pll, 0, 7, ptr->n);
 485
 486        /* M2DIV (CLKSEL_96M): CM_CLKSEL_CORE[12:13] */
 487        sr32(&prcm_base->clksel_core, 12, 2, ptr->m2div);
 488
 489        /* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */
 490        sr32(&prcm_base->clken_pll, 16, 3, PLL_LOCK);
 491        wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
 492}
 493
 494static void mpu_init_36xx(u32 sil_index, u32 clk_index)
 495{
 496        struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 497        dpll_param *ptr = (dpll_param *) get_36x_mpu_dpll_param();
 498
 499        /* Moving to the right sysclk */
 500        ptr += clk_index;
 501
 502        /* MPU DPLL (unlocked already */
 503
 504        /* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */
 505        sr32(&prcm_base->clksel2_pll_mpu, 0, 5, ptr->m2);
 506
 507        /* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */
 508        sr32(&prcm_base->clksel1_pll_mpu, 8, 11, ptr->m);
 509
 510        /* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */
 511        sr32(&prcm_base->clksel1_pll_mpu, 0, 7, ptr->n);
 512}
 513
 514static void iva_init_36xx(u32 sil_index, u32 clk_index)
 515{
 516        struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 517        dpll_param *ptr = (dpll_param *)get_36x_iva_dpll_param();
 518
 519        /* Moving to the right sysclk */
 520        ptr += clk_index;
 521
 522        /* IVA DPLL */
 523        /* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */
 524        sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_STOP);
 525        wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY);
 526
 527        /* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */
 528        sr32(&prcm_base->clksel2_pll_iva2, 0, 5, ptr->m2);
 529
 530        /* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */
 531        sr32(&prcm_base->clksel1_pll_iva2, 8, 11, ptr->m);
 532
 533        /* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */
 534        sr32(&prcm_base->clksel1_pll_iva2, 0, 7, ptr->n);
 535
 536        /* LOCK (MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
 537        sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_LOCK);
 538
 539        wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY);
 540}
 541
 542/******************************************************************************
 543 * prcm_init() - inits clocks for PRCM as defined in clocks.h
 544 *               called from SRAM, or Flash (using temp SRAM stack).
 545 *****************************************************************************/
 546void prcm_init(void)
 547{
 548        u32 osc_clk = 0, sys_clkin_sel;
 549        u32 clk_index, sil_index = 0;
 550        struct prm *prm_base = (struct prm *)PRM_BASE;
 551        struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 552
 553        /*
 554         * Gauge the input clock speed and find out the sys_clkin_sel
 555         * value corresponding to the input clock.
 556         */
 557        osc_clk = get_osc_clk_speed();
 558        get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
 559
 560        /* set input crystal speed */
 561        sr32(&prm_base->clksel, 0, 3, sys_clkin_sel);
 562
 563        /* If the input clock is greater than 19.2M always divide/2 */
 564        if (sys_clkin_sel > 2) {
 565                /* input clock divider */
 566                sr32(&prm_base->clksrc_ctrl, 6, 2, 2);
 567                clk_index = sys_clkin_sel / 2;
 568        } else {
 569                /* input clock divider */
 570                sr32(&prm_base->clksrc_ctrl, 6, 2, 1);
 571                clk_index = sys_clkin_sel;
 572        }
 573
 574        if (get_cpu_family() == CPU_OMAP36XX) {
 575                /*
 576                 * In warm reset conditions on OMAP36xx/AM/DM37xx
 577                 * the rom code incorrectly sets the DPLL4 clock
 578                 * input divider to /6.5. Section 3.5.3.3.3.2.1 of
 579                 * the AM/DM37x TRM explains that the /6.5 divider
 580                 * is used only when the input clock is 13MHz.
 581                 *
 582                 * If the part is in this cpu family *and* the input
 583                 * clock *is not* 13 MHz, then reset the DPLL4 clock
 584                 * input divider to /1 as it should never set to /6.5
 585                 * in this case.
 586                 */
 587                if (sys_clkin_sel != 1) /* 13 MHz */
 588                        /* Bit 8: DPLL4_CLKINP_DIV */
 589                        sr32(&prm_base->clksrc_ctrl, 8, 1, 0);
 590
 591                /* Unlock MPU DPLL (slows things down, and needed later) */
 592                sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS);
 593                wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
 594                                LDELAY);
 595
 596                dpll3_init_36xx(0, clk_index);
 597                dpll4_init_36xx(0, clk_index);
 598                dpll5_init_34xx(0, clk_index);
 599                iva_init_36xx(0, clk_index);
 600                mpu_init_36xx(0, clk_index);
 601
 602                /* Lock MPU DPLL to set frequency */
 603                sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOCK);
 604                wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu,
 605                                LDELAY);
 606        } else {
 607                /*
 608                 * The DPLL tables are defined according to sysclk value and
 609                 * silicon revision. The clk_index value will be used to get
 610                 * the values for that input sysclk from the DPLL param table
 611                 * and sil_index will get the values for that SysClk for the
 612                 * appropriate silicon rev.
 613                 */
 614                if (((get_cpu_family() == CPU_OMAP34XX)
 615                                && (get_cpu_rev() >= CPU_3XX_ES20)) ||
 616                        (get_cpu_family() == CPU_AM35XX))
 617                        sil_index = 1;
 618
 619                /* Unlock MPU DPLL (slows things down, and needed later) */
 620                sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS);
 621                wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
 622                                LDELAY);
 623
 624                dpll3_init_34xx(sil_index, clk_index);
 625                dpll4_init_34xx(sil_index, clk_index);
 626                dpll5_init_34xx(sil_index, clk_index);
 627                if (get_cpu_family() != CPU_AM35XX)
 628                        iva_init_34xx(sil_index, clk_index);
 629
 630                mpu_init_34xx(sil_index, clk_index);
 631
 632                /* Lock MPU DPLL to set frequency */
 633                sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOCK);
 634                wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu,
 635                                LDELAY);
 636        }
 637
 638        /* Set up GPTimers to sys_clk source only */
 639        sr32(&prcm_base->clksel_per, 0, 8, 0xff);
 640        sr32(&prcm_base->clksel_wkup, 0, 1, 1);
 641
 642        sdelay(5000);
 643}
 644
 645/*
 646 * Enable usb ehci uhh, tll clocks
 647 */
 648void ehci_clocks_enable(void)
 649{
 650        struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 651
 652        /* Enable USBHOST_L3_ICLK (USBHOST_MICLK) */
 653        sr32(&prcm_base->iclken_usbhost, 0, 1, 1);
 654        /*
 655         * Enable USBHOST_48M_FCLK (USBHOST_FCLK1)
 656         * and USBHOST_120M_FCLK (USBHOST_FCLK2)
 657         */
 658        sr32(&prcm_base->fclken_usbhost, 0, 2, 3);
 659        /* Enable USBTTL_ICLK */
 660        sr32(&prcm_base->iclken3_core, 2, 1, 1);
 661        /* Enable USBTTL_FCLK */
 662        sr32(&prcm_base->fclken3_core, 2, 1, 1);
 663}
 664
 665/******************************************************************************
 666 * peripheral_enable() - Enable the clks & power for perifs (GPT2, UART1,...)
 667 *****************************************************************************/
 668void per_clocks_enable(void)
 669{
 670        struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 671
 672        /* Enable GP2 timer. */
 673        sr32(&prcm_base->clksel_per, 0, 1, 0x1);        /* GPT2 = sys clk */
 674        sr32(&prcm_base->iclken_per, 3, 1, 0x1);        /* ICKen GPT2 */
 675        sr32(&prcm_base->fclken_per, 3, 1, 0x1);        /* FCKen GPT2 */
 676
 677#ifdef CONFIG_SYS_NS16550
 678        /* Enable UART1 clocks */
 679        sr32(&prcm_base->fclken1_core, 13, 1, 0x1);
 680        sr32(&prcm_base->iclken1_core, 13, 1, 0x1);
 681
 682        /* UART 3 Clocks */
 683        sr32(&prcm_base->fclken_per, 11, 1, 0x1);
 684        sr32(&prcm_base->iclken_per, 11, 1, 0x1);
 685#endif
 686
 687#ifdef CONFIG_OMAP3_GPIO_2
 688        sr32(&prcm_base->fclken_per, 13, 1, 1);
 689        sr32(&prcm_base->iclken_per, 13, 1, 1);
 690#endif
 691#ifdef CONFIG_OMAP3_GPIO_3
 692        sr32(&prcm_base->fclken_per, 14, 1, 1);
 693        sr32(&prcm_base->iclken_per, 14, 1, 1);
 694#endif
 695#ifdef CONFIG_OMAP3_GPIO_4
 696        sr32(&prcm_base->fclken_per, 15, 1, 1);
 697        sr32(&prcm_base->iclken_per, 15, 1, 1);
 698#endif
 699#ifdef CONFIG_OMAP3_GPIO_5
 700        sr32(&prcm_base->fclken_per, 16, 1, 1);
 701        sr32(&prcm_base->iclken_per, 16, 1, 1);
 702#endif
 703#ifdef CONFIG_OMAP3_GPIO_6
 704        sr32(&prcm_base->fclken_per, 17, 1, 1);
 705        sr32(&prcm_base->iclken_per, 17, 1, 1);
 706#endif
 707
 708#ifdef CONFIG_DRIVER_OMAP34XX_I2C
 709        /* Turn on all 3 I2C clocks */
 710        sr32(&prcm_base->fclken1_core, 15, 3, 0x7);
 711        sr32(&prcm_base->iclken1_core, 15, 3, 0x7);     /* I2C1,2,3 = on */
 712#endif
 713        /* Enable the ICLK for 32K Sync Timer as its used in udelay */
 714        sr32(&prcm_base->iclken_wkup, 2, 1, 0x1);
 715
 716        if (get_cpu_family() != CPU_AM35XX)
 717                sr32(&prcm_base->fclken_iva2, 0, 32, FCK_IVA2_ON);
 718
 719        sr32(&prcm_base->fclken1_core, 0, 32, FCK_CORE1_ON);
 720        sr32(&prcm_base->iclken1_core, 0, 32, ICK_CORE1_ON);
 721        sr32(&prcm_base->iclken2_core, 0, 32, ICK_CORE2_ON);
 722        sr32(&prcm_base->fclken_wkup, 0, 32, FCK_WKUP_ON);
 723        sr32(&prcm_base->iclken_wkup, 0, 32, ICK_WKUP_ON);
 724        sr32(&prcm_base->fclken_dss, 0, 32, FCK_DSS_ON);
 725        sr32(&prcm_base->iclken_dss, 0, 32, ICK_DSS_ON);
 726        if (get_cpu_family() != CPU_AM35XX) {
 727                sr32(&prcm_base->fclken_cam, 0, 32, FCK_CAM_ON);
 728                sr32(&prcm_base->iclken_cam, 0, 32, ICK_CAM_ON);
 729        }
 730        sr32(&prcm_base->fclken_per, 0, 32, FCK_PER_ON);
 731        sr32(&prcm_base->iclken_per, 0, 32, ICK_PER_ON);
 732
 733        sdelay(1000);
 734}
 735