LXR uboot/arch/arm/imx-common/cpu.c

   1/*
   2 * (C) Copyright 2007
   3 * Sascha Hauer, Pengutronix
   4 *
   5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
   6 *
   7 * See file CREDITS for list of people who contributed to this
   8 * project.
   9 *
  10 * This program is free software; you can redistribute it and/or
  11 * modify it under the terms of the GNU General Public License as
  12 * published by the Free Software Foundation; either version 2 of
  13 * the License, or (at your option) any later version.
  14 *
  15 * This program is distributed in the hope that it will be useful,
  16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18 * GNU General Public License for more details.
  19 *
  20 * You should have received a copy of the GNU General Public License
  21 * along with this program; if not, write to the Free Software
  22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23 * MA 02111-1307 USA
  24 */
  25
  26#include <common.h>
  27#include <asm/errno.h>
  28#include <asm/io.h>
  29#include <asm/arch/imx-regs.h>
  30#include <asm/arch/clock.h>
  31#include <asm/arch/sys_proto.h>
  32#include <asm/arch/crm_regs.h>
  33#include <ipu_pixfmt.h>
  34
  35#ifdef CONFIG_FSL_ESDHC
  36#include <fsl_esdhc.h>
  37#endif
  38
  39char *get_reset_cause(void)
  40{
  41        u32 cause;
  42        struct src *src_regs = (struct src *)SRC_BASE_ADDR;
  43
  44        cause = readl(&src_regs->srsr);
  45        writel(cause, &src_regs->srsr);
  46
  47        switch (cause) {
  48        case 0x00001:
  49        case 0x00011:
  50                return "POR";
  51        case 0x00004:
  52                return "CSU";
  53        case 0x00008:
  54                return "IPP USER";
  55        case 0x00010:
  56                return "WDOG";
  57        case 0x00020:
  58                return "JTAG HIGH-Z";
  59        case 0x00040:
  60                return "JTAG SW";
  61        case 0x10000:
  62                return "WARM BOOT";
  63        default:
  64                return "unknown reset";
  65        }
  66}
  67
  68#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
  69#if defined(CONFIG_MX53)
  70#define MEMCTL_BASE     ESDCTL_BASE_ADDR;
  71#else
  72#define MEMCTL_BASE     MMDC_P0_BASE_ADDR;
  73#endif
  74static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
  75static const unsigned char bank_lookup[] = {3, 2};
  76
  77struct esd_mmdc_regs {
  78        uint32_t        ctl;
  79        uint32_t        pdc;
  80        uint32_t        otc;
  81        uint32_t        cfg0;
  82        uint32_t        cfg1;
  83        uint32_t        cfg2;
  84        uint32_t        misc;
  85        uint32_t        scr;
  86        uint32_t        ref;
  87        uint32_t        rsvd1;
  88        uint32_t        rsvd2;
  89        uint32_t        rwd;
  90        uint32_t        or;
  91        uint32_t        mrr;
  92        uint32_t        cfg3lp;
  93        uint32_t        mr4;
  94};
  95
  96#define ESD_MMDC_CTL_GET_ROW(mdctl)     ((ctl >> 24) & 7)
  97#define ESD_MMDC_CTL_GET_COLUMN(mdctl)  ((ctl >> 20) & 7)
  98#define ESD_MMDC_CTL_GET_WIDTH(mdctl)   ((ctl >> 16) & 3)
  99#define ESD_MMDC_CTL_GET_CS1(mdctl)     ((ctl >> 30) & 1)
 100#define ESD_MMDC_MISC_GET_BANK(mdmisc)  ((misc >> 5) & 1)
 101
 102unsigned imx_ddr_size(void)
 103{
 104        struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE;
 105        unsigned ctl = readl(&mem->ctl);
 106        unsigned misc = readl(&mem->misc);
 107        int bits = 11 + 0 + 0 + 1;      /* row + col + bank + width */
 108
 109        bits += ESD_MMDC_CTL_GET_ROW(ctl);
 110        bits += col_lookup[ESD_MMDC_CTL_GET_COLUMN(ctl)];
 111        bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)];
 112        bits += ESD_MMDC_CTL_GET_WIDTH(ctl);
 113        bits += ESD_MMDC_CTL_GET_CS1(ctl);
 114        return 1 << bits;
 115}
 116#endif
 117
 118#if defined(CONFIG_DISPLAY_CPUINFO)
 119
 120const char *get_imx_type(u32 imxtype)
 121{
 122        switch (imxtype) {
 123        case MXC_CPU_MX6Q:
 124                return "6Q";    /* Quad-core version of the mx6 */
 125        case MXC_CPU_MX6DL:
 126                return "6DL";   /* Dual Lite version of the mx6 */
 127        case MXC_CPU_MX6SOLO:
 128                return "6SOLO"; /* Solo version of the mx6 */
 129        case MXC_CPU_MX6SL:
 130                return "6SL";   /* Solo-Lite version of the mx6 */
 131        case MXC_CPU_MX51:
 132                return "51";
 133        case MXC_CPU_MX53:
 134                return "53";
 135        default:
 136                return "??";
 137        }
 138}
 139
 140int print_cpuinfo(void)
 141{
 142        u32 cpurev;
 143
 144        cpurev = get_cpu_rev();
 145
 146        printf("CPU:   Freescale i.MX%s rev%d.%d at %d MHz\n",
 147                get_imx_type((cpurev & 0xFF000) >> 12),
 148                (cpurev & 0x000F0) >> 4,
 149                (cpurev & 0x0000F) >> 0,
 150                mxc_get_clock(MXC_ARM_CLK) / 1000000);
 151        printf("Reset cause: %s\n", get_reset_cause());
 152        return 0;
 153}
 154#endif
 155
 156int cpu_eth_init(bd_t *bis)
 157{
 158        int rc = -ENODEV;
 159
 160#if defined(CONFIG_FEC_MXC)
 161        rc = fecmxc_initialize(bis);
 162#endif
 163
 164        return rc;
 165}
 166
 167#ifdef CONFIG_FSL_ESDHC
 168/*
 169 * Initializes on-chip MMC controllers.
 170 * to override, implement board_mmc_init()
 171 */
 172int cpu_mmc_init(bd_t *bis)
 173{
 174        return fsl_esdhc_mmc_init(bis);
 175}
 176#endif
 177
 178u32 get_ahb_clk(void)
 179{
 180        struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 181        u32 reg, ahb_podf;
 182
 183        reg = __raw_readl(&imx_ccm->cbcdr);
 184        reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
 185        ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
 186
 187        return get_periph_clk() / (ahb_podf + 1);
 188}
 189
 190#if defined(CONFIG_VIDEO_IPUV3)
 191void arch_preboot_os(void)
 192{
 193        /* disable video before launching O/S */
 194        ipuv3_fb_shutdown();
 195}
 196#endif
 197