1/* 2 * ddr_defs.h 3 * 4 * ddr specific header 5 * 6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19#ifndef _DDR_DEFS_H 20#define _DDR_DEFS_H 21 22#include <asm/arch/hardware.h> 23#include <asm/emif.h> 24 25/* AM335X EMIF Register values */ 26#define VTP_CTRL_READY (0x1 << 5) 27#define VTP_CTRL_ENABLE (0x1 << 6) 28#define VTP_CTRL_START_EN (0x1) 29#define PHY_DLL_LOCK_DIFF 0x0 30#define DDR_CKE_CTRL_NORMAL 0x1 31 32/* Micron MT47H128M16RT-25E */ 33#define MT47H128M16RT25E_EMIF_READ_LATENCY 0x100005 34#define MT47H128M16RT25E_EMIF_TIM1 0x0666B3C9 35#define MT47H128M16RT25E_EMIF_TIM2 0x243631CA 36#define MT47H128M16RT25E_EMIF_TIM3 0x0000033F 37#define MT47H128M16RT25E_EMIF_SDCFG 0x41805332 38#define MT47H128M16RT25E_EMIF_SDREF 0x0000081a 39#define MT47H128M16RT25E_DLL_LOCK_DIFF 0x0 40#define MT47H128M16RT25E_RATIO 0x80 41#define MT47H128M16RT25E_INVERT_CLKOUT 0x00 42#define MT47H128M16RT25E_RD_DQS 0x12 43#define MT47H128M16RT25E_WR_DQS 0x00 44#define MT47H128M16RT25E_PHY_WRLVL 0x00 45#define MT47H128M16RT25E_PHY_GATELVL 0x00 46#define MT47H128M16RT25E_PHY_WR_DATA 0x40 47#define MT47H128M16RT25E_PHY_FIFO_WE 0x80 48#define MT47H128M16RT25E_PHY_RANK0_DELAY 0x1 49#define MT47H128M16RT25E_IOCTRL_VALUE 0x18B 50 51/* Micron MT41J128M16JT-125 */ 52#define MT41J128MJT125_EMIF_READ_LATENCY 0x06 53#define MT41J128MJT125_EMIF_TIM1 0x0888A39B 54#define MT41J128MJT125_EMIF_TIM2 0x26337FDA 55#define MT41J128MJT125_EMIF_TIM3 0x501F830F 56#define MT41J128MJT125_EMIF_SDCFG 0x61C04AB2 57#define MT41J128MJT125_EMIF_SDREF 0x0000093B 58#define MT41J128MJT125_ZQ_CFG 0x50074BE4 59#define MT41J128MJT125_DLL_LOCK_DIFF 0x1 60#define MT41J128MJT125_RATIO 0x40 61#define MT41J128MJT125_INVERT_CLKOUT 0x1 62#define MT41J128MJT125_RD_DQS 0x3B 63#define MT41J128MJT125_WR_DQS 0x85 64#define MT41J128MJT125_PHY_WR_DATA 0xC1 65#define MT41J128MJT125_PHY_FIFO_WE 0x100 66#define MT41J128MJT125_IOCTRL_VALUE 0x18B 67 68/** 69 * Configure SDRAM 70 */ 71void config_sdram(const struct emif_regs *regs); 72 73/** 74 * Set SDRAM timings 75 */ 76void set_sdram_timings(const struct emif_regs *regs); 77 78/** 79 * Configure DDR PHY 80 */ 81void config_ddr_phy(const struct emif_regs *regs); 82 83/** 84 * This structure represents the DDR registers on AM33XX devices. 85 * We make use of DDR_PHY_BASE_ADDR2 to address the DATA1 registers that 86 * correspond to DATA1 registers defined here. 87 */ 88struct ddr_regs { 89 unsigned int resv0[7]; 90 unsigned int cm0csratio; /* offset 0x01C */ 91 unsigned int resv1[2]; 92 unsigned int cm0dldiff; /* offset 0x028 */ 93 unsigned int cm0iclkout; /* offset 0x02C */ 94 unsigned int resv2[8]; 95 unsigned int cm1csratio; /* offset 0x050 */ 96 unsigned int resv3[2]; 97 unsigned int cm1dldiff; /* offset 0x05C */ 98 unsigned int cm1iclkout; /* offset 0x060 */ 99 unsigned int resv4[8]; 100 unsigned int cm2csratio; /* offset 0x084 */ 101 unsigned int resv5[2]; 102 unsigned int cm2dldiff; /* offset 0x090 */ 103 unsigned int cm2iclkout; /* offset 0x094 */ 104 unsigned int resv6[12]; 105 unsigned int dt0rdsratio0; /* offset 0x0C8 */ 106 unsigned int resv7[4]; 107 unsigned int dt0wdsratio0; /* offset 0x0DC */ 108 unsigned int resv8[4]; 109 unsigned int dt0wiratio0; /* offset 0x0F0 */ 110 unsigned int resv9; 111 unsigned int dt0wimode0; /* offset 0x0F8 */ 112 unsigned int dt0giratio0; /* offset 0x0FC */ 113 unsigned int resv10; 114 unsigned int dt0gimode0; /* offset 0x104 */ 115 unsigned int dt0fwsratio0; /* offset 0x108 */ 116 unsigned int resv11[4]; 117 unsigned int dt0dqoffset; /* offset 0x11C */ 118 unsigned int dt0wrsratio0; /* offset 0x120 */ 119 unsigned int resv12[4]; 120 unsigned int dt0rdelays0; /* offset 0x134 */ 121 unsigned int dt0dldiff0; /* offset 0x138 */ 122}; 123 124/** 125 * Encapsulates DDR CMD control registers. 126 */ 127struct cmd_control { 128 unsigned long cmd0csratio; 129 unsigned long cmd0csforce; 130 unsigned long cmd0csdelay; 131 unsigned long cmd0dldiff; 132 unsigned long cmd0iclkout; 133 unsigned long cmd1csratio; 134 unsigned long cmd1csforce; 135 unsigned long cmd1csdelay; 136 unsigned long cmd1dldiff; 137 unsigned long cmd1iclkout; 138 unsigned long cmd2csratio; 139 unsigned long cmd2csforce; 140 unsigned long cmd2csdelay; 141 unsigned long cmd2dldiff; 142 unsigned long cmd2iclkout; 143}; 144 145/** 146 * Encapsulates DDR DATA registers. 147 */ 148struct ddr_data { 149 unsigned long datardsratio0; 150 unsigned long datawdsratio0; 151 unsigned long datawiratio0; 152 unsigned long datagiratio0; 153 unsigned long datafwsratio0; 154 unsigned long datawrsratio0; 155 unsigned long datauserank0delay; 156 unsigned long datadldiff0; 157}; 158 159/** 160 * Configure DDR CMD control registers 161 */ 162void config_cmd_ctrl(const struct cmd_control *cmd); 163 164/** 165 * Configure DDR DATA registers 166 */ 167void config_ddr_data(int data_macrono, const struct ddr_data *data); 168 169/** 170 * This structure represents the DDR io control on AM33XX devices. 171 */ 172struct ddr_cmdtctrl { 173 unsigned int resv1[1]; 174 unsigned int cm0ioctl; 175 unsigned int cm1ioctl; 176 unsigned int cm2ioctl; 177 unsigned int resv2[12]; 178 unsigned int dt0ioctl; 179 unsigned int dt1ioctl; 180}; 181 182/** 183 * Configure DDR io control registers 184 */ 185void config_io_ctrl(unsigned long val); 186 187struct ddr_ctrl { 188 unsigned int ddrioctrl; 189 unsigned int resv1[325]; 190 unsigned int ddrckectrl; 191}; 192 193void config_ddr(unsigned int pll, unsigned int ioctrl, 194 const struct ddr_data *data, const struct cmd_control *ctrl, 195 const struct emif_regs *regs); 196 197#endif /* _DDR_DEFS_H */ 198