1/* 2 * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com> 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 17 * MA 02110-1301, USA. 18 */ 19 20#ifndef _LPC32XX_EMC_H 21#define _LPC32XX_EMC_H 22 23#include <asm/types.h> 24 25/* EMC Registers */ 26struct emc_regs { 27 u32 ctrl; /* Controls operation of the EMC */ 28 u32 status; /* Provides EMC status information */ 29 u32 config; /* Configures operation of the EMC */ 30 u32 reserved0[5]; 31 u32 control; /* Controls dyn memory operation */ 32 u32 refresh; /* Configures dyn memory refresh operation */ 33 u32 read_config; /* Configures the dyn memory read strategy */ 34 u32 reserved1; 35 u32 t_rp; /* Precharge command period */ 36 u32 t_ras; /* Active to precharge command period */ 37 u32 t_srex; /* Self-refresh exit time */ 38 u32 reserved2[2]; 39 u32 t_wr; /* Write recovery time */ 40 u32 t_rc; /* Active to active command period */ 41 u32 t_rfc; /* Auto-refresh period */ 42 u32 t_xsr; /* Exit self-refresh to active command time */ 43 u32 t_rrd; /* Active bank A to active bank B latency */ 44 u32 t_mrd; /* Load mode register to active command time */ 45 u32 t_cdlr; /* Last data in to read command time */ 46 u32 reserved3[8]; 47 u32 extended_wait; /* time for static memory rd/wr transfers */ 48 u32 reserved4[31]; 49 u32 config0; /* Configuration information for the SDRAM */ 50 u32 rascas0; /* RAS and CAS latencies for the SDRAM */ 51 u32 reserved5[6]; 52 u32 config1; /* Configuration information for the SDRAM */ 53 u32 rascas1; /* RAS and CAS latencies for the SDRAM */ 54 u32 reserved6[54]; 55 struct emc_stat_t { 56 u32 config; /* Static memory configuration */ 57 u32 waitwen; /* Delay from chip select to write enable */ 58 u32 waitoen; /* Delay to output enable */ 59 u32 waitrd; /* Delay to a read access */ 60 u32 waitpage; /* Delay for async page mode read */ 61 u32 waitwr; /* Delay to a write access */ 62 u32 waitturn; /* Number of bus turnaround cycles */ 63 u32 reserved; 64 } stat[4]; 65 u32 reserved7[96]; 66 struct emc_ahb_t { 67 u32 control; /* Control register for AHB */ 68 u32 status; /* Status register for AHB */ 69 u32 timeout; /* Timeout register for AHB */ 70 u32 reserved[5]; 71 } ahb[5]; 72}; 73 74/* Static Memory Configuration Register bits */ 75#define EMC_STAT_CONFIG_WP (1 << 20) 76#define EMC_STAT_CONFIG_EW (1 << 8) 77#define EMC_STAT_CONFIG_PB (1 << 7) 78#define EMC_STAT_CONFIG_PC (1 << 6) 79#define EMC_STAT_CONFIG_PM (1 << 3) 80#define EMC_STAT_CONFIG_32BIT (2 << 0) 81#define EMC_STAT_CONFIG_16BIT (1 << 0) 82#define EMC_STAT_CONFIG_8BIT (0 << 0) 83 84/* Static Memory Delay Registers */ 85#define EMC_STAT_WAITWEN(n) (((n) - 1) & 0x0F) 86#define EMC_STAT_WAITOEN(n) (((n) - 1) & 0x0F) 87#define EMC_STAT_WAITRD(n) (((n) - 1) & 0x1F) 88#define EMC_STAT_WAITPAGE(n) (((n) - 1) & 0x1F) 89#define EMC_STAT_WAITWR(n) (((n) - 2) & 0x1F) 90#define EMC_STAT_WAITTURN(n) (((n) - 1) & 0x0F) 91 92#endif /* _LPC32XX_EMC_H */ 93