1/* 2 * ColdFire Internal Memory Map and Defines 3 * 4 * Copyright 2004-2012 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26#ifndef __IMMAP_H 27#define __IMMAP_H 28 29#if defined(CONFIG_MCF520x) 30#include <asm/immap_520x.h> 31#include <asm/m520x.h> 32 33#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) 34#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000)) 35 36/* Timer */ 37#ifdef CONFIG_MCFTMR 38#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) 39#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) 40#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) 41#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1) 42#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) 43#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 44#define CONFIG_SYS_TMRINTR_PRI (6) 45#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 46#endif 47 48#ifdef CONFIG_MCFPIT 49#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0) 50#define CONFIG_SYS_PIT_BASE (MMAP_PIT1) 51#define CONFIG_SYS_PIT_PRESCALE (6) 52#endif 53 54#define CONFIG_SYS_INTR_BASE (MMAP_INTC0) 55#define CONFIG_SYS_NUM_IRQS (128) 56#endif /* CONFIG_M520x */ 57 58#ifdef CONFIG_M52277 59#include <asm/immap_5227x.h> 60#include <asm/m5227x.h> 61 62#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000)) 63 64#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC) 65 66#ifdef CONFIG_LCD 67#define CONFIG_SYS_LCD_BASE (MMAP_LCD) 68#endif 69 70/* Timer */ 71#ifdef CONFIG_MCFTMR 72#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) 73#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) 74#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) 75#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1) 76#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) 77#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 78#define CONFIG_SYS_TMRINTR_PRI (6) 79#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 80#endif 81 82#ifdef CONFIG_MCFPIT 83#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0) 84#define CONFIG_SYS_PIT_BASE (MMAP_PIT1) 85#define CONFIG_SYS_PIT_PRESCALE (6) 86#endif 87 88#define CONFIG_SYS_INTR_BASE (MMAP_INTC0) 89#define CONFIG_SYS_NUM_IRQS (128) 90#endif /* CONFIG_M52277 */ 91 92#ifdef CONFIG_M5235 93#include <asm/immap_5235.h> 94#include <asm/m5235.h> 95 96#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) 97#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) 98 99/* Timer */ 100#ifdef CONFIG_MCFTMR 101#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) 102#define CONFIG_SYS_TMR_BASE (MMAP_DTMR3) 103#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0) 104#define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3) 105#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22) 106#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 107#define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */ 108#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 109#endif 110 111#ifdef CONFIG_MCFPIT 112#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0) 113#define CONFIG_SYS_PIT_BASE (MMAP_PIT1) 114#define CONFIG_SYS_PIT_PRESCALE (6) 115#endif 116 117#define CONFIG_SYS_INTR_BASE (MMAP_INTC0) 118#define CONFIG_SYS_NUM_IRQS (128) 119#endif /* CONFIG_M5235 */ 120 121#ifdef CONFIG_M5249 122#include <asm/immap_5249.h> 123#include <asm/m5249.h> 124 125#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) 126 127#define CONFIG_SYS_INTR_BASE (MMAP_INTC) 128#define CONFIG_SYS_NUM_IRQS (64) 129 130/* Timer */ 131#ifdef CONFIG_MCFTMR 132#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) 133#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) 134#define CONFIG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR)) 135#define CONFIG_SYS_TMRINTR_NO (31) 136#define CONFIG_SYS_TMRINTR_MASK (0x00000400) 137#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 138#define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3) 139#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8) 140#endif 141#endif /* CONFIG_M5249 */ 142 143#ifdef CONFIG_M5253 144#include <asm/immap_5253.h> 145#include <asm/m5249.h> 146#include <asm/m5253.h> 147 148#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) 149 150#define CONFIG_SYS_INTR_BASE (MMAP_INTC) 151#define CONFIG_SYS_NUM_IRQS (64) 152 153/* Timer */ 154#ifdef CONFIG_MCFTMR 155#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) 156#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) 157#define CONFIG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR)) 158#define CONFIG_SYS_TMRINTR_NO (27) 159#define CONFIG_SYS_TMRINTR_MASK (0x00000400) 160#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 161#define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3) 162#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8) 163#endif 164#endif /* CONFIG_M5253 */ 165 166#ifdef CONFIG_M5271 167#include <asm/immap_5271.h> 168#include <asm/m5271.h> 169 170#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) 171#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) 172 173/* Timer */ 174#ifdef CONFIG_MCFTMR 175#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) 176#define CONFIG_SYS_TMR_BASE (MMAP_DTMR3) 177#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0) 178#define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3) 179#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22) 180#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 181#define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Interrupt level 3, priority 6 */ 182#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 183#endif 184 185#define CONFIG_SYS_INTR_BASE (MMAP_INTC0) 186#define CONFIG_SYS_NUM_IRQS (128) 187#endif /* CONFIG_M5271 */ 188 189#ifdef CONFIG_M5272 190#include <asm/immap_5272.h> 191#include <asm/m5272.h> 192 193#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) 194#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) 195 196#define CONFIG_SYS_INTR_BASE (MMAP_INTC) 197#define CONFIG_SYS_NUM_IRQS (64) 198 199/* Timer */ 200#ifdef CONFIG_MCFTMR 201#define CONFIG_SYS_UDELAY_BASE (MMAP_TMR0) 202#define CONFIG_SYS_TMR_BASE (MMAP_TMR3) 203#define CONFIG_SYS_TMRPND_REG (((volatile intctrl_t *)(CONFIG_SYS_INTR_BASE))->int_isr) 204#define CONFIG_SYS_TMRINTR_NO (INT_TMR3) 205#define CONFIG_SYS_TMRINTR_MASK (INT_ISR_INT24) 206#define CONFIG_SYS_TMRINTR_PEND (0) 207#define CONFIG_SYS_TMRINTR_PRI (INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5)) 208#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 209#endif 210#endif /* CONFIG_M5272 */ 211 212#ifdef CONFIG_M5275 213#include <asm/immap_5275.h> 214#include <asm/m5275.h> 215 216#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) 217#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) 218#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) 219 220#define CONFIG_SYS_INTR_BASE (MMAP_INTC0) 221#define CONFIG_SYS_NUM_IRQS (192) 222 223/* Timer */ 224#ifdef CONFIG_MCFTMR 225#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) 226#define CONFIG_SYS_TMR_BASE (MMAP_DTMR3) 227#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0) 228#define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3) 229#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22) 230#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 231#define CONFIG_SYS_TMRINTR_PRI (0x1E) 232#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 233#endif 234#endif /* CONFIG_M5275 */ 235 236#ifdef CONFIG_M5282 237#include <asm/immap_5282.h> 238#include <asm/m5282.h> 239 240#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) 241#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) 242 243#define CONFIG_SYS_INTR_BASE (MMAP_INTC0) 244#define CONFIG_SYS_NUM_IRQS (128) 245 246/* Timer */ 247#ifdef CONFIG_MCFTMR 248#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) 249#define CONFIG_SYS_TMR_BASE (MMAP_DTMR3) 250#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0) 251#define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3) 252#define CONFIG_SYS_TMRINTR_MASK (1 << INT0_LO_DTMR3) 253#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 254#define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */ 255#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 256#endif 257#endif /* CONFIG_M5282 */ 258 259#if defined(CONFIG_MCF5301x) 260#include <asm/immap_5301x.h> 261#include <asm/m5301x.h> 262 263#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) 264#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) 265#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000)) 266 267#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC) 268 269/* Timer */ 270#ifdef CONFIG_MCFTMR 271#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) 272#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) 273#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) 274#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1) 275#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) 276#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 277#define CONFIG_SYS_TMRINTR_PRI (6) 278#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 279#endif 280 281#ifdef CONFIG_MCFPIT 282#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0) 283#define CONFIG_SYS_PIT_BASE (MMAP_PIT1) 284#define CONFIG_SYS_PIT_PRESCALE (6) 285#endif 286 287#define CONFIG_SYS_INTR_BASE (MMAP_INTC0) 288#define CONFIG_SYS_NUM_IRQS (128) 289#endif /* CONFIG_M5301x */ 290 291#if defined(CONFIG_M5329) || defined(CONFIG_M5373) 292#include <asm/immap_5329.h> 293#include <asm/m5329.h> 294 295#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) 296#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000)) 297#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC) 298 299/* Timer */ 300#ifdef CONFIG_MCFTMR 301#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) 302#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) 303#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) 304#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1) 305#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) 306#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 307#define CONFIG_SYS_TMRINTR_PRI (6) 308#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 309#endif 310 311#ifdef CONFIG_MCFPIT 312#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0) 313#define CONFIG_SYS_PIT_BASE (MMAP_PIT1) 314#define CONFIG_SYS_PIT_PRESCALE (6) 315#endif 316 317#define CONFIG_SYS_INTR_BASE (MMAP_INTC0) 318#define CONFIG_SYS_NUM_IRQS (128) 319#endif /* CONFIG_M5329 && CONFIG_M5373 */ 320 321#if defined(CONFIG_M54418) 322#include <asm/immap_5441x.h> 323#include <asm/m5441x.h> 324 325#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) 326#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) 327 328#if (CONFIG_SYS_UART_PORT < 4) 329#define CONFIG_SYS_UART_BASE (MMAP_UART0 + \ 330 (CONFIG_SYS_UART_PORT * 0x4000)) 331#else 332#define CONFIG_SYS_UART_BASE (MMAP_UART4 + \ 333 ((CONFIG_SYS_UART_PORT - 4) * 0x4000)) 334#endif 335 336#define MMAP_DSPI MMAP_DSPI0 337#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC) 338 339/* Timer */ 340#ifdef CONFIG_MCFTMR 341#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) 342#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) 343#define CONFIG_SYS_TMRPND_REG (((int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) 344#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1) 345#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) 346#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 347#define CONFIG_SYS_TMRINTR_PRI (6) 348#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 349#endif 350 351#ifdef CONFIG_MCFPIT 352#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0) 353#define CONFIG_SYS_PIT_BASE (MMAP_PIT1) 354#define CONFIG_SYS_PIT_PRESCALE (6) 355#endif 356 357#define CONFIG_SYS_INTR_BASE (MMAP_INTC0) 358#define CONFIG_SYS_NUM_IRQS (128) 359 360#endif /* CONFIG_M54418 */ 361 362#if defined(CONFIG_M54451) || defined(CONFIG_M54455) 363#include <asm/immap_5445x.h> 364#include <asm/m5445x.h> 365 366#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) 367#if defined(CONFIG_M54455EVB) 368#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) 369#endif 370 371#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000)) 372 373#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC) 374 375/* Timer */ 376#ifdef CONFIG_MCFTMR 377#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) 378#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) 379#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) 380#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1) 381#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) 382#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 383#define CONFIG_SYS_TMRINTR_PRI (6) 384#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 385#endif 386 387#ifdef CONFIG_MCFPIT 388#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0) 389#define CONFIG_SYS_PIT_BASE (MMAP_PIT1) 390#define CONFIG_SYS_PIT_PRESCALE (6) 391#endif 392 393#define CONFIG_SYS_INTR_BASE (MMAP_INTC0) 394#define CONFIG_SYS_NUM_IRQS (128) 395 396#ifdef CONFIG_PCI 397#define CONFIG_SYS_PCI_BAR0 (CONFIG_SYS_MBAR) 398#define CONFIG_SYS_PCI_BAR5 (CONFIG_SYS_SDRAM_BASE) 399#define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR) 400#define CONFIG_SYS_PCI_TBATR5 (CONFIG_SYS_SDRAM_BASE) 401#endif 402#endif /* CONFIG_M54451 || CONFIG_M54455 */ 403 404#ifdef CONFIG_M547x 405#include <asm/immap_547x_8x.h> 406#include <asm/m547x_8x.h> 407 408#ifdef CONFIG_FSLDMAFEC 409#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) 410#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) 411 412#define FEC0_RX_TASK 0 413#define FEC0_TX_TASK 1 414#define FEC0_RX_PRIORITY 6 415#define FEC0_TX_PRIORITY 7 416#define FEC0_RX_INIT 16 417#define FEC0_TX_INIT 17 418#define FEC1_RX_TASK 2 419#define FEC1_TX_TASK 3 420#define FEC1_RX_PRIORITY 6 421#define FEC1_TX_PRIORITY 7 422#define FEC1_RX_INIT 30 423#define FEC1_TX_INIT 31 424#endif 425 426#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x100)) 427 428#ifdef CONFIG_SLTTMR 429#define CONFIG_SYS_UDELAY_BASE (MMAP_SLT1) 430#define CONFIG_SYS_TMR_BASE (MMAP_SLT0) 431#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) 432#define CONFIG_SYS_TMRINTR_NO (INT0_HI_SLT0) 433#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT54) 434#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 435#define CONFIG_SYS_TMRINTR_PRI (0x1E) 436#define CONFIG_SYS_TIMER_PRESCALER (gd->bus_clk / 1000000) 437#endif 438 439#define CONFIG_SYS_INTR_BASE (MMAP_INTC0) 440#define CONFIG_SYS_NUM_IRQS (128) 441 442#ifdef CONFIG_PCI 443#define CONFIG_SYS_PCI_BAR0 (0x40000000) 444#define CONFIG_SYS_PCI_BAR1 (CONFIG_SYS_SDRAM_BASE) 445#define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR) 446#define CONFIG_SYS_PCI_TBATR1 (CONFIG_SYS_SDRAM_BASE) 447#endif 448#endif /* CONFIG_M547x */ 449 450#ifdef CONFIG_M548x 451#include <asm/immap_547x_8x.h> 452#include <asm/m547x_8x.h> 453 454#ifdef CONFIG_FSLDMAFEC 455#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) 456#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) 457 458#define FEC0_RX_TASK 0 459#define FEC0_TX_TASK 1 460#define FEC0_RX_PRIORITY 6 461#define FEC0_TX_PRIORITY 7 462#define FEC0_RX_INIT 16 463#define FEC0_TX_INIT 17 464#define FEC1_RX_TASK 2 465#define FEC1_TX_TASK 3 466#define FEC1_RX_PRIORITY 6 467#define FEC1_TX_PRIORITY 7 468#define FEC1_RX_INIT 30 469#define FEC1_TX_INIT 31 470#endif 471 472#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x100)) 473 474/* Timer */ 475#ifdef CONFIG_SLTTMR 476#define CONFIG_SYS_UDELAY_BASE (MMAP_SLT1) 477#define CONFIG_SYS_TMR_BASE (MMAP_SLT0) 478#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) 479#define CONFIG_SYS_TMRINTR_NO (INT0_HI_SLT0) 480#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT54) 481#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 482#define CONFIG_SYS_TMRINTR_PRI (0x1E) 483#define CONFIG_SYS_TIMER_PRESCALER (gd->bus_clk / 1000000) 484#endif 485 486#define CONFIG_SYS_INTR_BASE (MMAP_INTC0) 487#define CONFIG_SYS_NUM_IRQS (128) 488 489#ifdef CONFIG_PCI 490#define CONFIG_SYS_PCI_BAR0 (CONFIG_SYS_MBAR) 491#define CONFIG_SYS_PCI_BAR1 (CONFIG_SYS_SDRAM_BASE) 492#define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR) 493#define CONFIG_SYS_PCI_TBATR1 (CONFIG_SYS_SDRAM_BASE) 494#endif 495#endif /* CONFIG_M548x */ 496 497#endif /* __IMMAP_H */ 498