1/* 2 * (C) Copyright 2010 3 * Stefan Roese, DENX Software Engineering, sr@denx.de. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License as 7 * published by the Free Software Foundation; either version 2 of 8 * the License, or (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 18 * MA 02111-1307 USA 19 */ 20 21#ifndef _PPC440EPX_GRX_H_ 22#define _PPC440EPX_GRX_H_ 23 24#define CONFIG_SDRAM_PPC4xx_DENALI_DDR2 /* Denali DDR(2) controller */ 25 26#define CONFIG_NAND_NDFC 27 28/* 29 * Some SoC specific registers (not common for all 440 SoC's) 30 */ 31 32/* Memory mapped registers */ 33#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* Internal Peripherals */ 34 35#define SPI0_MODE (CONFIG_SYS_PERIPHERAL_BASE + 0x0090) 36 37#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300) 38#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0400) 39#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_PERIPHERAL_BASE + 0x0500) 40#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_PERIPHERAL_BASE + 0x0600) 41 42#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0b00) 43#define GPIO1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0c00) 44 45/* DCR */ 46#define CPM0_ER 0x00b0 47#define CPM1_ER 0x00f0 48#define PLB3A0_ACR 0x0077 49#define PLB4A0_ACR 0x0081 50#define PLB4A1_ACR 0x0089 51#define OPB2PLB40_BCTRL 0x0350 52#define P4P3BO0_CFG 0x0026 53 54/* SDR */ 55#define SDR0_DDRCFG 0x00e0 56#define SDR0_PCI0 0x0300 57#define SDR0_SDSTP2 0x4001 58#define SDR0_SDSTP3 0x4003 59#define SDR0_EMAC0RXST 0x4301 60#define SDR0_EMAC0TXST 0x4302 61#define SDR0_CRYP0 0x4500 62 63#define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 21) 64#define SDR0_SDSTP1_PAME_MASK (0x80000000 >> 27) 65 66/* Pin Function Control Register 1 */ 67#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */ 68#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */ 69#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */ 70#define SDR0_PFC1_SELECT_MASK 0x01C00000 /* Ethernet Pin Select 71 EMAC 0 */ 72#define SDR0_PFC1_SELECT_CONFIG_1_1 0x00C00000 /* 1xMII using RGMII 73 bridge */ 74#define SDR0_PFC1_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII 75 bridge */ 76#define SDR0_PFC1_SELECT_CONFIG_2 0x00C00000 /* 1xGMII using RGMII 77 bridge */ 78#define SDR0_PFC1_SELECT_CONFIG_3 0x01000000 /* 1xTBI using RGMII 79 bridge */ 80#define SDR0_PFC1_SELECT_CONFIG_4 0x01400000 /* 2xRGMII using RGMII 81 bridge */ 82#define SDR0_PFC1_SELECT_CONFIG_5 0x01800000 /* 2xRTBI using RGMII 83 bridge */ 84#define SDR0_PFC1_SELECT_CONFIG_6 0x00800000 /* 2xSMII using ZMII 85 bridge */ 86#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */ 87#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */ 88#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */ 89#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */ 90#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */ 91#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */ 92#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */ 93#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */ 94#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */ 95#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold 96 Req Selection */ 97#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */ 98#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */ 99#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) 100 Selection */ 101#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */ 102#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */ 103#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) 104 Selection */ 105#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. 106 Selected */ 107#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */ 108#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject 109 Selection */ 110#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject 111 Disable */ 112#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject 113 Enable */ 114#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor Enable 115 Selection */ 116#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor 117 Enable */ 118#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor 119 Enable */ 120#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation 121 Gated In */ 122 123#define SDR0_PFC2_SELECT_MASK 0xe0000000 /* Ethernet Pin select EMAC1 */ 124#define SDR0_PFC2_SELECT_CONFIG_1_1 0x60000000 /* 1xMII using RGMII bridge */ 125#define SDR0_PFC2_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII bridge */ 126#define SDR0_PFC2_SELECT_CONFIG_2 0x60000000 /* 1xGMII using RGMII bridge */ 127#define SDR0_PFC2_SELECT_CONFIG_3 0x80000000 /* 1xTBI using RGMII bridge */ 128#define SDR0_PFC2_SELECT_CONFIG_4 0xa0000000 /* 2xRGMII using RGMII bridge */ 129#define SDR0_PFC2_SELECT_CONFIG_5 0xc0000000 /* 2xRTBI using RGMII bridge */ 130#define SDR0_PFC2_SELECT_CONFIG_6 0x40000000 /* 2xSMII using ZMII bridge */ 131 132#define SDR0_USB2D0CR 0x0320 133#define SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK 0x00000004 /* USB 2.0 Device/EBC 134 Master Selection */ 135#define SDR0_USB2D0CR_USB2DEV_SELECTION 0x00000004 /* USB 2.0 Device Selection*/ 136#define SDR0_USB2D0CR_EBC_SELECTION 0x00000000 /* EBC Selection */ 137 138#define SDR0_USB2D0CR_USB_DEV_INT_SEL_MASK 0x00000002 /* USB Device Interface 139 Selection */ 140#define SDR0_USB2D0CR_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */ 141#define SDR0_USB2D0CR_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */ 142 143#define SDR0_USB2D0CR_LEEN_MASK 0x00000001 /* Little Endian selection */ 144#define SDR0_USB2D0CR_LEEN_DISABLE 0x00000000 /* Little Endian Disable */ 145#define SDR0_USB2D0CR_LEEN_ENABLE 0x00000001 /* Little Endian Enable */ 146 147/* USB2 Host Control Register */ 148#define SDR0_USB2H0CR 0x0340 149#define SDR0_USB2H0CR_WDINT_MASK 0x00000001 /* Host UTMI Word Interface*/ 150#define SDR0_USB2H0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit/60MHz */ 151#define SDR0_USB2H0CR_WDINT_16BIT_30MHZ 0x00000001 /* 16-bit/30MHz */ 152#define SDR0_USB2H0CR_EFLADJ_MASK 0x0000007e /* EHCI Frame Length 153 Adjustment */ 154/* USB2PHY0 Control Register */ 155#define SDR0_USB2PHY0CR 0x4103 156#define SDR0_USB2PHY0CR_UTMICN_MASK 0x00100000 157 158 /* PHY UTMI interface connection */ 159#define SDR0_USB2PHY0CR_UTMICN_DEV 0x00000000 /* Device support */ 160#define SDR0_USB2PHY0CR_UTMICN_HOST 0x00100000 /* Host support */ 161 162#define SDR0_USB2PHY0CR_DWNSTR_MASK 0x00400000 /* Select downstream port mode */ 163#define SDR0_USB2PHY0CR_DWNSTR_DEV 0x00000000 /* Device */ 164#define SDR0_USB2PHY0CR_DWNSTR_HOST 0x00400000 /* Host */ 165 166/* VBus detect (Device mode only) */ 167#define SDR0_USB2PHY0CR_DVBUS_MASK 0x00800000 168/* Pull-up resistance on D+ is disabled */ 169#define SDR0_USB2PHY0CR_DVBUS_PURDIS 0x00000000 170/* Pull-up resistance on D+ is enabled */ 171#define SDR0_USB2PHY0CR_DVBUS_PUREN 0x00800000 172 173/* PHY UTMI data width and clock select */ 174#define SDR0_USB2PHY0CR_WDINT_MASK 0x01000000 175#define SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit data/60MHz */ 176#define SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ 0x01000000 /* 16-bit data/30MHz */ 177 178#define SDR0_USB2PHY0CR_LOOPEN_MASK 0x02000000 /* Loop back test enable */ 179#define SDR0_USB2PHY0CR_LOOP_ENABLE 0x00000000 /* Loop back disabled */ 180/* Loop back enabled (only test purposes) */ 181#define SDR0_USB2PHY0CR_LOOP_DISABLE 0x02000000 182 183/* Force XO block on during a suspend */ 184#define SDR0_USB2PHY0CR_XOON_MASK 0x04000000 185#define SDR0_USB2PHY0CR_XO_ON 0x00000000 /* PHY XO block is powered-on */ 186/* PHY XO block is powered-off when all ports are suspended */ 187#define SDR0_USB2PHY0CR_XO_OFF 0x04000000 188 189#define SDR0_USB2PHY0CR_PWRSAV_MASK 0x08000000 /* Select PHY power-save mode */ 190#define SDR0_USB2PHY0CR_PWRSAV_OFF 0x00000000 /* Non-power-save mode */ 191#define SDR0_USB2PHY0CR_PWRSAV_ON 0x08000000 /* Power-save mode. Valid only 192 for full-speed operation */ 193 194#define SDR0_USB2PHY0CR_XOREF_MASK 0x10000000 /* Select reference clock 195 source */ 196#define SDR0_USB2PHY0CR_XOREF_INTERNAL 0x00000000 /* PHY PLL uses chip internal 197 48M clock as a reference */ 198#define SDR0_USB2PHY0CR_XOREF_XO 0x10000000 /* PHY PLL uses internal XO 199 block output as a reference */ 200 201#define SDR0_USB2PHY0CR_XOCLK_MASK 0x20000000 /* Select clock for XO 202 block*/ 203#define SDR0_USB2PHY0CR_XOCLK_EXTERNAL 0x00000000 /* PHY macro used an external 204 clock */ 205#define SDR0_USB2PHY0CR_XOCLK_CRYSTAL 0x20000000 /* PHY macro uses the clock 206 from a crystal */ 207 208#define SDR0_USB2PHY0CR_CLKSEL_MASK 0xc0000000 /* Select ref clk freq */ 209#define SDR0_USB2PHY0CR_CLKSEL_12MHZ 0x00000000 /* Select ref clk freq 210 = 12 MHz */ 211#define SDR0_USB2PHY0CR_CLKSEL_48MHZ 0x40000000 /* Select ref clk freq 212 = 48 MHz */ 213#define SDR0_USB2PHY0CR_CLKSEL_24MHZ 0x80000000 /* Select ref clk freq 214 = 24 MHz */ 215 216/* USB2.0 Device */ 217/* 218 * todo: check if this can be completely removed, only used in 219 * cpu/ppc4xx/usbdev.c. And offsets are completely wrong. This could 220 * never have actually worked. Best probably is to remove this 221 * usbdev.c file completely (and these defines). 222 */ 223#define USB2D0_BASE CONFIG_SYS_USB2D0_BASE 224 225#define USB2D0_INTRIN (USB2D0_BASE + 0x00000000) 226 227#define USB2D0_INTRIN (USB2D0_BASE + 0x00000000) /* Interrupt register for 228 Endpoint 0 plus IN Endpoints 1 to 3 */ 229#define USB2D0_POWER (USB2D0_BASE + 0x00000000) /* Power management 230 register */ 231#define USB2D0_FADDR (USB2D0_BASE + 0x00000000) /* Function address 232 register */ 233#define USB2D0_INTRINE (USB2D0_BASE + 0x00000000) /* Interrupt enable 234 register for USB2D0_INTRIN */ 235#define USB2D0_INTROUT (USB2D0_BASE + 0x00000000) /* Interrupt register for 236 OUT Endpoints 1 to 3 */ 237#define USB2D0_INTRUSBE (USB2D0_BASE + 0x00000000) /* Interrupt enable 238 register for USB2D0_INTRUSB */ 239#define USB2D0_INTRUSB (USB2D0_BASE + 0x00000000) /* Interrupt register for 240 common USB interrupts */ 241#define USB2D0_INTROUTE (USB2D0_BASE + 0x00000000) /* Interrupt enable 242 register for IntrOut */ 243#define USB2D0_TSTMODE (USB2D0_BASE + 0x00000000) /* Enables the USB 2.0 244 test modes */ 245#define USB2D0_INDEX (USB2D0_BASE + 0x00000000) /* Index register for 246 selecting the Endpoint status/control registers */ 247#define USB2D0_FRAME (USB2D0_BASE + 0x00000000) /* Frame number */ 248#define USB2D0_INCSR0 (USB2D0_BASE + 0x00000000) /* Control Status 249 register for Endpoint 0. (Index register set to select Endpoint 0) */ 250#define USB2D0_INCSR (USB2D0_BASE + 0x00000000) /* Control Status 251 register for IN Endpoint. (Index register set to select Endpoints 13) */ 252#define USB2D0_INMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet 253 size for IN Endpoint. (Index register set to select Endpoints 13) */ 254#define USB2D0_OUTCSR (USB2D0_BASE + 0x00000000) /* Control Status 255 register for OUT Endpoint. (Index register set to select Endpoints 13) */ 256#define USB2D0_OUTMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet 257 size for OUT Endpoint. (Index register set to select Endpoints 13) */ 258#define USB2D0_OUTCOUNT0 (USB2D0_BASE + 0x00000000) /* Number of received 259 bytes in Endpoint 0 FIFO. (Index register set to select Endpoint 0) */ 260#define USB2D0_OUTCOUNT (USB2D0_BASE + 0x00000000) /* Number of bytes in 261 OUT Endpoint FIFO. (Index register set to select Endpoints 13) */ 262 263/* Miscealleneaous Function Reg. */ 264#define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */ 265#define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000 266#define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */ 267#define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000 268#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */ 269#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */ 270#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */ 271#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */ 272#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */ 273#define SDR0_MFR_ZM_ENCODE(n) ((((u32)(n)) & 0x3) << 24) 274#define SDR0_MFR_ZM_DECODE(n) ((((u32)(n)) << 24) & 0x3) 275#define SDR0_MFR_PKT_REJ_MASK 0x00300000 /* Pkt Rej. Enable Mask */ 276#define SDR0_MFR_PKT_REJ_EN 0x00300000 /* Pkt Rej. Ena. on both EMAC3 0-1 */ 277#define SDR0_MFR_PKT_REJ_EN0 0x00200000 /* Pkt Rej. Enable on EMAC3(0) */ 278#define SDR0_MFR_PKT_REJ_EN1 0x00100000 /* Pkt Rej. Enable on EMAC3(1) */ 279#define SDR0_MFR_PKT_REJ_POL 0x00080000 /* Packet Reject Polarity */ 280 281/* CUST0 Customer Configuration Register0 */ 282#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */ 283#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */ 284#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */ 285#define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */ 286 287#define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */ 288#define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */ 289#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */ 290 291#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */ 292#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */ 293#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */ 294 295#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */ 296#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((u32)(n)) & 0xF) << 24) 297#define SDR0_CUST0_NDFC_BP_DECODE(n) ((((u32)(n)) >> 24) & 0xF) 298 299#define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */ 300#define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((u32)(n)) & 0x3) << 22) 301#define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((u32)(n)) >> 22) & 0x3) 302 303#define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */ 304#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */ 305#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */ 306 307#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */ 308#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */ 309#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */ 310 311#define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */ 312#define SDR0_CUST0_NDRSC_ENCODE(n) ((((u32)(n)) & 0xFFF) << 4) 313#define SDR0_CUST0_NDRSC_DECODE(n) ((((u32)(n)) >> 4) & 0xFFF) 314 315#define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */ 316#define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */ 317#define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /*All Chip Select Gating Enable*/ 318#define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */ 319#define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */ 320#define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */ 321#define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */ 322 323#define SDR0_SRST0_BGO 0x80000000 /* PLB to OPB bridge */ 324#define SDR0_SRST0_PLB4 0x40000000 /* PLB4 arbiter */ 325#define SDR0_SRST0_EBC 0x20000000 /* External bus controller */ 326#define SDR0_SRST0_OPB 0x10000000 /* OPB arbiter */ 327#define SDR0_SRST0_UART0 0x08000000 /* Universal asynchronous receiver/ 328 transmitter 0 */ 329#define SDR0_SRST0_UART1 0x04000000 /* Universal asynchronous receiver/ 330 transmitter 1 */ 331#define SDR0_SRST0_IIC0 0x02000000 /* Inter integrated circuit 0 */ 332#define SDR0_SRST0_USB2H 0x01000000 /* USB2.0 Host */ 333#define SDR0_SRST0_GPIO 0x00800000 /* General purpose I/O */ 334#define SDR0_SRST0_GPT 0x00400000 /* General purpose timer */ 335#define SDR0_SRST0_DMC 0x00200000 /* DDR SDRAM memory controller */ 336#define SDR0_SRST0_PCI 0x00100000 /* PCI */ 337#define SDR0_SRST0_EMAC0 0x00080000 /* Ethernet media access controller 0 */ 338#define SDR0_SRST0_EMAC1 0x00040000 /* Ethernet media access controller 1 */ 339#define SDR0_SRST0_CPM0 0x00020000 /* Clock and power management */ 340#define SDR0_SRST0_ZMII 0x00010000 /* ZMII bridge */ 341#define SDR0_SRST0_UIC0 0x00008000 /* Universal interrupt controller 0 */ 342#define SDR0_SRST0_UIC1 0x00004000 /* Universal interrupt controller 1 */ 343#define SDR0_SRST0_IIC1 0x00002000 /* Inter integrated circuit 1 */ 344#define SDR0_SRST0_SCP 0x00001000 /* Serial communications port */ 345#define SDR0_SRST0_BGI 0x00000800 /* OPB to PLB bridge */ 346#define SDR0_SRST0_DMA 0x00000400 /* Direct memory access controller */ 347#define SDR0_SRST0_DMAC 0x00000200 /* DMA channel */ 348#define SDR0_SRST0_MAL 0x00000100 /* Media access layer */ 349#define SDR0_SRST0_USB2D 0x00000080 /* USB2.0 device */ 350#define SDR0_SRST0_GPTR 0x00000040 /* General purpose timer */ 351#define SDR0_SRST0_P4P3 0x00000010 /* PLB4 to PLB3 bridge */ 352#define SDR0_SRST0_P3P4 0x00000008 /* PLB3 to PLB4 bridge */ 353#define SDR0_SRST0_PLB3 0x00000004 /* PLB3 arbiter */ 354#define SDR0_SRST0_UART2 0x00000002 /* Universal asynchronous receiver/ 355 transmitter 2 */ 356#define SDR0_SRST0_UART3 0x00000001 /* Universal asynchronous receiver/ 357 transmitter 3 */ 358 359#define SDR0_SRST1_NDFC 0x80000000 /* Nand flash controller */ 360#define SDR0_SRST1_OPBA1 0x40000000 /* OPB Arbiter attached to PLB4 */ 361#define SDR0_SRST1_P4OPB0 0x20000000 /* PLB4 to OPB Bridge0 */ 362#define SDR0_SRST1_PLB42OPB0 SDR0_SRST1_P4OPB0 363#define SDR0_SRST1_DMA4 0x10000000 /* DMA to PLB4 */ 364#define SDR0_SRST1_DMA4CH 0x08000000 /* DMA Channel to PLB4 */ 365#define SDR0_SRST1_OPBA2 0x04000000 /* OPB Arbiter attached to PLB4 366 USB 2.0 Host */ 367#define SDR0_SRST1_OPB2PLB40 0x02000000 /* OPB to PLB4 Bridge attached to 368 USB 2.0 Host */ 369#define SDR0_SRST1_PLB42OPB1 0x01000000 /* PLB4 to OPB Bridge attached to 370 USB 2.0 Host */ 371#define SDR0_SRST1_CPM1 0x00800000 /* Clock and Power management 1 */ 372#define SDR0_SRST1_UIC2 0x00400000 /* Universal Interrupt Controller 2*/ 373#define SDR0_SRST1_CRYP0 0x00200000 /* Security Engine */ 374#define SDR0_SRST1_USB20PHY 0x00100000 /* USB 2.0 Phy */ 375#define SDR0_SRST1_USB2HUTMI 0x00080000 /* USB 2.0 Host UTMI Interface */ 376#define SDR0_SRST1_USB2HPHY 0x00040000 /* USB 2.0 Host Phy Interface */ 377#define SDR0_SRST1_SRAM0 0x00020000 /* Internal SRAM Controller */ 378#define SDR0_SRST1_RGMII0 0x00010000 /* RGMII Bridge */ 379#define SDR0_SRST1_ETHPLL 0x00008000 /* Ethernet PLL */ 380#define SDR0_SRST1_FPU 0x00004000 /* Floating Point Unit */ 381#define SDR0_SRST1_KASU0 0x00002000 /* Kasumi Engine */ 382 383#define PLLSYS0_ENG_MASK 0x80000000 /* 0 = SysClk, 1 = PLL VCO */ 384#define PLLSYS0_SRC_MASK 0x40000000 /* 0 = PLL A, 1 = PLL B */ 385#define PLLSYS0_SEL_MASK 0x38000000 /* 0 = PLL, 1 = CPU, 5 = PerClk */ 386#define PLLSYS0_TUNE_MASK 0x07fe0000 /* PLL Tune bits */ 387#define PLLSYS0_FB_DIV_MASK 0x0001f000 /* Feedback divisor */ 388#define PLLSYS0_FWD_DIV_A_MASK 0x00000f00 /* Fwd Div A */ 389#define PLLSYS0_FWD_DIV_B_MASK 0x000000e0 /* Fwd Div B */ 390#define PLLSYS0_PRI_DIV_B_MASK 0x0000001c /* PLL Primary Divisor B */ 391#define PLLSYS0_OPB_DIV_MASK 0x00000003 /* OPB Divisor */ 392 393#define PLLC_ENG_MASK 0x20000000 /* PLL primary forward divisor source */ 394#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */ 395#define PLLD_FBDV_MASK 0x1f000000 /* PLL Feedback Divisor */ 396#define PLLD_FWDVA_MASK 0x000f0000 /* PLL Forward Divisor A */ 397#define PLLD_FWDVB_MASK 0x00000700 /* PLL Forward Divisor B */ 398#define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */ 399 400#define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */ 401#define PERDV_MASK 0x07000000 /* Peripheral Clock Divisor */ 402#define PRADV_MASK 0x07000000 /* Primary Divisor A */ 403#define PRBDV_MASK 0x07000000 /* Primary Divisor B */ 404#define SPCID_MASK 0x03000000 /* Sync PCI Divisor */ 405 406/* Strap 1 Register */ 407#define PLLSYS1_LF_DIV_MASK 0xfc000000 /* PLL Local Feedback Divisor */ 408#define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */ 409#define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */ 410#define PLLSYS1_RW_MASK 0x00300000 /* ROM width */ 411#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Address reset vector */ 412#define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */ 413#define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */ 414#define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */ 415#define PLLSYS1_PCWE_MASK 0x00008000 /* PCI local cpu wait enable */ 416#define PLLSYS1_PPIM_MASK 0x00007800 /* PCI inbound map */ 417#define PLLSYS1_PR64E_MASK 0x00000400 /* PCI init Req64 enable */ 418#define PLLSYS1_PXFS_MASK 0x00000300 /* PCI-X Freq Sel */ 419#define PLLSYS1_RSVD_MASK 0x00000080 /* RSVD */ 420#define PLLSYS1_PDM_MASK 0x00000040 /* PCI-X Driver Mode */ 421#define PLLSYS1_EPS_MASK 0x00000038 /* Ethernet Pin Select */ 422#define PLLSYS1_RMII_MASK 0x00000004 /* RMII Mode */ 423#define PLLSYS1_TRE_MASK 0x00000002 /* GPIO Trace Enable */ 424#define PLLSYS1_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */ 425 426#define CPR0_ICFG_RLI_MASK 0x80000000 427#define CPR0_ICFG_ICS_MASK 0x00000007 428#define CPR0_SPCID_SPCIDV0_MASK 0x03000000 429#define CPR0_SPCID_SPCIDV0_DIV1 0x01000000 430#define CPR0_SPCID_SPCIDV0_DIV2 0x02000000 431#define CPR0_SPCID_SPCIDV0_DIV3 0x03000000 432#define CPR0_SPCID_SPCIDV0_DIV4 0x00000000 433#define CPR0_PERD_PERDV0_MASK 0x07000000 434 435#define PCI_MMIO_LCR_BASE (CONFIG_SYS_PCI_BASE + 0x0f400000) /* Real => 436 0x0EF400000 */ 437 438/* PCI Master Local Configuration Registers */ 439#define PCIL0_PMM0LA (PCI_MMIO_LCR_BASE + 0x00) /* PMM0 Local Address */ 440#define PCIL0_PMM0MA (PCI_MMIO_LCR_BASE + 0x04) /* PMM0 Mask/Attribute */ 441#define PCIL0_PMM0PCILA (PCI_MMIO_LCR_BASE + 0x08) /* PMM0 PCI Low Address */ 442#define PCIL0_PMM0PCIHA (PCI_MMIO_LCR_BASE + 0x0C) /* PMM0 PCI High Address */ 443#define PCIL0_PMM1LA (PCI_MMIO_LCR_BASE + 0x10) /* PMM1 Local Address */ 444#define PCIL0_PMM1MA (PCI_MMIO_LCR_BASE + 0x14) /* PMM1 Mask/Attribute */ 445#define PCIL0_PMM1PCILA (PCI_MMIO_LCR_BASE + 0x18) /* PMM1 PCI Low Address */ 446#define PCIL0_PMM1PCIHA (PCI_MMIO_LCR_BASE + 0x1C) /* PMM1 PCI High Address */ 447#define PCIL0_PMM2LA (PCI_MMIO_LCR_BASE + 0x20) /* PMM2 Local Address */ 448#define PCIL0_PMM2MA (PCI_MMIO_LCR_BASE + 0x24) /* PMM2 Mask/Attribute */ 449#define PCIL0_PMM2PCILA (PCI_MMIO_LCR_BASE + 0x28) /* PMM2 PCI Low Address */ 450#define PCIL0_PMM2PCIHA (PCI_MMIO_LCR_BASE + 0x2C) /* PMM2 PCI High Address */ 451 452/* PCI Target Local Configuration Registers */ 453#define PCIL0_PTM1MS (PCI_MMIO_LCR_BASE + 0x30) /* PTM1 Memory Size/ 454 Attribute */ 455#define PCIL0_PTM1LA (PCI_MMIO_LCR_BASE + 0x34) /* PTM1 Local Addr. Reg */ 456#define PCIL0_PTM2MS (PCI_MMIO_LCR_BASE + 0x38) /* PTM2 Memory Size/ 457 Attribute */ 458#define PCIL0_PTM2LA (PCI_MMIO_LCR_BASE + 0x3C) /* PTM2 Local Addr. Reg */ 459 460/* 440EPx boot strap options */ 461#define BOOT_STRAP_OPTION_A 0x00000000 462#define BOOT_STRAP_OPTION_B 0x00000001 463#define BOOT_STRAP_OPTION_D 0x00000003 464#define BOOT_STRAP_OPTION_E 0x00000004 465 466#endif /* _PPC440EPX_GRX_H_ */ 467