1#ifndef __ASM_PPC_PROCESSOR_H
2#define __ASM_PPC_PROCESSOR_H
3
4
5
6
7
8#define current_text_addr() ({ __label__ _l; _l: &&_l;})
9
10#include <linux/config.h>
11
12#include <asm/ptrace.h>
13#include <asm/types.h>
14
15
16
17#ifdef CONFIG_PPC64BRIDGE
18#define MSR_SF (1<<63)
19#define MSR_ISF (1<<61)
20#endif
21#define MSR_UCLE (1<<26)
22#define MSR_VEC (1<<25)
23#define MSR_SPE (1<<25)
24#define MSR_POW (1<<18)
25#define MSR_WE (1<<18)
26#define MSR_TGPR (1<<17)
27#define MSR_CE (1<<17)
28#define MSR_ILE (1<<16)
29#define MSR_EE (1<<15)
30#define MSR_PR (1<<14)
31#define MSR_FP (1<<13)
32#define MSR_ME (1<<12)
33#define MSR_FE0 (1<<11)
34#define MSR_SE (1<<10)
35#define MSR_DWE (1<<10)
36#define MSR_UBLE (1<<10)
37#define MSR_BE (1<<9)
38#define MSR_DE (1<<9)
39#define MSR_FE1 (1<<8)
40#define MSR_IP (1<<6)
41#define MSR_IR (1<<5)
42#define MSR_IS (1<<5)
43#define MSR_DR (1<<4)
44#define MSR_DS (1<<4)
45#define MSR_PE (1<<3)
46#define MSR_PX (1<<2)
47#define MSR_PMM (1<<2)
48#define MSR_RI (1<<1)
49#define MSR_LE (1<<0)
50
51#ifdef CONFIG_APUS_FAST_EXCEPT
52#define MSR_ MSR_ME|MSR_IP|MSR_RI
53#else
54#define MSR_ MSR_ME|MSR_RI
55#endif
56#ifndef CONFIG_E500
57#define MSR_KERNEL MSR_|MSR_IR|MSR_DR
58#else
59#define MSR_KERNEL MSR_ME
60#endif
61
62
63
64#define FPSCR_FX 0x80000000
65#define FPSCR_FEX 0x40000000
66#define FPSCR_VX 0x20000000
67#define FPSCR_OX 0x10000000
68#define FPSCR_UX 0x08000000
69#define FPSCR_ZX 0x04000000
70#define FPSCR_XX 0x02000000
71#define FPSCR_VXSNAN 0x01000000
72#define FPSCR_VXISI 0x00800000
73#define FPSCR_VXIDI 0x00400000
74#define FPSCR_VXZDZ 0x00200000
75#define FPSCR_VXIMZ 0x00100000
76#define FPSCR_VXVC 0x00080000
77#define FPSCR_FR 0x00040000
78#define FPSCR_FI 0x00020000
79#define FPSCR_FPRF 0x0001f000
80#define FPSCR_FPCC 0x0000f000
81#define FPSCR_VXSOFT 0x00000400
82#define FPSCR_VXSQRT 0x00000200
83#define FPSCR_VXCVI 0x00000100
84#define FPSCR_VE 0x00000080
85#define FPSCR_OE 0x00000040
86#define FPSCR_UE 0x00000020
87#define FPSCR_ZE 0x00000010
88#define FPSCR_XE 0x00000008
89#define FPSCR_NI 0x00000004
90#define FPSCR_RN 0x00000003
91
92
93
94
95#ifdef CONFIG_440
96#define CONFIG_BOOKE
97#endif
98
99#define SPRN_CCR0 0x3B3
100#ifdef CONFIG_BOOKE
101#define SPRN_CCR1 0x378
102#endif
103#define SPRN_CDBCR 0x3D7
104#define SPRN_CTR 0x009
105#define SPRN_DABR 0x3F5
106#ifndef CONFIG_BOOKE
107#define SPRN_DAC1 0x3F6
108#define SPRN_DAC2 0x3F7
109#else
110#define SPRN_DAC1 0x13C
111#define SPRN_DAC2 0x13D
112#endif
113#define SPRN_DAR 0x013
114#define SPRN_DBAT0L 0x219
115#define SPRN_DBAT0U 0x218
116#define SPRN_DBAT1L 0x21B
117#define SPRN_DBAT1U 0x21A
118#define SPRN_DBAT2L 0x21D
119#define SPRN_DBAT2U 0x21C
120#define SPRN_DBAT3L 0x21F
121#define SPRN_DBAT3U 0x21E
122#define SPRN_DBAT4L 0x239
123#define SPRN_DBAT4U 0x238
124#define SPRN_DBAT5L 0x23B
125#define SPRN_DBAT5U 0x23A
126#define SPRN_DBAT6L 0x23D
127#define SPRN_DBAT6U 0x23C
128#define SPRN_DBAT7L 0x23F
129#define SPRN_DBAT7U 0x23E
130#define SPRN_DBCR 0x3F2
131#define DBCR_EDM 0x80000000
132#define DBCR_IDM 0x40000000
133#define DBCR_RST(x) (((x) & 0x3) << 28)
134#define DBCR_RST_NONE 0
135#define DBCR_RST_CORE 1
136#define DBCR_RST_CHIP 2
137#define DBCR_RST_SYSTEM 3
138#define DBCR_IC 0x08000000
139#define DBCR_BT 0x04000000
140#define DBCR_EDE 0x02000000
141#define DBCR_TDE 0x01000000
142#define DBCR_FER 0x00F80000
143#define DBCR_FT 0x00040000
144#define DBCR_IA1 0x00020000
145#define DBCR_IA2 0x00010000
146#define DBCR_D1R 0x00008000
147#define DBCR_D1W 0x00004000
148#define DBCR_D1S(x) (((x) & 0x3) << 12)
149#define DAC_BYTE 0
150#define DAC_HALF 1
151#define DAC_WORD 2
152#define DAC_QUAD 3
153#define DBCR_D2R 0x00000800
154#define DBCR_D2W 0x00000400
155#define DBCR_D2S(x) (((x) & 0x3) << 8)
156#define DBCR_SBT 0x00000040
157#define DBCR_SED 0x00000020
158#define DBCR_STD 0x00000010
159#define DBCR_SIA 0x00000008
160#define DBCR_SDA 0x00000004
161#define DBCR_JOI 0x00000002
162#define DBCR_JII 0x00000001
163#ifndef CONFIG_BOOKE
164#define SPRN_DBCR0 0x3F2
165#else
166#define SPRN_DBCR0 0x134
167#endif
168#ifndef CONFIG_BOOKE
169#define SPRN_DBCR1 0x3BD
170#define SPRN_DBSR 0x3F0
171#else
172#define SPRN_DBCR1 0x135
173#ifdef CONFIG_BOOKE
174#define SPRN_DBDR 0x3f3
175#endif
176#define SPRN_DBSR 0x130
177#define DBSR_IC 0x08000000
178#define DBSR_TIE 0x01000000
179#endif
180#define SPRN_DCCR 0x3FA
181#define DCCR_NOCACHE 0
182#define DCCR_CACHE 1
183#ifndef CONFIG_BOOKE
184#define SPRN_DCDBTRL 0x39c
185#define SPRN_DCDBTRH 0x39d
186#endif
187#define SPRN_DCMP 0x3D1
188#define SPRN_DCWR 0x3BA
189#define DCWR_COPY 0
190#define DCWR_WRITE 1
191#ifndef CONFIG_BOOKE
192#define SPRN_DEAR 0x3D5
193#else
194#define SPRN_DEAR 0x03D
195#endif
196#define SPRN_DEC 0x016
197#define SPRN_DMISS 0x3D0
198#ifdef CONFIG_BOOKE
199#define SPRN_DNV0 0x390
200#define SPRN_DNV1 0x391
201#define SPRN_DNV2 0x392
202#define SPRN_DNV3 0x393
203#endif
204#define SPRN_DSISR 0x012
205#ifdef CONFIG_BOOKE
206#define SPRN_DTV0 0x394
207#define SPRN_DTV1 0x395
208#define SPRN_DTV2 0x396
209#define SPRN_DTV3 0x397
210#define SPRN_DVLIM 0x398
211#endif
212#define SPRN_EAR 0x11A
213#ifndef CONFIG_BOOKE
214#define SPRN_ESR 0x3D4
215#else
216#define SPRN_ESR 0x03E
217#endif
218#define ESR_IMCP 0x80000000
219#define ESR_IMCN 0x40000000
220#define ESR_IMCB 0x20000000
221#define ESR_IMCT 0x10000000
222#define ESR_PIL 0x08000000
223#define ESR_PPR 0x04000000
224#define ESR_PTR 0x02000000
225#define ESR_DST 0x00800000
226#define ESR_DIZ 0x00400000
227#define SPRN_EVPR 0x3D6
228#define SPRN_HASH1 0x3D2
229#define SPRN_HASH2 0x3D3
230#define SPRN_HID0 0x3F0
231
232#define HID0_ICE_SHIFT 15
233#define HID0_DCE_SHIFT 14
234#define HID0_DLOCK_SHIFT 12
235
236#define HID0_EMCP (1<<31)
237#define HID0_EBA (1<<29)
238#define HID0_EBD (1<<28)
239#define HID0_SBCLK (1<<27)
240#define HID0_EICE (1<<26)
241#define HID0_ECLK (1<<25)
242#define HID0_PAR (1<<24)
243#define HID0_DOZE (1<<23)
244#define HID0_NAP (1<<22)
245#define HID0_SLEEP (1<<21)
246#define HID0_DPM (1<<20)
247#define HID0_ICE (1<<HID0_ICE_SHIFT)
248#define HID0_DCE (1<<HID0_DCE_SHIFT)
249#define HID0_TBEN (1<<14)
250#define HID0_ILOCK (1<<13)
251#define HID0_DLOCK (1<<HID0_DLOCK_SHIFT)
252#define HID0_ICFI (1<<11)
253#define HID0_DCFI (1<<10)
254#define HID0_DCI HID0_DCFI
255#define HID0_SPD (1<<9)
256#define HID0_ENMAS7 (1<<7)
257#define HID0_SGE (1<<7)
258#define HID0_SIED HID_SGE
259#define HID0_DCFA (1<<6)
260#define HID0_BTIC (1<<5)
261#define HID0_ABE (1<<3)
262#define HID0_BHTE (1<<2)
263#define HID0_BTCD (1<<1)
264#define SPRN_HID1 0x3F1
265#define HID1_RFXE (1<<17)
266#define HID1_ASTME (1<<13)
267#define HID1_ABE (1<<12)
268#define HID1_MBDD (1<<6)
269#define SPRN_IABR 0x3F2
270#ifndef CONFIG_BOOKE
271#define SPRN_IAC1 0x3F4
272#define SPRN_IAC2 0x3F5
273#else
274#define SPRN_IAC1 0x138
275#define SPRN_IAC2 0x139
276#endif
277#define SPRN_IBAT0L 0x211
278#define SPRN_IBAT0U 0x210
279#define SPRN_IBAT1L 0x213
280#define SPRN_IBAT1U 0x212
281#define SPRN_IBAT2L 0x215
282#define SPRN_IBAT2U 0x214
283#define SPRN_IBAT3L 0x217
284#define SPRN_IBAT3U 0x216
285#define SPRN_IBAT4L 0x231
286#define SPRN_IBAT4U 0x230
287#define SPRN_IBAT5L 0x233
288#define SPRN_IBAT5U 0x232
289#define SPRN_IBAT6L 0x235
290#define SPRN_IBAT6U 0x234
291#define SPRN_IBAT7L 0x237
292#define SPRN_IBAT7U 0x236
293#define SPRN_ICCR 0x3FB
294#define ICCR_NOCACHE 0
295#define ICCR_CACHE 1
296#define SPRN_ICDBDR 0x3D3
297#ifdef CONFIG_BOOKE
298#define SPRN_ICDBTRL 0x39e
299#define SPRN_ICDBTRH 0x39f
300#endif
301#define SPRN_ICMP 0x3D5
302#define SPRN_ICTC 0x3FB
303#define SPRN_IMISS 0x3D4
304#define SPRN_IMMR 0x27E
305#ifdef CONFIG_BOOKE
306#define SPRN_INV0 0x370
307#define SPRN_INV1 0x371
308#define SPRN_INV2 0x372
309#define SPRN_INV3 0x373
310#define SPRN_ITV0 0x374
311#define SPRN_ITV1 0x375
312#define SPRN_ITV2 0x376
313#define SPRN_ITV3 0x377
314#define SPRN_IVLIM 0x399
315#endif
316#define SPRN_LDSTCR 0x3F8
317#define SPRN_L2CR 0x3F9
318#define SPRN_LR 0x008
319#define SPRN_MBAR 0x137
320#define SPRN_MMCR0 0x3B8
321#define SPRN_MMCR1 0x3BC
322#ifdef CONFIG_BOOKE
323#define SPRN_MMUCR 0x3b2
324#endif
325#define SPRN_PBL1 0x3FC
326#define SPRN_PBL2 0x3FE
327#define SPRN_PBU1 0x3FD
328#define SPRN_PBU2 0x3FF
329#ifndef CONFIG_BOOKE
330#define SPRN_PID 0x3B1
331#define SPRN_PIR 0x3FF
332#else
333#define SPRN_PID 0x030
334#define SPRN_PIR 0x11E
335#endif
336#define SPRN_PIT 0x3DB
337#define SPRN_PMC1 0x3B9
338#define SPRN_PMC2 0x3BA
339#define SPRN_PMC3 0x3BD
340#define SPRN_PMC4 0x3BE
341#define SPRN_PVR 0x11F
342#define SPRN_RPA 0x3D6
343#ifdef CONFIG_BOOKE
344#define SPRN_RSTCFG 0x39b
345#endif
346#define SPRN_SDA 0x3BF
347#define SPRN_SDR1 0x019
348#define SPRN_SGR 0x3B9
349#define SGR_NORMAL 0
350#define SGR_GUARDED 1
351#define SPRN_SIA 0x3BB
352#define SPRN_SPRG0 0x110
353#define SPRN_SPRG1 0x111
354#define SPRN_SPRG2 0x112
355#define SPRN_SPRG3 0x113
356#define SPRN_SPRG4 0x114
357#define SPRN_SPRG5 0x115
358#define SPRN_SPRG6 0x116
359#define SPRN_SPRG7 0x117
360#define SPRN_SRR0 0x01A
361#define SPRN_SRR1 0x01B
362#define SPRN_SRR2 0x3DE
363#define SPRN_SRR3 0x3DF
364
365#ifdef CONFIG_BOOKE
366#define SPRN_SVR 0x3FF
367#else
368#define SPRN_SVR 0x11E
369#endif
370#define SPRN_TBHI 0x3DC
371#define SPRN_TBHU 0x3CC
372#define SPRN_TBLO 0x3DD
373#define SPRN_TBLU 0x3CD
374#define SPRN_TBRL 0x10C
375#define SPRN_TBRU 0x10D
376#define SPRN_TBWL 0x11C
377#define SPRN_TBWU 0x11D
378#ifndef CONFIG_BOOKE
379#define SPRN_TCR 0x3DA
380#else
381#define SPRN_TCR 0x154
382#endif
383#define TCR_WP(x) (((x)&0x3)<<30)
384#define WP_2_17 0
385#define WP_2_21 1
386#define WP_2_25 2
387#define WP_2_29 3
388#define TCR_WRC(x) (((x)&0x3)<<28)
389#define WRC_NONE 0
390#define WRC_CORE 1
391#define WRC_CHIP 2
392#define WRC_SYSTEM 3
393#define TCR_WIE 0x08000000
394#define TCR_PIE 0x04000000
395#define TCR_FP(x) (((x)&0x3)<<24)
396#define FP_2_9 0
397#define FP_2_13 1
398#define FP_2_17 2
399#define FP_2_21 3
400#define TCR_FIE 0x00800000
401#define TCR_ARE 0x00400000
402#define SPRN_THRM1 0x3FC
403#define THRM1_TIN (1<<0)
404#define THRM1_TIV (1<<1)
405#define THRM1_THRES (0x7f<<2)
406#define THRM1_TID (1<<29)
407#define THRM1_TIE (1<<30)
408#define THRM1_V (1<<31)
409#define SPRN_THRM2 0x3FD
410#define SPRN_THRM3 0x3FE
411#define THRM3_E (1<<31)
412#define SPRN_TLBMISS 0x3D4
413#ifndef CONFIG_BOOKE
414#define SPRN_TSR 0x3D8
415#else
416#define SPRN_TSR 0x150
417#endif
418#define TSR_ENW 0x80000000
419#define TSR_WIS 0x40000000
420#define TSR_WRS(x) (((x)&0x3)<<28)
421#define WRS_NONE 0
422#define WRS_CORE 1
423#define WRS_CHIP 2
424#define WRS_SYSTEM 3
425#define TSR_PIS 0x08000000
426#define TSR_FIS 0x04000000
427#define SPRN_UMMCR0 0x3A8
428#define SPRN_UMMCR1 0x3AC
429#define SPRN_UPMC1 0x3A9
430#define SPRN_UPMC2 0x3AA
431#define SPRN_UPMC3 0x3AD
432#define SPRN_UPMC4 0x3AE
433#define SPRN_USIA 0x3AB
434#define SPRN_XER 0x001
435#define SPRN_ZPR 0x3B0
436
437
438#define SPRN_DECAR 0x036
439#define SPRN_CSRR0 0x03A
440#define SPRN_CSRR1 0x03B
441#define SPRN_IVPR 0x03F
442#define SPRN_USPRG0 0x100
443#define SPRN_SPRG4R 0x104
444#define SPRN_SPRG5R 0x105
445#define SPRN_SPRG6R 0x106
446#define SPRN_SPRG7R 0x107
447#define SPRN_SPRG4W 0x114
448#define SPRN_SPRG5W 0x115
449#define SPRN_SPRG6W 0x116
450#define SPRN_SPRG7W 0x117
451#define SPRN_DBCR2 0x136
452#define SPRN_IAC3 0x13A
453#define SPRN_IAC4 0x13B
454#define SPRN_DVC1 0x13E
455#define SPRN_DVC2 0x13F
456#define SPRN_IVOR0 0x190
457#define SPRN_IVOR1 0x191
458#define SPRN_IVOR2 0x192
459#define SPRN_IVOR3 0x193
460#define SPRN_IVOR4 0x194
461#define SPRN_IVOR5 0x195
462#define SPRN_IVOR6 0x196
463#define SPRN_IVOR7 0x197
464#define SPRN_IVOR8 0x198
465#define SPRN_IVOR9 0x199
466#define SPRN_IVOR10 0x19a
467#define SPRN_IVOR11 0x19b
468#define SPRN_IVOR12 0x19c
469#define SPRN_IVOR13 0x19d
470#define SPRN_IVOR14 0x19e
471#define SPRN_IVOR15 0x19f
472#define SPRN_IVOR38 0x1b0
473#define SPRN_IVOR39 0x1b1
474#define SPRN_IVOR40 0x1b2
475#define SPRN_IVOR41 0x1b3
476#define SPRN_GIVOR2 0x1b8
477#define SPRN_GIVOR3 0x1b9
478#define SPRN_GIVOR4 0x1ba
479#define SPRN_GIVOR8 0x1bb
480#define SPRN_GIVOR13 0x1bc
481#define SPRN_GIVOR14 0x1bd
482
483
484#define SPRN_L1CFG0 0x203
485#define SPRN_L1CFG1 0x204
486#define SPRN_L2CFG0 0x207
487#define SPRN_L1CSR0 0x3f2
488#define L1CSR0_CPE 0x00010000
489#define L1CSR0_CUL 0x00000400
490#define L1CSR0_DCLFR 0x00000100
491#define L1CSR0_DCFI 0x00000002
492#define L1CSR0_DCE 0x00000001
493#define SPRN_L1CSR1 0x3f3
494#define L1CSR1_CPE 0x00010000
495#define L1CSR1_ICUL 0x00000400
496#define L1CSR1_ICLFR 0x00000100
497#define L1CSR1_ICFI 0x00000002
498#define L1CSR1_ICE 0x00000001
499#define SPRN_L1CSR2 0x25e
500#define L1CSR2_DCWS 0x40000000
501#define SPRN_L2CSR0 0x3f9
502#define L2CSR0_L2E 0x80000000
503#define L2CSR0_L2PE 0x40000000
504#define L2CSR0_L2WP 0x1c000000
505#define L2CSR0_L2CM 0x03000000
506#define L2CSR0_L2FI 0x00200000
507#define L2CSR0_L2IO 0x00100000
508#define L2CSR0_L2DO 0x00010000
509#define L2CSR0_L2REP 0x00003000
510#define L2CSR0_L2FL 0x00000800
511#define L2CSR0_L2LFC 0x00000400
512#define L2CSR0_L2LOA 0x00000080
513#define L2CSR0_L2LO 0x00000020
514#define SPRN_L2CSR1 0x3fa
515
516#define SPRN_TLB0CFG 0x2B0
517#define SPRN_TLB1CFG 0x2B1
518#define TLBnCFG_NENTRY_MASK 0x00000fff
519#define SPRN_TLB0PS 0x158
520#define SPRN_TLB1PS 0x159
521#define SPRN_MMUCSR0 0x3f4
522#define SPRN_MMUCFG 0x3F7
523#define MMUCFG_MAVN 0x00000003
524#define MMUCFG_MAVN_V1 0x00000000
525#define MMUCFG_MAVN_V2 0x00000001
526#define SPRN_MAS0 0x270
527#define SPRN_MAS1 0x271
528#define SPRN_MAS2 0x272
529#define SPRN_MAS3 0x273
530#define SPRN_MAS4 0x274
531#define SPRN_MAS5 0x275
532#define SPRN_MAS6 0x276
533#define SPRN_MAS7 0x3B0
534#define SPRN_MAS8 0x155
535
536#define SPRN_IVOR32 0x210
537#define SPRN_IVOR33 0x211
538#define SPRN_IVOR34 0x212
539#define SPRN_IVOR35 0x213
540#define SPRN_IVOR36 0x214
541#define SPRN_IVOR37 0x215
542#define SPRN_SPEFSCR 0x200
543
544#define SPRN_MCSRR0 0x23a
545#define SPRN_MCSRR1 0x23b
546#define SPRN_BUCSR 0x3f5
547#define BUCSR_STAC_EN 0x01000000
548#define BUCSR_LS_EN 0x00400000
549#define BUCSR_BBFI 0x00000200
550#define BUCSR_BPEN 0x00000001
551#define BUCSR_ENABLE (BUCSR_STAC_EN|BUCSR_LS_EN|BUCSR_BBFI|BUCSR_BPEN)
552#define SPRN_BBEAR 0x201
553#define SPRN_BBTAR 0x202
554#define SPRN_PID1 0x279
555#define SPRN_PID2 0x27a
556#define SPRN_MCSR 0x23c
557#define SPRN_MCAR 0x23d
558#define MCSR_MCS 0x80000000
559#define MCSR_IB 0x40000000
560#if defined(CONFIG_440)
561#define MCSR_DRB 0x20000000
562#define MCSR_DWB 0x10000000
563#else
564#define MCSR_DB 0x20000000
565#endif
566#define MCSR_TLBP 0x08000000
567#define MCSR_ICP 0x04000000
568#define MCSR_DCSP 0x02000000
569#define MCSR_DCFP 0x01000000
570#define MCSR_IMPE 0x00800000
571#define ESR_ST 0x00800000
572
573#if defined(CONFIG_MPC86xx)
574#define SPRN_MSSCR0 0x3f6
575#define SPRN_MSSSR0 0x3f7
576#endif
577
578
579
580#define CTR SPRN_CTR
581#define DAR SPRN_DAR
582#define DABR SPRN_DABR
583#define DAC1 SPRN_DAC1
584#define DAC2 SPRN_DAC2
585#define DBAT0L SPRN_DBAT0L
586#define DBAT0U SPRN_DBAT0U
587#define DBAT1L SPRN_DBAT1L
588#define DBAT1U SPRN_DBAT1U
589#define DBAT2L SPRN_DBAT2L
590#define DBAT2U SPRN_DBAT2U
591#define DBAT3L SPRN_DBAT3L
592#define DBAT3U SPRN_DBAT3U
593#define DBAT4L SPRN_DBAT4L
594#define DBAT4U SPRN_DBAT4U
595#define DBAT5L SPRN_DBAT5L
596#define DBAT5U SPRN_DBAT5U
597#define DBAT6L SPRN_DBAT6L
598#define DBAT6U SPRN_DBAT6U
599#define DBAT7L SPRN_DBAT7L
600#define DBAT7U SPRN_DBAT7U
601#define DBCR0 SPRN_DBCR0
602#define DBCR1 SPRN_DBCR1
603#define DBSR SPRN_DBSR
604#define DCMP SPRN_DCMP
605#define DEC SPRN_DEC
606#define DMISS SPRN_DMISS
607#define DSISR SPRN_DSISR
608#define EAR SPRN_EAR
609#define ESR SPRN_ESR
610#define HASH1 SPRN_HASH1
611#define HASH2 SPRN_HASH2
612#define HID0 SPRN_HID0
613#define HID1 SPRN_HID1
614#define IABR SPRN_IABR
615#define IAC1 SPRN_IAC1
616#define IAC2 SPRN_IAC2
617#define IBAT0L SPRN_IBAT0L
618#define IBAT0U SPRN_IBAT0U
619#define IBAT1L SPRN_IBAT1L
620#define IBAT1U SPRN_IBAT1U
621#define IBAT2L SPRN_IBAT2L
622#define IBAT2U SPRN_IBAT2U
623#define IBAT3L SPRN_IBAT3L
624#define IBAT3U SPRN_IBAT3U
625#define IBAT4L SPRN_IBAT4L
626#define IBAT4U SPRN_IBAT4U
627#define IBAT5L SPRN_IBAT5L
628#define IBAT5U SPRN_IBAT5U
629#define IBAT6L SPRN_IBAT6L
630#define IBAT6U SPRN_IBAT6U
631#define IBAT7L SPRN_IBAT7L
632#define IBAT7U SPRN_IBAT7U
633#define ICMP SPRN_ICMP
634#define IMISS SPRN_IMISS
635#define IMMR SPRN_IMMR
636#define LDSTCR SPRN_LDSTCR
637#define L2CR SPRN_L2CR
638#define LR SPRN_LR
639#define MBAR SPRN_MBAR
640#if defined(CONFIG_MPC86xx)
641#define MSSCR0 SPRN_MSSCR0
642#endif
643#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
644#define PIR SPRN_PIR
645#endif
646#define SVR SPRN_SVR
647#define PVR SPRN_PVR
648#define RPA SPRN_RPA
649#define SDR1 SPRN_SDR1
650#define SPR0 SPRN_SPRG0
651#define SPR1 SPRN_SPRG1
652#define SPR2 SPRN_SPRG2
653#define SPR3 SPRN_SPRG3
654#define SPRG0 SPRN_SPRG0
655#define SPRG1 SPRN_SPRG1
656#define SPRG2 SPRN_SPRG2
657#define SPRG3 SPRN_SPRG3
658#define SPRG4 SPRN_SPRG4
659#define SPRG5 SPRN_SPRG5
660#define SPRG6 SPRN_SPRG6
661#define SPRG7 SPRN_SPRG7
662#define SRR0 SPRN_SRR0
663#define SRR1 SPRN_SRR1
664#define SRR2 SPRN_SRR2
665#define SRR3 SPRN_SRR3
666#define SVR SPRN_SVR
667#define TBRL SPRN_TBRL
668#define TBRU SPRN_TBRU
669#define TBWL SPRN_TBWL
670#define TBWU SPRN_TBWU
671#define TCR SPRN_TCR
672#define TSR SPRN_TSR
673#define ICTC 1019
674#define THRM1 SPRN_THRM1
675#define THRM2 SPRN_THRM2
676#define THRM3 SPRN_THRM3
677#define XER SPRN_XER
678
679#define DECAR SPRN_DECAR
680#define CSRR0 SPRN_CSRR0
681#define CSRR1 SPRN_CSRR1
682#define IVPR SPRN_IVPR
683#define USPRG0 SPRN_USPRG
684#define SPRG4R SPRN_SPRG4R
685#define SPRG5R SPRN_SPRG5R
686#define SPRG6R SPRN_SPRG6R
687#define SPRG7R SPRN_SPRG7R
688#define SPRG4W SPRN_SPRG4W
689#define SPRG5W SPRN_SPRG5W
690#define SPRG6W SPRN_SPRG6W
691#define SPRG7W SPRN_SPRG7W
692#define DEAR SPRN_DEAR
693#define DBCR2 SPRN_DBCR2
694#define IAC3 SPRN_IAC3
695#define IAC4 SPRN_IAC4
696#define DVC1 SPRN_DVC1
697#define DVC2 SPRN_DVC2
698#define IVOR0 SPRN_IVOR0
699#define IVOR1 SPRN_IVOR1
700#define IVOR2 SPRN_IVOR2
701#define IVOR3 SPRN_IVOR3
702#define IVOR4 SPRN_IVOR4
703#define IVOR5 SPRN_IVOR5
704#define IVOR6 SPRN_IVOR6
705#define IVOR7 SPRN_IVOR7
706#define IVOR8 SPRN_IVOR8
707#define IVOR9 SPRN_IVOR9
708#define IVOR10 SPRN_IVOR10
709#define IVOR11 SPRN_IVOR11
710#define IVOR12 SPRN_IVOR12
711#define IVOR13 SPRN_IVOR13
712#define IVOR14 SPRN_IVOR14
713#define IVOR15 SPRN_IVOR15
714#define IVOR32 SPRN_IVOR32
715#define IVOR33 SPRN_IVOR33
716#define IVOR34 SPRN_IVOR34
717#define IVOR35 SPRN_IVOR35
718#define MCSRR0 SPRN_MCSRR0
719#define MCSRR1 SPRN_MCSRR1
720#define L1CSR0 SPRN_L1CSR0
721#define L1CSR1 SPRN_L1CSR1
722#define L1CSR2 SPRN_L1CSR2
723#define L1CFG0 SPRN_L1CFG0
724#define L1CFG1 SPRN_L1CFG1
725#define L2CFG0 SPRN_L2CFG0
726#define L2CSR0 SPRN_L2CSR0
727#define L2CSR1 SPRN_L2CSR1
728#define MCSR SPRN_MCSR
729#define MMUCSR0 SPRN_MMUCSR0
730#define BUCSR SPRN_BUCSR
731#define PID0 SPRN_PID
732#define PID1 SPRN_PID1
733#define PID2 SPRN_PID2
734#define MAS0 SPRN_MAS0
735#define MAS1 SPRN_MAS1
736#define MAS2 SPRN_MAS2
737#define MAS3 SPRN_MAS3
738#define MAS4 SPRN_MAS4
739#define MAS5 SPRN_MAS5
740#define MAS6 SPRN_MAS6
741#define MAS7 SPRN_MAS7
742#define MAS8 SPRN_MAS8
743
744#if defined(CONFIG_4xx) || defined(CONFIG_44x) || defined(CONFIG_MPC85xx)
745#define DAR_DEAR DEAR
746#else
747#define DAR_DEAR DAR
748#endif
749
750
751
752#define DCRN_BEAR 0x090
753#define DCRN_BESR 0x091
754#define BESR_DSES 0x80000000
755#define BESR_DMES 0x40000000
756#define BESR_RWS 0x20000000
757#define BESR_ETMASK 0x1C000000
758#define ET_PROT 0
759#define ET_PARITY 1
760#define ET_NCFG 2
761#define ET_BUSERR 4
762#define ET_BUSTO 6
763#define DCRN_DMACC0 0x0C4
764#define DCRN_DMACC1 0x0CC
765#define DCRN_DMACC2 0x0D4
766#define DCRN_DMACC3 0x0DC
767#define DCRN_DMACR0 0x0C0
768#define DCRN_DMACR1 0x0C8
769#define DCRN_DMACR2 0x0D0
770#define DCRN_DMACR3 0x0D8
771#define DCRN_DMACT0 0x0C1
772#define DCRN_DMACT1 0x0C9
773#define DCRN_DMACT2 0x0D1
774#define DCRN_DMACT3 0x0D9
775#define DCRN_DMADA0 0x0C2
776#define DCRN_DMADA1 0x0CA
777#define DCRN_DMADA2 0x0D2
778#define DCRN_DMADA3 0x0DA
779#define DCRN_DMASA0 0x0C3
780#define DCRN_DMASA1 0x0CB
781#define DCRN_DMASA2 0x0D3
782#define DCRN_DMASA3 0x0DB
783#define DCRN_DMASR 0x0E0
784#define DCRN_EXIER 0x042
785#define EXIER_CIE 0x80000000
786#define EXIER_SRIE 0x08000000
787#define EXIER_STIE 0x04000000
788#define EXIER_JRIE 0x02000000
789#define EXIER_JTIE 0x01000000
790#define EXIER_D0IE 0x00800000
791#define EXIER_D1IE 0x00400000
792#define EXIER_D2IE 0x00200000
793#define EXIER_D3IE 0x00100000
794#define EXIER_E0IE 0x00000010
795#define EXIER_E1IE 0x00000008
796#define EXIER_E2IE 0x00000004
797#define EXIER_E3IE 0x00000002
798#define EXIER_E4IE 0x00000001
799#define DCRN_EXISR 0x040
800#define DCRN_IOCR 0x0A0
801#define IOCR_E0TE 0x80000000
802#define IOCR_E0LP 0x40000000
803#define IOCR_E1TE 0x20000000
804#define IOCR_E1LP 0x10000000
805#define IOCR_E2TE 0x08000000
806#define IOCR_E2LP 0x04000000
807#define IOCR_E3TE 0x02000000
808#define IOCR_E3LP 0x01000000
809#define IOCR_E4TE 0x00800000
810#define IOCR_E4LP 0x00400000
811#define IOCR_EDT 0x00080000
812#define IOCR_SOR 0x00040000
813#define IOCR_EDO 0x00008000
814#define IOCR_2XC 0x00004000
815#define IOCR_ATC 0x00002000
816#define IOCR_SPD 0x00001000
817#define IOCR_BEM 0x00000800
818#define IOCR_PTD 0x00000400
819#define IOCR_ARE 0x00000080
820#define IOCR_DRC 0x00000020
821#define IOCR_RDM(x) (((x) & 0x3) << 3)
822#define IOCR_TCS 0x00000004
823#define IOCR_SCS 0x00000002
824#define IOCR_SPC 0x00000001
825
826
827
828
829
830#define SVR_VER(svr) (((svr) >> 16) & 0xFFFF)
831#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF)
832
833#define SVR_CID(svr) (((svr) >> 28) & 0x0F)
834#define SVR_SOCOP(svr) (((svr) >> 22) & 0x3F)
835#define SVR_SID(svr) (((svr) >> 16) & 0x3F)
836#define SVR_PROC(svr) (((svr) >> 12) & 0x0F)
837#define SVR_MFG(svr) (((svr) >> 8) & 0x0F)
838#define SVR_MJREV(svr) (((svr) >> 4) & 0x0F)
839#define SVR_MNREV(svr) (((svr) >> 0) & 0x0F)
840
841
842
843
844
845#define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF)
846#define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF)
847
848
849
850
851
852
853#define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF)
854#define PVR_MEM(pvr) (((pvr) >> 16) & 0xF)
855#define PVR_CORE(pvr) (((pvr) >> 12) & 0xF)
856#define PVR_CFG(pvr) (((pvr) >> 8) & 0xF)
857#define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF)
858#define PVR_MIN(pvr) (((pvr) >> 0) & 0xF)
859
860
861
862#define PVR_E600_VER(pvr) (((pvr) >> 15) & 0xFFFF)
863#define PVR_E600_TECH(pvr) (((pvr) >> 12) & 0xF)
864#define PVR_E600_MAJ(pvr) (((pvr) >> 8) & 0xF)
865#define PVR_E600_MIN(pvr) (((pvr) >> 0) & 0xFF)
866
867
868
869#define PVR_403GA 0x00200000
870#define PVR_403GB 0x00200100
871#define PVR_403GC 0x00200200
872#define PVR_403GCX 0x00201400
873#define PVR_405GP 0x40110000
874#define PVR_405GP_RB 0x40110040
875#define PVR_405GP_RC 0x40110082
876#define PVR_405GP_RD 0x401100C4
877#define PVR_405GP_RE 0x40110145
878#define PVR_405CR_RA 0x40110041
879#define PVR_405CR_RB 0x401100C5
880#define PVR_405CR_RC 0x40110145
881#define PVR_405EP_RA 0x51210950
882#define PVR_405GPR_RB 0x50910951
883#define PVR_405EZ_RA 0x41511460
884#define PVR_405EXR2_RA 0x12911471
885#define PVR_405EX1_RA 0x12911477
886#define PVR_405EXR1_RC 0x1291147B
887#define PVR_405EXR2_RC 0x12911479
888#define PVR_405EX1_RC 0x1291147F
889#define PVR_405EX2_RC 0x1291147D
890#define PVR_405EXR1_RD 0x12911472
891#define PVR_405EXR2_RD 0x12911470
892#define PVR_405EX1_RD 0x12911475
893#define PVR_405EX2_RD 0x12911473
894#define PVR_440GP_RB 0x40120440
895#define PVR_440GP_RC 0x40120481
896#define PVR_440EP_RA 0x42221850
897#define PVR_440EP_RB 0x422218D3
898#define PVR_440EP_RC 0x422218D4
899#define PVR_440GR_RA 0x422218D3
900#define PVR_440GR_RB 0x422218D4
901#define PVR_440EPX1_RA 0x216218D0
902#define PVR_440EPX2_RA 0x216218D4
903#define PVR_440GRX1_RA 0x216218D0
904#define PVR_440GRX2_RA 0x216218D4
905#define PVR_440GX_RA 0x51B21850
906#define PVR_440GX_RB 0x51B21851
907#define PVR_440GX_RC 0x51B21892
908#define PVR_440GX_RF 0x51B21894
909#define PVR_405EP_RB 0x51210950
910#define PVR_440SP_6_RAB 0x53221850
911#define PVR_440SP_RAB 0x53321850
912#define PVR_440SP_6_RC 0x53221891
913#define PVR_440SP_RC 0x53321891
914#define PVR_440SPe_6_RA 0x53421890
915#define PVR_440SPe_RA 0x53521890
916#define PVR_440SPe_6_RB 0x53421891
917#define PVR_440SPe_RB 0x53521891
918#define PVR_460EX_SE_RA 0x130218A2
919#define PVR_460EX_RA 0x130218A3
920#define PVR_460EX_RB 0x130218A4
921#define PVR_460GT_SE_RA 0x130218A0
922#define PVR_460GT_RA 0x130218A1
923#define PVR_460GT_RB 0x130218A5
924#define PVR_460SX_RA 0x13541800
925#define PVR_460SX_RA_V1 0x13541801
926#define PVR_460GX_RA 0x13541802
927#define PVR_460GX_RA_V1 0x13541803
928#define PVR_APM821XX_RA 0x12C41C80
929#define PVR_601 0x00010000
930#define PVR_602 0x00050000
931#define PVR_603 0x00030000
932#define PVR_603e 0x00060000
933#define PVR_603ev 0x00070000
934#define PVR_603r 0x00071000
935#define PVR_604 0x00040000
936#define PVR_604e 0x00090000
937#define PVR_604r 0x000A0000
938#define PVR_620 0x00140000
939#define PVR_740 0x00080000
940#define PVR_750 PVR_740
941#define PVR_740P 0x10080000
942#define PVR_750P PVR_740P
943#define PVR_7400 0x000C0000
944#define PVR_7410 0x800C0000
945#define PVR_7450 0x80000000
946
947#define PVR_85xx 0x80200000
948#define PVR_85xx_REV1 (PVR_85xx | 0x0010)
949#define PVR_85xx_REV2 (PVR_85xx | 0x0020)
950#define PVR_VER_E500_V1 0x8020
951#define PVR_VER_E500_V2 0x8021
952#define PVR_VER_E500MC 0x8023
953#define PVR_VER_E5500 0x8024
954#define PVR_VER_E6500 0x8040
955
956#define PVR_86xx 0x80040000
957
958#define PVR_VIRTEX5 0x7ff21912
959
960
961
962
963
964
965
966#define PVR_821 0x00500000
967#define PVR_823 PVR_821
968#define PVR_850 PVR_821
969#define PVR_860 PVR_821
970#define PVR_7400 0x000C0000
971#define PVR_8240 0x00810100
972
973
974
975
976
977#define PVR_8260 PVR_8240
978#define PVR_8260_HIP3 0x00810101
979#define PVR_8260_HIP4 0x80811014
980#define PVR_8260_HIP7 0x80822011
981#define PVR_8260_HIP7R1 0x80822013
982#define PVR_8260_HIP7RA 0x80822014
983
984
985
986
987#define PVR_5200 0x80822011
988#define PVR_5200B 0x80822014
989
990
991
992
993#ifdef CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY
994#define CONFIG_SYS_4xx_CHIP_21_ERRATA
995#define CONFIG_405EX_CHIP21_PVR_REV_C PVR_405EX1_RC
996#define CONFIG_405EX_CHIP21_PVR_REV_D PVR_405EX1_RD
997#define CONFIG_405EX_CHIP21_ECID3_REV_D 0x0
998#endif
999
1000#ifdef CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY
1001#define CONFIG_SYS_4xx_CHIP_21_ERRATA
1002#define CONFIG_405EX_CHIP21_PVR_REV_C PVR_405EX2_RC
1003#define CONFIG_405EX_CHIP21_PVR_REV_D PVR_405EX2_RD
1004#define CONFIG_405EX_CHIP21_ECID3_REV_D 0x1
1005#endif
1006
1007#ifdef CONFIG_SYS_4xx_CHIP_21_405EXr_SECURITY
1008#define CONFIG_SYS_4xx_CHIP_21_ERRATA
1009#define CONFIG_405EX_CHIP21_PVR_REV_C PVR_405EXR1_RC
1010#define CONFIG_405EX_CHIP21_PVR_REV_D PVR_405EXR1_RD
1011#define CONFIG_405EX_CHIP21_ECID3_REV_D 0x2
1012#endif
1013
1014#ifdef CONFIG_SYS_4xx_CHIP_21_405EXr_NO_SECURITY
1015#define CONFIG_SYS_4xx_CHIP_21_ERRATA
1016#define CONFIG_405EX_CHIP21_PVR_REV_C PVR_405EXR2_RC
1017#define CONFIG_405EX_CHIP21_PVR_REV_D PVR_405EXR2_RD
1018#define CONFIG_405EX_CHIP21_ECID3_REV_D 0x3
1019#endif
1020
1021
1022
1023
1024
1025
1026
1027#define SVR_VER(svr) (((svr) >> 16) & 0xFFFF)
1028#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF)
1029
1030#define SVR_SUBVER(svr) (((svr) >> 8) & 0xFF)
1031
1032#define SVR_FAM(svr) (((svr) >> 20) & 0xFFF)
1033#define SVR_MEM(svr) (((svr) >> 16) & 0xF)
1034
1035#ifdef CONFIG_MPC8536
1036#define SVR_MAJ(svr) (((svr) >> 4) & 0x7)
1037#else
1038#define SVR_MAJ(svr) (((svr) >> 4) & 0xF)
1039#endif
1040#define SVR_MIN(svr) (((svr) >> 0) & 0xF)
1041
1042
1043#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFF7FF)
1044
1045
1046#if defined(CONFIG_MPC85xx)
1047#define IS_E_PROCESSOR(svr) (svr & 0x80000)
1048#else
1049#if defined(CONFIG_MPC83xx)
1050#define IS_E_PROCESSOR(spridr) (!(spridr & 0x00010000))
1051#endif
1052#endif
1053
1054#define IS_SVR_REV(svr, maj, min) \
1055 ((SVR_MAJ(svr) == maj) && (SVR_MIN(svr) == min))
1056
1057
1058
1059
1060
1061#define SVR_8533 0x803400
1062#define SVR_8535 0x803701
1063#define SVR_8536 0x803700
1064#define SVR_8540 0x803000
1065#define SVR_8541 0x807200
1066#define SVR_8543 0x803200
1067#define SVR_8544 0x803401
1068#define SVR_8545 0x803102
1069#define SVR_8547 0x803101
1070#define SVR_8548 0x803100
1071#define SVR_8555 0x807100
1072#define SVR_8560 0x807000
1073#define SVR_8567 0x807501
1074#define SVR_8568 0x807500
1075#define SVR_8569 0x808000
1076#define SVR_8572 0x80E000
1077#define SVR_P1010 0x80F100
1078#define SVR_P1011 0x80E500
1079#define SVR_P1012 0x80E501
1080#define SVR_P1013 0x80E700
1081#define SVR_P1014 0x80F101
1082#define SVR_P1017 0x80F700
1083#define SVR_P1020 0x80E400
1084#define SVR_P1021 0x80E401
1085#define SVR_P1022 0x80E600
1086#define SVR_P1023 0x80F600
1087#define SVR_P1024 0x80E402
1088#define SVR_P1025 0x80E403
1089#define SVR_P2010 0x80E300
1090#define SVR_P2020 0x80E200
1091#define SVR_P2040 0x821000
1092#define SVR_P2041 0x821001
1093#define SVR_P3041 0x821103
1094#define SVR_P4040 0x820100
1095#define SVR_P4080 0x820000
1096#define SVR_P5010 0x822100
1097#define SVR_P5020 0x822000
1098#define SVR_P5021 0X820500
1099#define SVR_P5040 0x820400
1100#define SVR_T4240 0x824000
1101#define SVR_T4120 0x824001
1102#define SVR_B4860 0X868000
1103#define SVR_G4860 0x868001
1104#define SVR_G4060 0x868003
1105#define SVR_B4440 0x868100
1106#define SVR_G4440 0x868101
1107#define SVR_B4420 0x868102
1108#define SVR_B4220 0x868103
1109
1110#define SVR_8610 0x80A000
1111#define SVR_8641 0x809000
1112#define SVR_8641D 0x809001
1113
1114#define SVR_9130 0x860001
1115#define SVR_9131 0x860000
1116
1117#define SVR_Unknown 0xFFFFFF
1118
1119#define _GLOBAL(n)\
1120 .globl n;\
1121n:
1122
1123
1124
1125#define stringify(s) tostring(s)
1126#define tostring(s) #s
1127
1128#define mfdcr(rn) ({unsigned int rval; \
1129 asm volatile("mfdcr %0," stringify(rn) \
1130 : "=r" (rval)); rval;})
1131#define mtdcr(rn, v) asm volatile("mtdcr " stringify(rn) ",%0" : : "r" (v))
1132
1133#define mfmsr() ({unsigned int rval; \
1134 asm volatile("mfmsr %0" : "=r" (rval)); rval;})
1135#define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v))
1136
1137#define mfspr(rn) ({unsigned int rval; \
1138 asm volatile("mfspr %0," stringify(rn) \
1139 : "=r" (rval)); rval;})
1140#define mtspr(rn, v) asm volatile("mtspr " stringify(rn) ",%0" : : "r" (v))
1141
1142#define tlbie(v) asm volatile("tlbie %0 \n sync" : : "r" (v))
1143
1144
1145
1146#define SR0 0
1147#define SR1 1
1148#define SR2 2
1149#define SR3 3
1150#define SR4 4
1151#define SR5 5
1152#define SR6 6
1153#define SR7 7
1154#define SR8 8
1155#define SR9 9
1156#define SR10 10
1157#define SR11 11
1158#define SR12 12
1159#define SR13 13
1160#define SR14 14
1161#define SR15 15
1162
1163#ifndef __ASSEMBLY__
1164
1165struct cpu_type {
1166 char name[15];
1167 u32 soc_ver;
1168 u32 num_cores;
1169 u32 mask;
1170};
1171
1172struct cpu_type *identify_cpu(u32 ver);
1173int fixup_cpu(void);
1174
1175#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
1176#define CPU_TYPE_ENTRY(n, v, nc) \
1177 { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc), \
1178 .mask = (1 << (nc)) - 1 }
1179#define CPU_TYPE_ENTRY_MASK(n, v, nc, m) \
1180 { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc), .mask = (m) }
1181#else
1182#if defined(CONFIG_MPC83xx)
1183#define CPU_TYPE_ENTRY(x) {#x, SPR_##x}
1184#endif
1185#endif
1186
1187
1188#ifndef CONFIG_MACH_SPECIFIC
1189extern int _machine;
1190extern int have_of;
1191#endif
1192
1193
1194extern int _prep_type;
1195
1196
1197
1198
1199extern unsigned char ucSystemType;
1200extern unsigned char ucBoardRev;
1201extern unsigned char ucBoardRevMaj, ucBoardRevMin;
1202
1203struct task_struct;
1204void start_thread(struct pt_regs *regs, unsigned long nip, unsigned long sp);
1205void release_thread(struct task_struct *);
1206
1207
1208
1209
1210extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
1211
1212
1213
1214
1215#define EISA_bus 0
1216#define EISA_bus__is_a_macro
1217#define MCA_bus 0
1218#define MCA_bus__is_a_macro
1219
1220
1221extern struct task_struct *last_task_used_math;
1222extern struct task_struct *last_task_used_altivec;
1223
1224
1225
1226
1227
1228
1229
1230#define TASK_SIZE (0x80000000UL)
1231
1232
1233
1234
1235#define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3)
1236
1237typedef struct {
1238 unsigned long seg;
1239} mm_segment_t;
1240
1241struct thread_struct {
1242 unsigned long ksp;
1243 unsigned long wchan;
1244 struct pt_regs *regs;
1245 mm_segment_t fs;
1246 void *pgdir;
1247 signed long last_syscall;
1248 double fpr[32];
1249 unsigned long fpscr_pad;
1250 unsigned long fpscr;
1251#ifdef CONFIG_ALTIVEC
1252 vector128 vr[32];
1253 vector128 vscr;
1254 unsigned long vrsave;
1255#endif
1256};
1257
1258#define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack)
1259
1260#define INIT_THREAD { \
1261 INIT_SP, \
1262 0, \
1263 (struct pt_regs *)INIT_SP - 1, \
1264 KERNEL_DS, \
1265 swapper_pg_dir, \
1266 0, \
1267 {0}, 0, 0 \
1268}
1269
1270
1271
1272
1273
1274#define INIT_MMAP { &init_mm, 0, 0x1000, NULL, \
1275 PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, \
1276 1, NULL, NULL }
1277
1278
1279
1280
1281static inline unsigned long thread_saved_pc(struct thread_struct *t)
1282{
1283 return (t->regs) ? t->regs->nip : 0;
1284}
1285
1286#define copy_segments(tsk, mm) do { } while (0)
1287#define release_segments(mm) do { } while (0)
1288#define forget_segments() do { } while (0)
1289
1290unsigned long get_wchan(struct task_struct *p);
1291
1292#define KSTK_EIP(tsk) ((tsk)->thread.regs->nip)
1293#define KSTK_ESP(tsk) ((tsk)->thread.regs->gpr[1])
1294
1295
1296
1297
1298#define THREAD_SIZE (2*PAGE_SIZE)
1299#define alloc_task_struct() \
1300 ((struct task_struct *) __get_free_pages(GFP_KERNEL,1))
1301#define free_task_struct(p) free_pages((unsigned long)(p),1)
1302#define get_task_struct(tsk) atomic_inc(&mem_map[MAP_NR(tsk)].count)
1303
1304
1305int ll_printk(const char *, ...);
1306void ll_puts(const char *);
1307
1308#define init_task (init_task_union.task)
1309#define init_stack (init_task_union.stack)
1310
1311
1312void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
1313
1314#endif
1315
1316#ifdef CONFIG_MACH_SPECIFIC
1317#if defined(CONFIG_8xx)
1318#define _machine _MACH_8xx
1319#define have_of 0
1320#elif defined(CONFIG_OAK)
1321#define _machine _MACH_oak
1322#define have_of 0
1323#elif defined(CONFIG_WALNUT)
1324#define _machine _MACH_walnut
1325#define have_of 0
1326#elif defined(CONFIG_APUS)
1327#define _machine _MACH_apus
1328#define have_of 0
1329#elif defined(CONFIG_GEMINI)
1330#define _machine _MACH_gemini
1331#define have_of 0
1332#elif defined(CONFIG_8260)
1333#define _machine _MACH_8260
1334#define have_of 0
1335#elif defined(CONFIG_SANDPOINT)
1336#define _machine _MACH_sandpoint
1337#elif defined(CONFIG_HIDDEN_DRAGON)
1338#define _machine _MACH_hidden_dragon
1339#define have_of 0
1340#else
1341#error "Machine not defined correctly"
1342#endif
1343#endif
1344
1345#if defined(CONFIG_MPC85xx) || defined(CONFIG_440)
1346 #define EPAPR_MAGIC (0x45504150)
1347#else
1348 #define EPAPR_MAGIC (0x65504150)
1349#endif
1350
1351#endif
1352