LXR uboot/arch/sh/include/asm/cpu

   1/*
   2 * Copyright (C) 2012  Renesas Solutions Corp.
   3 *
   4 * This program is free software; you can redistribute it and/or
   5 * modify it under the terms of the GNU General Public License as
   6 * published by the Free Software Foundation; either version 2 of
   7 * the License, or (at your option) any later version.
   8 *
   9 * This program is distributed in the hope that it will be useful,
  10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12 * GNU General Public License for more details.
  13 *
  14 * You should have received a copy of the GNU General Public License
  15 * along with this program; if not, write to the Free Software
  16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  17 * MA 02111-1307 USA
  18 *
  19 */
  20
  21#ifndef _ASM_CPU_SH7752_H_
  22#define _ASM_CPU_SH7752_H_
  23
  24#define CCR             0xFF00001C
  25#define WTCNT           0xFFCC0000
  26#define CCR_CACHE_INIT  0x0000090b
  27#define CACHE_OC_NUM_WAYS       1
  28
  29#ifndef __ASSEMBLY__            /* put C only stuff in this section */
  30/* MMU */
  31struct mmu_regs {
  32        unsigned int    reserved[4];
  33        unsigned int    mmucr;
  34};
  35#define MMU_BASE        ((struct mmu_regs *)0xff000000)
  36
  37/* Watchdog */
  38#define WTCSR0          0xffcc0002
  39#define WRSTCSR_R       0xffcc0003
  40#define WRSTCSR_W       0xffcc0002
  41#define WTCSR_PREFIX            0xa500
  42#define WRSTCSR_PREFIX          0x6900
  43#define WRSTCSR_WOVF_PREFIX     0x9600
  44
  45/* SCIF */
  46#define SCIF0_BASE      0xfe4b0000      /* The real name is SCIF2 */
  47#define SCIF1_BASE      0xfe4c0000      /* The real name is SCIF3 */
  48#define SCIF2_BASE      0xfe4d0000      /* The real name is SCIF4 */
  49
  50/* TMU0 */
  51#define TMU_BASE         0xFE430000
  52
  53/* ETHER, GETHER MAC address */
  54struct ether_mac_regs {
  55        unsigned int    reserved[114];
  56        unsigned int    mahr;
  57        unsigned int    reserved2;
  58        unsigned int    malr;
  59};
  60#define GETHER0_MAC_BASE        ((struct ether_mac_regs *)0xfee0400)
  61#define GETHER1_MAC_BASE        ((struct ether_mac_regs *)0xfee0c00)
  62#define ETHER0_MAC_BASE         ((struct ether_mac_regs *)0xfef0000)
  63#define ETHER1_MAC_BASE         ((struct ether_mac_regs *)0xfef0800)
  64
  65/* GETHER */
  66struct gether_control_regs {
  67        unsigned int    gbecont;
  68};
  69#define GETHER_CONTROL_BASE     ((struct gether_control_regs *)0xffc10100)
  70#define GBECONT_RMII1           0x00020000
  71#define GBECONT_RMII0           0x00010000
  72
  73/* SerMux */
  74struct sermux_regs {
  75        unsigned char   smr0;
  76        unsigned char   smr1;
  77        unsigned char   smr2;
  78        unsigned char   smr3;
  79        unsigned char   smr4;
  80        unsigned char   smr5;
  81};
  82#define SERMUX_BASE     ((struct sermux_regs *)0xfe470000)
  83
  84
  85/* USB0/1 */
  86struct usb_common_regs {
  87        unsigned short  reserved[129];
  88        unsigned short  suspmode;
  89};
  90#define USB0_COMMON_BASE        ((struct usb_common_regs *)0xfe450000)
  91#define USB1_COMMON_BASE        ((struct usb_common_regs *)0xfe4f0000)
  92
  93struct usb0_phy_regs {
  94        unsigned short  reset;
  95        unsigned short  reserved[4];
  96        unsigned short  portsel;
  97};
  98#define USB0_PHY_BASE           ((struct usb0_phy_regs *)0xfe5f0000)
  99
 100struct usb1_port_regs {
 101        unsigned int    port1sel;
 102        unsigned int    reserved;
 103        unsigned int    usb1intsts;
 104};
 105#define USB1_PORT_BASE          ((struct usb1_port_regs *)0xfe4f2000)
 106
 107struct usb1_alignment_regs {
 108        unsigned int    ehcidatac;      /* 0xfe4fe018 */
 109        unsigned int    reserved[63];
 110        unsigned int    ohcidatac;
 111};
 112#define USB1_ALIGNMENT_BASE     ((struct usb1_alignment_regs *)0xfe4fe018)
 113
 114/* GPIO */
 115struct gpio_regs {
 116        unsigned short  pacr;
 117        unsigned short  pbcr;
 118        unsigned short  pccr;
 119        unsigned short  pdcr;
 120        unsigned short  pecr;
 121        unsigned short  pfcr;
 122        unsigned short  pgcr;
 123        unsigned short  phcr;
 124        unsigned short  picr;
 125        unsigned short  pjcr;
 126        unsigned short  pkcr;
 127        unsigned short  plcr;
 128        unsigned short  pmcr;
 129        unsigned short  pncr;
 130        unsigned short  pocr;
 131        unsigned short  reserved;
 132        unsigned short  pqcr;
 133        unsigned short  prcr;
 134        unsigned short  pscr;
 135        unsigned short  ptcr;
 136        unsigned short  pucr;
 137        unsigned short  pvcr;
 138        unsigned short  pwcr;
 139        unsigned short  pxcr;
 140        unsigned short  pycr;
 141        unsigned short  pzcr;
 142        unsigned char   padr;
 143        unsigned char   reserved_a;
 144        unsigned char   pbdr;
 145        unsigned char   reserved_b;
 146        unsigned char   pcdr;
 147        unsigned char   reserved_c;
 148        unsigned char   pddr;
 149        unsigned char   reserved_d;
 150        unsigned char   pedr;
 151        unsigned char   reserved_e;
 152        unsigned char   pfdr;
 153        unsigned char   reserved_f;
 154        unsigned char   pgdr;
 155        unsigned char   reserved_g;
 156        unsigned char   phdr;
 157        unsigned char   reserved_h;
 158        unsigned char   pidr;
 159        unsigned char   reserved_i;
 160        unsigned char   pjdr;
 161        unsigned char   reserved_j;
 162        unsigned char   pkdr;
 163        unsigned char   reserved_k;
 164        unsigned char   pldr;
 165        unsigned char   reserved_l;
 166        unsigned char   pmdr;
 167        unsigned char   reserved_m;
 168        unsigned char   pndr;
 169        unsigned char   reserved_n;
 170        unsigned char   podr;
 171        unsigned char   reserved_o;
 172        unsigned char   ppdr;
 173        unsigned char   reserved_p;
 174        unsigned char   pqdr;
 175        unsigned char   reserved_q;
 176        unsigned char   prdr;
 177        unsigned char   reserved_r;
 178        unsigned char   psdr;
 179        unsigned char   reserved_s;
 180        unsigned char   ptdr;
 181        unsigned char   reserved_t;
 182        unsigned char   pudr;
 183        unsigned char   reserved_u;
 184        unsigned char   pvdr;
 185        unsigned char   reserved_v;
 186        unsigned char   pwdr;
 187        unsigned char   reserved_w;
 188        unsigned char   pxdr;
 189        unsigned char   reserved_x;
 190        unsigned char   pydr;
 191        unsigned char   reserved_y;
 192        unsigned char   pzdr;
 193        unsigned char   reserved_z;
 194        unsigned short  ncer;
 195        unsigned short  ncmcr;
 196        unsigned short  nccsr;
 197        unsigned char   reserved2[2];
 198        unsigned short  psel0;          /* +0x70 */
 199        unsigned short  psel1;
 200        unsigned short  psel2;
 201        unsigned short  psel3;
 202        unsigned short  psel4;
 203        unsigned short  psel5;
 204        unsigned short  psel6;
 205        unsigned short  reserved3[2];
 206        unsigned short  psel7;
 207};
 208#define GPIO_BASE       ((struct gpio_regs *)0xffec0000)
 209
 210#endif  /* ifndef __ASSEMBLY__ */
 211#endif  /* _ASM_CPU_SH7752_H_ */
 212