LXR uboot/board/flagadm/flagadm.c

   1/*
   2 * (C) Copyright 2001
   3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24#include <common.h>
  25#include <mpc8xx.h>
  26
  27#define _NOT_USED_      0xFFFFFFFF
  28
  29/*Orginal table, GPL4 disabled*/
  30const uint sdram_table[] =
  31{
  32        /* single read   (offset 0x00 in upm ram) */
  33        0x1f07cc04, 0xeeaeec04, 0x11adcc04, 0xefbbac00,
  34        0x1ff74c47,
  35        /* Precharge */
  36        0x1FF74C05,
  37        _NOT_USED_,
  38        _NOT_USED_,
  39        /* burst read    (offset 0x08 in upm ram) */
  40        0x1f07cc04, 0xeeaeec04, 0x00adcc04, 0x00afcc00,
  41        0x00afcc00, 0x01afcc00, 0x0fbb8c00, 0x1ff74c47,
  42        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  43        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  44        /* single write  (offset 0x18 in upm ram) */
  45        0x1f27cc04, 0xeeaeac00, 0x01b90c04, 0x1ff74c47,
  46        /* Load moderegister */
  47        0x1FF74C34, /*Precharge*/
  48        0xEFEA8C34, /*NOP*/
  49        0x1FB54C35, /*Load moderegister*/
  50        _NOT_USED_,
  51
  52        /* burst write   (offset 0x20 in upm ram) */
  53        0x1f07cc04, 0xeeaeac00, 0x00ad4c00, 0x00afcc00,
  54        0x00afcc00, 0x01bb8c04, 0x1ff74c47, _NOT_USED_,
  55        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  56        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  57        /* refresh       (offset 0x30 in upm ram) */
  58        0x1ff5cc84, 0xffffec04, 0xffffec04, 0xffffec04,
  59        0xffffec84, 0xffffec07, _NOT_USED_, _NOT_USED_,
  60        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  61        /* exception     (offset 0x3C in upm ram) */
  62        0x7fffec07, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  63};
  64
  65/* GPL5 driven every cycle */
  66/* the display and the DSP */
  67const uint dsp_disp_table[] =
  68{
  69        /* single read   (offset 0x00 in upm ram) */
  70        0xffffc80c, 0xffffc004, 0x0fffc004, 0x0fffd004,
  71        0x0fffc000, 0x0fffc004, 0x3fffc004, 0xffffcc05,
  72        /* burst read    (offset 0x08 in upm ram) */
  73        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  74        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  75        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  76        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  77        /* single write  (offset 0x18 in upm ram) */
  78        0xffffcc0c, 0xffffc004, 0x0fffc004, 0x0fffd004,
  79        0x0fffc000, 0x0fffc004, 0x7fffc004, 0xfffffc05,
  80        /* burst write   (offset 0x20 in upm ram) */
  81        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  82        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  83        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  84        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  85        /* refresh       (offset 0x30 in upm ram) */
  86        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  87        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  88        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  89        /* exception     (offset 0x3C in upm ram) */
  90        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  91};
  92
  93int checkboard (void)
  94{
  95        puts ("Board: FlagaDM V3.0\n");
  96        return 0;
  97}
  98
  99phys_size_t initdram (int board_type)
 100{
 101        volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
 102        volatile memctl8xx_t *memctl = &immap->im_memctl;
 103        long int size_b0;
 104
 105        memctl->memc_or2 = CONFIG_SYS_OR2;
 106        memctl->memc_br2 = CONFIG_SYS_BR2;
 107
 108        udelay(100);
 109        upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
 110
 111        memctl->memc_mptpr = MPTPR_PTP_DIV16;
 112        memctl->memc_mamr = CONFIG_SYS_MAMR_48_SDR | MAMR_TLFA_1X;
 113
 114        /*Do the initialization of the SDRAM*/
 115        /*Start with the precharge cycle*/
 116        memctl->memc_mcr = (MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS2 | \
 117                                MCR_MLCF(1) | MCR_MAD(0x5));
 118
 119        /*Then we need two refresh cycles*/
 120        memctl->memc_mamr = CONFIG_SYS_MAMR_48_SDR | MAMR_TLFA_2X;
 121        memctl->memc_mcr = (MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS2 | \
 122                                MCR_MLCF(2) | MCR_MAD(0x30));
 123
 124        /*Mode register programming*/
 125        memctl->memc_mar = 0x00000088; /*CAS Latency = 2 and burst length = 4*/
 126        memctl->memc_mcr = (MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS2 | \
 127                                MCR_MLCF(1) | MCR_MAD(0x1C));
 128
 129        /* That should do it, just enable the periodic refresh in burst of 4*/
 130        memctl->memc_mamr = CONFIG_SYS_MAMR_48_SDR | MAMR_TLFA_4X;
 131        memctl->memc_mamr |= (MAMR_PTAE | MAMR_GPL_A4DIS);
 132
 133        size_b0 = 16*1024*1024;
 134
 135        /*
 136         * No bank 1 or 3
 137         * invalidate bank
 138         */
 139        memctl->memc_br1 = 0;
 140        memctl->memc_br3 = 0;
 141
 142        upmconfig(UPMB, (uint *)dsp_disp_table, sizeof(dsp_disp_table)/sizeof(uint));
 143
 144        memctl->memc_mbmr = MBMR_GPL_B4DIS;
 145
 146        memctl->memc_or4 = CONFIG_SYS_OR4;
 147        memctl->memc_br4 = CONFIG_SYS_BR4;
 148
 149        return (size_b0);
 150}
 151