LXR uboot/board/freescale/p2020ds/ddr.c

   1/*
   2 * Copyright 2008-2009 Freescale Semiconductor, Inc.
   3 *
   4 * This program is free software; you can redistribute it and/or
   5 * modify it under the terms of the GNU General Public License
   6 * Version 2 as published by the Free Software Foundation.
   7 */
   8
   9#include <common.h>
  10
  11#include <asm/fsl_ddr_sdram.h>
  12#include <asm/fsl_ddr_dimm_params.h>
  13
  14struct board_specific_parameters {
  15        u32 n_ranks;
  16        u32 datarate_mhz_high;
  17        u32 clk_adjust;
  18        u32 cpo;
  19        u32 write_data_delay;
  20        u32 force_2T;
  21};
  22
  23
  24/*
  25 * This table contains all valid speeds we want to override with board
  26 * specific parameters. datarate_mhz_high values need to be in ascending order
  27 * for each n_ranks group.
  28 *
  29 * ranges for parameters:
  30 *  wr_data_delay = 0-6
  31 *  clk adjust = 0-8
  32 *  cpo 2-0x1E (30)
  33 */
  34static const struct board_specific_parameters dimm0[] = {
  35        /*
  36         * memory controller 0
  37         *   num|  hi|  clk| cpo|wrdata|2T
  38         * ranks| mhz|adjst|    | delay|
  39         */
  40#ifdef CONFIG_FSL_DDR2
  41        {2,  549,    4,   0x1f,    2,  0},
  42        {2,  680,    4,   0x1f,    3,  0},
  43        {2,  850,    4,   0x1f,    4,  0},
  44        {1,  549,    4,   0x1f,    2,  0},
  45        {1,  680,    4,   0x1f,    3,  0},
  46        {1,  850,    4,   0x1f,    4,  0},
  47#else
  48        {2,  850,    6,   0x1f,    4,  0},
  49        {1,  850,    4,   0x1f,    4,  0},
  50#endif
  51        {}
  52};
  53
  54void fsl_ddr_board_options(memctl_options_t *popts,
  55                                dimm_params_t *pdimm,
  56                                unsigned int ctrl_num)
  57{
  58        const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  59        ulong ddr_freq;
  60        int i;
  61
  62        if (ctrl_num) {
  63                printf("Wrong parameter for controller number %d", ctrl_num);
  64                return;
  65        }
  66        if (!pdimm->n_ranks)
  67                return;
  68
  69        /*
  70         * set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
  71         * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
  72         * there are two dimms in the controller, set odt_rd_cfg to 3 and
  73         * odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
  74         */
  75        for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  76                popts->cs_local_opts[i].odt_rd_cfg = 0;
  77                popts->cs_local_opts[i].odt_wr_cfg = 1;
  78        }
  79
  80        pbsp = dimm0;
  81
  82        /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
  83         * freqency and n_banks specified in board_specific_parameters table.
  84         */
  85        ddr_freq = get_ddr_freq(0) / 1000000;
  86        while (pbsp->datarate_mhz_high) {
  87                if (pbsp->n_ranks == pdimm->n_ranks) {
  88                        if (ddr_freq <= pbsp->datarate_mhz_high) {
  89                                popts->clk_adjust = pbsp->clk_adjust;
  90                                popts->cpo_override = pbsp->cpo;
  91                                popts->write_data_delay =
  92                                        pbsp->write_data_delay;
  93                                popts->twoT_en = pbsp->force_2T;
  94                                goto found;
  95                        }
  96                        pbsp_highest = pbsp;
  97                }
  98                pbsp++;
  99        }
 100
 101        if (pbsp_highest) {
 102                printf("Error: board specific timing not found "
 103                        "for data rate %lu MT/s!\n"
 104                        "Trying to use the highest speed (%u) parameters\n",
 105                        ddr_freq, pbsp_highest->datarate_mhz_high);
 106                popts->clk_adjust = pbsp_highest->clk_adjust;
 107                popts->cpo_override = pbsp_highest->cpo;
 108                popts->write_data_delay = pbsp_highest->write_data_delay;
 109                popts->twoT_en = pbsp_highest->force_2T;
 110        } else {
 111                panic("DIMM is not supported by this board");
 112        }
 113
 114found:
 115        /*
 116         * Factors to consider for half-strength driver enable:
 117         *      - number of DIMMs installed
 118         */
 119        popts->half_strength_driver_enable = 0;
 120        popts->wrlvl_en = 1;
 121        /* Write leveling override */
 122        popts->wrlvl_override = 1;
 123        popts->wrlvl_sample = 0xa;
 124        popts->wrlvl_start = 0x8;
 125        /* Rtt and Rtt_WR override */
 126        popts->rtt_override = 1;
 127        popts->rtt_override_value = DDR3_RTT_120_OHM;
 128        popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */
 129}
 130