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23#include <common.h>
24#include <command.h>
25#include <i2c.h>
26#include <netdev.h>
27#include <linux/compiler.h>
28#include <asm/mmu.h>
29#include <asm/processor.h>
30#include <asm/cache.h>
31#include <asm/immap_85xx.h>
32#include <asm/fsl_law.h>
33#include <asm/fsl_serdes.h>
34#include <asm/fsl_portals.h>
35#include <asm/fsl_liodn.h>
36#include <fm_eth.h>
37
38#include "../common/qixis.h"
39#include "../common/vsc3316_3308.h"
40#include "t4qds.h"
41#include "t4240qds_qixis.h"
42
43DECLARE_GLOBAL_DATA_PTR;
44
45int checkboard(void)
46{
47 u8 sw;
48 struct cpu_type *cpu = gd->cpu;
49 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
50 unsigned int i;
51
52 printf("Board: %sQDS, ", cpu->name);
53 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
54 QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver));
55
56 sw = QIXIS_READ(brdcfg[0]);
57 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
58
59 if (sw < 0x8)
60 printf("vBank: %d\n", sw);
61 else if (sw == 0x8)
62 puts("Promjet\n");
63 else if (sw == 0x9)
64 puts("NAND\n");
65 else
66 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
67
68
69
70
71 puts("Reset Configuration Word (RCW):");
72 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
73 u32 rcw = in_be32(&gur->rcwsr[i]);
74
75 if ((i % 4) == 0)
76 printf("\n %08x:", i * 4);
77 printf(" %08x", rcw);
78 }
79 puts("\n");
80
81
82
83
84
85
86
87
88
89 puts("SERDES Reference Clocks: ");
90 sw = QIXIS_READ(brdcfg[2]);
91 for (i = 0; i < MAX_SERDES; i++) {
92 static const char *freq[] = {
93 "100", "125", "156.25", "161.1328125"};
94 unsigned int clock = (sw >> (2 * i)) & 3;
95
96 printf("SERDES%u=%sMHz ", i+1, freq[clock]);
97 }
98 puts("\n");
99
100 return 0;
101}
102
103int select_i2c_ch_pca9547(u8 ch)
104{
105 int ret;
106
107 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
108 if (ret) {
109 puts("PCA: failed to select proper channel\n");
110 return ret;
111 }
112
113 return 0;
114}
115
116
117int config_frontside_crossbar_vsc3316(void)
118{
119 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
120 u32 srds_prtcl_s1, srds_prtcl_s2;
121 int ret;
122
123 ret = select_i2c_ch_pca9547(I2C_MUX_CH_VSC3316_FS);
124 if (ret)
125 return ret;
126
127 srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
128 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
129 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
130 if (srds_prtcl_s1) {
131 ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm1_tx, 8);
132 if (ret)
133 return ret;
134 ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm1_rx, 8);
135 if (ret)
136 return ret;
137 }
138
139 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
140 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
141 srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
142 if (srds_prtcl_s2) {
143 ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm2_tx, 8);
144 if (ret)
145 return ret;
146 ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm2_rx, 8);
147 if (ret)
148 return ret;
149 }
150
151 return 0;
152}
153
154int config_backside_crossbar_mux(void)
155{
156 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
157 u32 srds_prtcl_s3, srds_prtcl_s4;
158 u8 brdcfg;
159
160 srds_prtcl_s3 = in_be32(&gur->rcwsr[4]) &
161 FSL_CORENET2_RCWSR4_SRDS3_PRTCL;
162 srds_prtcl_s3 >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT;
163 switch (srds_prtcl_s3) {
164 case 0:
165
166 break;
167 case 2:
168 case 9:
169 case 10:
170
171 brdcfg = QIXIS_READ(brdcfg[12]);
172 brdcfg &= ~BRDCFG12_SD3MX_MASK;
173 brdcfg |= BRDCFG12_SD3MX_SLOT5;
174 QIXIS_WRITE(brdcfg[12], brdcfg);
175 break;
176 case 4:
177 case 6:
178 case 8:
179 case 12:
180 case 14:
181 case 16:
182 case 17:
183 case 19:
184 case 20:
185
186 brdcfg = QIXIS_READ(brdcfg[12]);
187 brdcfg &= ~BRDCFG12_SD3MX_MASK;
188 brdcfg |= BRDCFG12_SD3MX_SLOT6;
189 QIXIS_WRITE(brdcfg[12], brdcfg);
190 break;
191 default:
192 printf("WARNING: unsupported for SerDes3 Protocol %d\n",
193 srds_prtcl_s3);
194 return -1;
195 }
196
197 srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) &
198 FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
199 srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
200 switch (srds_prtcl_s4) {
201 case 0:
202
203 break;
204 case 2:
205
206 brdcfg = QIXIS_READ(brdcfg[12]);
207 brdcfg &= ~BRDCFG12_SD4MX_MASK;
208 brdcfg |= BRDCFG12_SD4MX_SLOT7;
209 QIXIS_WRITE(brdcfg[12], brdcfg);
210 break;
211 case 4:
212 case 6:
213 case 8:
214
215 brdcfg = QIXIS_READ(brdcfg[12]);
216 brdcfg &= ~BRDCFG12_SD4MX_MASK;
217 brdcfg |= BRDCFG12_SD4MX_SLOT8;
218 QIXIS_WRITE(brdcfg[12], brdcfg);
219 break;
220 case 10:
221 case 12:
222 case 14:
223 case 16:
224 case 18:
225
226 brdcfg = QIXIS_READ(brdcfg[12]);
227 brdcfg &= ~BRDCFG12_SD4MX_MASK;
228 brdcfg |= BRDCFG12_SD4MX_AURO_SATA;
229 QIXIS_WRITE(brdcfg[12], brdcfg);
230 break;
231 default:
232 printf("WARNING: unsupported for SerDes4 Protocol %d\n",
233 srds_prtcl_s4);
234 return -1;
235 }
236
237 return 0;
238}
239
240int board_early_init_r(void)
241{
242 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
243 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
244
245
246
247
248
249
250
251 flush_dcache();
252 invalidate_icache();
253
254
255 disable_tlb(flash_esel);
256
257 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
258 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
259 0, flash_esel, BOOKE_PAGESZ_256M, 1);
260
261 set_liodns();
262#ifdef CONFIG_SYS_DPAA_QBMAN
263 setup_portals();
264#endif
265
266
267 QIXIS_WRITE(brdcfg[5], BRDCFG5_RESET);
268
269
270 config_frontside_crossbar_vsc3316();
271 config_backside_crossbar_mux();
272 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
273
274 return 0;
275}
276
277unsigned long get_board_sys_clk(void)
278{
279 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
280
281 switch (sysclk_conf & 0x0F) {
282 case QIXIS_SYSCLK_83:
283 return 83333333;
284 case QIXIS_SYSCLK_100:
285 return 100000000;
286 case QIXIS_SYSCLK_125:
287 return 125000000;
288 case QIXIS_SYSCLK_133:
289 return 133333333;
290 case QIXIS_SYSCLK_150:
291 return 150000000;
292 case QIXIS_SYSCLK_160:
293 return 160000000;
294 case QIXIS_SYSCLK_166:
295 return 166666666;
296 }
297 return 66666666;
298}
299
300unsigned long get_board_ddr_clk(void)
301{
302 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
303
304 switch ((ddrclk_conf & 0x30) >> 4) {
305 case QIXIS_DDRCLK_100:
306 return 100000000;
307 case QIXIS_DDRCLK_125:
308 return 125000000;
309 case QIXIS_DDRCLK_133:
310 return 133333333;
311 }
312 return 66666666;
313}
314
315static const char *serdes_clock_to_string(u32 clock)
316{
317 switch (clock) {
318 case SRDS_PLLCR0_RFCK_SEL_100:
319 return "100";
320 case SRDS_PLLCR0_RFCK_SEL_125:
321 return "125";
322 case SRDS_PLLCR0_RFCK_SEL_156_25:
323 return "156.25";
324 case SRDS_PLLCR0_RFCK_SEL_161_13:
325 return "161.1328125";
326 default:
327 return "???";
328 }
329}
330
331int misc_init_r(void)
332{
333 u8 sw;
334 serdes_corenet_t *srds_regs =
335 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
336 u32 actual[MAX_SERDES];
337 unsigned int i;
338
339 sw = QIXIS_READ(brdcfg[2]);
340 for (i = 0; i < MAX_SERDES; i++) {
341 unsigned int clock = (sw >> (2 * i)) & 3;
342 switch (clock) {
343 case 0:
344 actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
345 break;
346 case 1:
347 actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
348 break;
349 case 2:
350 actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
351 break;
352 case 3:
353 actual[i] = SRDS_PLLCR0_RFCK_SEL_161_13;
354 break;
355 }
356 }
357
358 for (i = 0; i < MAX_SERDES; i++) {
359 u32 pllcr0 = srds_regs->bank[i].pllcr0;
360 u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
361 if (expected != actual[i]) {
362 printf("Warning: SERDES%u expects reference clock"
363 " %sMHz, but actual is %sMHz\n", i + 1,
364 serdes_clock_to_string(expected),
365 serdes_clock_to_string(actual[i]));
366 }
367 }
368
369 return 0;
370}
371
372void ft_board_setup(void *blob, bd_t *bd)
373{
374 phys_addr_t base;
375 phys_size_t size;
376
377 ft_cpu_setup(blob, bd);
378
379 base = getenv_bootm_low();
380 size = getenv_bootm_size();
381
382 fdt_fixup_memory(blob, (u64)base, (u64)size);
383
384#ifdef CONFIG_PCI
385 pci_of_setup(blob, bd);
386#endif
387
388 fdt_fixup_liodn(blob);
389 fdt_fixup_dr_usb(blob, bd);
390
391#ifdef CONFIG_SYS_DPAA_FMAN
392 fdt_fixup_fman_ethernet(blob);
393 fdt_fixup_board_enet(blob);
394#endif
395}
396
