LXR uboot/board/mx1ads/mx1ads.c

   1/*
   2 * board/mx1ads/mx1ads.c
   3 *
   4 * (c) Copyright 2004
   5 * Techware Information Technology, Inc.
   6 * http://www.techware.com.tw/
   7 *
   8 * Ming-Len Wu <minglen_wu@techware.com.tw>
   9 *
  10 * This program is free software; you can redistribute it and/or
  11 * modify it under the terms of the GNU General Public License as
  12 * published by the Free Software Foundation; either version 2 of
  13 * the License, or (at your option) any later version.
  14 *
  15 * This program is distributed in the hope that it will be useful,
  16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18 * GNU General Public License for more details.
  19 *
  20 * You should have received a copy of the GNU General Public License
  21 * along with this program; if not, write to the Free Software
  22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23 * MA 02111-1307 USA
  24 */
  25
  26#include <common.h>
  27#include <netdev.h>
  28/*#include <mc9328.h>*/
  29#include <asm/arch/imx-regs.h>
  30#include <asm/io.h>
  31
  32DECLARE_GLOBAL_DATA_PTR;
  33
  34#define FCLK_SPEED 1
  35
  36#if FCLK_SPEED==0               /* Fout = 203MHz, Fin = 12MHz for Audio */
  37#define M_MDIV  0xC3
  38#define M_PDIV  0x4
  39#define M_SDIV  0x1
  40#elif FCLK_SPEED==1             /* Fout = 202.8MHz */
  41#define M_MDIV  0xA1
  42#define M_PDIV  0x3
  43#define M_SDIV  0x1
  44#endif
  45
  46#define USB_CLOCK 1
  47
  48#if USB_CLOCK==0
  49#define U_M_MDIV        0xA1
  50#define U_M_PDIV        0x3
  51#define U_M_SDIV        0x1
  52#elif USB_CLOCK==1
  53#define U_M_MDIV        0x48
  54#define U_M_PDIV        0x3
  55#define U_M_SDIV        0x2
  56#endif
  57
  58#if 0
  59
  60static inline void delay (unsigned long loops)
  61{
  62        __asm__ volatile ("1:\n"
  63                          "subs %0, %1, #1\n"
  64                          "bne 1b":"=r" (loops):"0" (loops));
  65}
  66
  67#endif
  68
  69/*
  70 * Miscellaneous platform dependent initialisations
  71 */
  72
  73void SetAsynchMode (void)
  74{
  75        __asm__ ("mrc p15,0,r0,c1,c0,0 \n"
  76                 "mov r2, #0xC0000000 \n"
  77                 "orr r0,r2,r0 \n" "mcr p15,0,r0,c1,c0,0 \n");
  78}
  79
  80static u32 mc9328sid;
  81
  82int board_early_init_f(void)
  83{
  84        mc9328sid = SIDR;
  85
  86        GPCR = 0x000003AB;      /* I/O pad driving strength     */
  87
  88        /*      MX1_CS1U        = 0x00000A00;   */ /* SRAM initialization          */
  89/*      MX1_CS1L        = 0x11110601;   */
  90
  91        MPCTL0 = 0x04632410;    /* setting for 150 MHz MCU PLL CLK      */
  92
  93/* set FCLK divider 1 (i.e. FCLK to MCU PLL CLK) and
  94 * BCLK divider to 2 (i.e. BCLK to 48 MHz)
  95 */
  96        CSCR = 0xAF000403;
  97
  98        CSCR |= 0x00200000;     /* Trigger the restart bit(bit 21)      */
  99        CSCR &= 0xFFFF7FFF;     /* Program PRESC bit(bit 15) to 0 to divide-by-1 */
 100
 101/* setup cs4 for cs8900 ethernet */
 102
 103        CS4U = 0x00000F00;      /* Initialize CS4 for CS8900 ethernet   */
 104        CS4L = 0x00001501;
 105
 106        GIUS (0) &= 0xFF3FFFFF;
 107        GPR (0) &= 0xFF3FFFFF;
 108
 109        readl(0x1500000C);
 110        readl(0x1500000C);
 111
 112        SetAsynchMode ();
 113
 114        icache_enable ();
 115        dcache_enable ();
 116
 117/* set PERCLKs                          */
 118        PCDR = 0x00000055;      /* set PERCLKS                          */
 119
 120/* PERCLK3 is only used by SSI so the SSI driver can set it any value it likes
 121 * PERCLK1 and PERCLK2 are shared so DO NOT change it in any other place
 122 * all sources selected as normal interrupt
 123 */
 124
 125/*      MX1_INTTYPEH = 0;
 126        MX1_INTTYPEL = 0;
 127*/
 128        return 0;
 129}
 130
 131int board_init(void)
 132{
 133        gd->bd->bi_arch_number = MACH_TYPE_MX1ADS;
 134
 135        gd->bd->bi_boot_params = 0x08000100;    /* adress of boot parameters */
 136
 137        return 0;
 138}
 139
 140int board_late_init (void)
 141{
 142
 143        setenv ("stdout", "serial");
 144        setenv ("stderr", "serial");
 145
 146        switch (mc9328sid) {
 147        case 0x0005901d:
 148                printf ("MX1ADS board with MC9328 MX1 (0L44N), Silicon ID 0x%08x \n\n",
 149                        mc9328sid);
 150                break;
 151        case 0x04d4c01d:
 152                printf ("MX1ADS board with MC9328 MXL (1L45N), Silicon ID 0x%08x \n\n",
 153                        mc9328sid);
 154                break;
 155        case 0x00d4c01d:
 156                printf ("MX1ADS board with MC9328 MXL (2L45N), Silicon ID 0x%08x \n\n",
 157                        mc9328sid);
 158                break;
 159
 160        default:
 161                printf ("MX1ADS board with UNKNOWN MC9328 cpu, Silicon ID 0x%08x \n",
 162                        mc9328sid);
 163                break;
 164        }
 165        return 0;
 166}
 167
 168int dram_init(void)
 169{
 170        /* dram_init must store complete ramsize in gd->ram_size */
 171        gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
 172                                PHYS_SDRAM_1_SIZE);
 173        return 0;
 174}
 175
 176void dram_init_banksize(void)
 177{
 178        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 179        gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 180}
 181
 182#ifdef CONFIG_CMD_NET
 183int board_eth_init(bd_t *bis)
 184{
 185        int rc = 0;
 186#ifdef CONFIG_CS8900
 187        rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
 188#endif
 189        return rc;
 190}
 191#endif
 192