LXR uboot/board/sandpoint/early

   1/*
   2 * (C) Copyright 2001
   3 * Thomas Koeller, tkoeller@gmx.net
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24#ifndef __ASSEMBLY__
  25#define __ASSEMBLY__    1
  26#endif
  27
  28#include <asm-offsets.h>
  29#include <config.h>
  30#include <asm/processor.h>
  31#include <mpc824x.h>
  32#include <ppc_asm.tmpl>
  33
  34#if defined(USE_DINK32)
  35  /* We are running from RAM, so do not clear the MCCR1_MEMGO bit! */
  36  #define MCCR1VAL ((CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT) | MCCR1_MEMGO)
  37#else
  38  #define MCCR1VAL (CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT)
  39#endif
  40
  41        .text
  42
  43        /* Values to program into memory controller registers */
  44tbl:    .long   MCCR1, MCCR1VAL
  45        .long   MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT
  46        .long   MCCR3
  47        .long   (((CONFIG_SYS_BSTOPRE & 0x000000f0) >> 4) << MCCR3_BSTOPRE2TO5_SHIFT) | \
  48                (CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT) | \
  49                (CONFIG_SYS_RDLAT  << MCCR3_RDLAT_SHIFT)
  50        .long   MCCR4
  51        .long   (CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) | (CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | \
  52                (CONFIG_SYS_REGISTERD_TYPE_BUFFER << 20) | \
  53                (((CONFIG_SYS_BSTOPRE & 0x00000300) >> 8) << MCCR4_BSTOPRE0TO1_SHIFT ) | \
  54                ((CONFIG_SYS_SDMODE_CAS_LAT << 4) | (CONFIG_SYS_SDMODE_WRAP << 3) | \
  55                (CONFIG_SYS_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) | \
  56                (CONFIG_SYS_ACTTORW << MCCR4_ACTTORW_SHIFT) | \
  57                ((CONFIG_SYS_BSTOPRE & 0x0000000f) << MCCR4_BSTOPRE6TO9_SHIFT )
  58        .long   MSAR1
  59        .long   (((CONFIG_SYS_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
  60                (((CONFIG_SYS_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
  61                (((CONFIG_SYS_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
  62                (((CONFIG_SYS_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
  63        .long   EMSAR1
  64        .long   (((CONFIG_SYS_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
  65                (((CONFIG_SYS_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
  66                (((CONFIG_SYS_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
  67                (((CONFIG_SYS_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
  68        .long   MSAR2
  69        .long   (((CONFIG_SYS_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
  70                (((CONFIG_SYS_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
  71                (((CONFIG_SYS_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
  72                (((CONFIG_SYS_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
  73        .long   EMSAR2
  74        .long   (((CONFIG_SYS_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
  75                (((CONFIG_SYS_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
  76                (((CONFIG_SYS_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
  77                (((CONFIG_SYS_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
  78        .long   MEAR1
  79        .long   (((CONFIG_SYS_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
  80                (((CONFIG_SYS_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
  81                (((CONFIG_SYS_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
  82                (((CONFIG_SYS_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
  83        .long   EMEAR1
  84        .long   (((CONFIG_SYS_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
  85                (((CONFIG_SYS_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
  86                (((CONFIG_SYS_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
  87                (((CONFIG_SYS_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
  88        .long   MEAR2
  89        .long   (((CONFIG_SYS_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
  90                (((CONFIG_SYS_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
  91                (((CONFIG_SYS_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
  92                (((CONFIG_SYS_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
  93        .long   EMEAR2
  94        .long   (((CONFIG_SYS_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
  95                (((CONFIG_SYS_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
  96                (((CONFIG_SYS_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
  97                (((CONFIG_SYS_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
  98        .long   0
  99
 100
 101        /*
 102         * Early CPU initialization. Set up memory controller, so we can access any RAM at all. This
 103         * must be done in assembly, since we have no stack at this point.
 104         */
 105        .global early_init_f
 106early_init_f:
 107        mflr    r10
 108
 109        /* basic memory controller configuration */
 110        lis     r3, CONFIG_ADDR_HIGH
 111        lis     r4, CONFIG_DATA_HIGH
 112        bl      lab
 113lab:    mflr    r5
 114        lwzu    r0, tbl - lab(r5)
 115loop:   lwz     r1, 4(r5)
 116        stwbrx  r0, 0, r3
 117        eieio
 118        stwbrx  r1, 0, r4
 119        eieio
 120        lwzu    r0, 8(r5)
 121        cmpli   cr0, 0, r0, 0
 122        bne     cr0, loop
 123
 124        /* set bank enable bits */
 125        lis     r0, MBER@h
 126        ori     r0, 0, MBER@l
 127        li      r1, CONFIG_SYS_BANK_ENABLE
 128        stwbrx  r0, 0, r3
 129        eieio
 130        stb     r1, 0(r4)
 131        eieio
 132
 133        /* delay loop */
 134        lis     r0, 0x0003
 135        mtctr   r0
 136delay:  bdnz    delay
 137
 138        /* enable memory controller */
 139        lis     r0, MCCR1@h
 140        ori     r0, 0, MCCR1@l
 141        stwbrx  r0, 0, r3
 142        eieio
 143        lwbrx   r0, 0, r4
 144        oris    r0, 0, MCCR1_MEMGO@h
 145        stwbrx  r0, 0, r4
 146        eieio
 147
 148        /* set up stack pointer */
 149        lis     r1, CONFIG_SYS_INIT_SP_OFFSET@h
 150        ori     r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l
 151
 152        mtlr    r10
 153        blr
 154