LXR uboot/board/scb9328/lowlevel

   1/*
   2 * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH
   3 *
   4 * This program is free software; you can redistribute it and/or
   5 * modify it under the terms of the GNU General Public License
   6 * as published by the Free Software Foundation; either version 2
   7 * of the License, or (at your option) any later version.
   8 *
   9 * This program is distributed in the hope that it will be useful,
  10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12 * GNU General Public License for more details.
  13 *
  14 * You should have received a copy of the GNU General Public License
  15 * along with this program; if not, write to the Free Software
  16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
  17 * 02111-1307, USA.
  18 *
  19 */
  20
  21#include <config.h>
  22#include <version.h>
  23#include <asm/arch/imx-regs.h>
  24
  25.globl lowlevel_init
  26lowlevel_init:
  27
  28        mov     r10, lr
  29
  30/* Change PERCLK1DIV to 14 ie 14+1 */
  31        ldr             r0,     =PCDR
  32        ldr             r1,     =CONFIG_SYS_PCDR_VAL
  33        str             r1,   [r0]
  34
  35/* set MCU PLL Control Register 0 */
  36
  37        ldr             r0,     =MPCTL0
  38        ldr             r1,     =CONFIG_SYS_MPCTL0_VAL
  39        str             r1,   [r0]
  40
  41/* set mpll restart bit */
  42        ldr             r0, =CSCR
  43        ldr             r1, [r0]
  44        orr             r1,r1,#(1<<21)
  45        str             r1, [r0]
  46
  47        mov             r2,#0x10
  481:
  49        mov             r3,#0x2000
  502:
  51        subs    r3,r3,#1
  52        bne             2b
  53
  54        subs    r2,r2,#1
  55        bne             1b
  56
  57/* set System PLL Control Register 0 */
  58
  59        ldr             r0,     =SPCTL0
  60        ldr             r1,     =CONFIG_SYS_SPCTL0_VAL
  61        str             r1,   [r0]
  62
  63/* set spll restart bit */
  64        ldr             r0, =CSCR
  65        ldr             r1, [r0]
  66        orr             r1,r1,#(1<<22)
  67        str             r1, [r0]
  68
  69        mov             r2,#0x10
  701:
  71        mov             r3,#0x2000
  722:
  73        subs    r3,r3,#1
  74        bne             2b
  75
  76        subs    r2,r2,#1
  77        bne             1b
  78
  79        ldr             r0,   =CSCR
  80        ldr             r1,   =CONFIG_SYS_CSCR_VAL
  81        str             r1,   [r0]
  82
  83/* I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon
  84 *this.....
  85 *
  86 * It would appear that from a Cold-Boot the ARM920T enters "FastBus" mode CP15
  87 * register 1, this stops it using the output of the PLL and thus runs at the
  88 * slow rate. Unless you place the Core into "Asynch" mode, the CPU will never
  89 * use the value set in the CM_OSC registers...regardless of what you set it
  90 * too!  Thus, although i thought i was running at 140MHz, i'm actually running
  91 * at 40!..
  92
  93 * Slapping this into my bootloader does the trick...
  94
  95 * MRC p15,0,r0,c1,c0,0    ; read core configuration register
  96 * ORR r0,r0,#0xC0000000   ; set asynchronous clocks and not fastbus mode
  97 * MCR p15,0,r0,c1,c0,0    ; write modified value to core configuration
  98 * register
  99 */
 100        MRC p15,0,r0,c1,c0,0
 101        ORR r0,r0,#0xC0000000
 102        MCR p15,0,r0,c1,c0,0
 103
 104        ldr             r0,     =GPR(0)
 105        ldr             r1,     =CONFIG_SYS_GPR_A_VAL
 106        str             r1,   [r0]
 107
 108        ldr             r0,     =GIUS(0)
 109        ldr             r1,     =CONFIG_SYS_GIUS_A_VAL
 110        str             r1,   [r0]
 111
 112/* CS3 becomes CS3 by clearing reset default bit 1 in FMCR */
 113
 114        ldr             r0,     =FMCR
 115        ldr             r1,     =CONFIG_SYS_FMCR_VAL
 116        str             r1,   [r0]
 117
 118        ldr             r0,     =CS0U
 119        ldr             r1,     =CONFIG_SYS_CS0U_VAL
 120        str             r1,   [r0]
 121
 122        ldr             r0,     =CS0L
 123        ldr             r1,     =CONFIG_SYS_CS0L_VAL
 124        str             r1,   [r0]
 125
 126        ldr             r0,     =CS1U
 127        ldr             r1,     =CONFIG_SYS_CS1U_VAL
 128        str             r1,   [r0]
 129
 130        ldr             r0,     =CS1L
 131        ldr             r1,     =CONFIG_SYS_CS1L_VAL
 132        str             r1,   [r0]
 133
 134        ldr             r0,     =CS2U
 135        ldr             r1,     =CONFIG_SYS_CS2U_VAL
 136        str             r1,   [r0]
 137
 138        ldr             r0,     =CS2L
 139        ldr             r1,     =CONFIG_SYS_CS2L_VAL
 140        str             r1,   [r0]
 141
 142        ldr             r0,     =CS3U
 143        ldr             r1,     =CONFIG_SYS_CS3U_VAL
 144        str             r1,   [r0]
 145
 146        ldr             r0,     =CS3L
 147        ldr             r1,     =CONFIG_SYS_CS3L_VAL
 148        str             r1,   [r0]
 149
 150        ldr             r0,     =CS4U
 151        ldr             r1,     =CONFIG_SYS_CS4U_VAL
 152        str             r1,   [r0]
 153
 154        ldr             r0,     =CS4L
 155        ldr             r1,     =CONFIG_SYS_CS4L_VAL
 156        str             r1,   [r0]
 157
 158        ldr             r0,     =CS5U
 159        ldr             r1,     =CONFIG_SYS_CS5U_VAL
 160        str             r1,   [r0]
 161
 162        ldr             r0,     =CS5L
 163        ldr             r1,     =CONFIG_SYS_CS5L_VAL
 164        str             r1,   [r0]
 165
 166/* SDRAM Setup */
 167
 168        ldr             r0, =SDCTL0
 169        ldr             r1, =PRECHARGE_CMD
 170        str             r1,   [r0]
 171
 172        ldr             r0, =0x08200000
 173        ldr             r1, =0x0 /* Issue Precharge all Command */
 174        str             r1,   [r0]
 175
 176        ldr             r0, =SDCTL0
 177        ldr             r1, =AUTOREFRESH_CMD
 178        str             r1,   [r0]
 179
 180        ldr             r0, =0x08000000
 181        ldr             r1, =0x0 /* Issue AutoRefresh Command */
 182        str             r1,   [r0]
 183        str             r1,   [r0]
 184        str             r1,   [r0]
 185        str             r1,   [r0]
 186        str             r1,   [r0]
 187        str             r1,   [r0]
 188        str             r1,   [r0]
 189        str             r1,   [r0]
 190
 191        ldr             r0, =SDCTL0
 192        ldr             r1, =0xb10a8300
 193        str             r1,   [r0]
 194
 195        ldr             r0, =0x08223000 /* CAS Latency 2 */
 196        ldr             r1, =0x0   /* Issue Mode Register Command, Burst Length = 8 */
 197        str             r1,   [r0]
 198
 199        ldr             r0, =SDCTL0
 200        ldr             r1, =0x810a8200 /* Set to Normal Mode CAS 2 */
 201        str             r1,   [r0]
 202
 203        mov     pc,r10
 204