LXR uboot/board/v37/v37.c

   1/*
   2 * (C) Copyright 2003
   3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24/*
  25 * Yoo. Jonghoon, IPone, yooth@ipone.co.kr
  26 * U-Boot port on RPXlite board
  27 *
  28 * DRAM related UPMA register values are modified.
  29 * See RPXLite engineering note : 50MHz/60ns - UPM RAM WORDS
  30 */
  31
  32#include <common.h>
  33#include "mpc8xx.h"
  34
  35/* ------------------------------------------------------------------------- */
  36
  37static long int dram_size (void);
  38
  39/* ------------------------------------------------------------------------- */
  40
  41#define MBYTE           (1024*1024)
  42#define DRAM_DELAY      0x00000379  /* DRAM delay count */
  43#define _NOT_USED_      0xFFFFCC25
  44
  45const uint sdram_table[] =
  46{
  47        /*  single read. (offset 0 in upm RAM) */
  48        0x1F07D004, 0xEEAEE004, 0x11ADD004, 0xEFBBA000,
  49        0x1FF75447, 0x1FF77C34, 0xEFEABC34, 0x1FB57C35,
  50
  51        /* burst read. (Offset 8 in upm RAM)   */
  52        0x1F07D004, 0xEEAEE004, 0x00ADC004, 0x00AFC000,
  53        0x00AFC000, 0x01AFC000, 0x0FBB8000, 0x1FF75447,
  54        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  55        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  56
  57        /* single write. (Offset 0x18 in upm RAM) */
  58        0x1F27D004, 0xEEAEA000, 0x01B90004, 0x1FF75447,
  59        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  60
  61        /*  burst write. (Offset 0x20 in upm RAM) */
  62        0x1F07D004, 0xEEAEA000, 0x00AD4000, 0x00AFC000,
  63        0x00AFC000, 0x01BB8004, 0x1FF75447, 0xFFFFFFFF,
  64        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  65        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  66
  67        /* Refresh cycle, offset 0x30 */
  68        0x1FF5DC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
  69        0xFFFFFC84, 0xFFFFFC07, 0xFFFFFFFF, 0xFFFFFFFF,
  70        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  71
  72        /* Exception, 0ffset 0x3C */
  73        0x7FFFFC07, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  74};
  75/* ------------------------------------------------------------------------- */
  76
  77
  78/*
  79 * Check Board Identity:
  80 *
  81 * Return 1 for now.
  82 *
  83 */
  84
  85int checkboard (void)
  86{
  87        printf("Marel V37\n") ;
  88        return (0) ;
  89}
  90
  91/* ------------------------------------------------------------------------- */
  92
  93phys_size_t initdram (int board_type)
  94{
  95    volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
  96    volatile memctl8xx_t *memctl = &immap->im_memctl;
  97    unsigned long temp;
  98    volatile int delay_cnt;
  99    long int ramsize;
 100
 101    ramsize = dram_size();
 102
 103        /* Refresh clock prescalar */
 104    memctl->memc_mptpr = 0x400 ;
 105
 106    if( ramsize == 32*MBYTE )
 107       temp = 0xd0904110;
 108   else                         /* 16MB */
 109       temp = 0xd0802110;
 110
 111    memctl->memc_mbmr = temp;
 112
 113    upmconfig(UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
 114
 115        /* Map controller banks 2 to the SDRAM bank */
 116    memctl->memc_or2 = 0xA00 | (0 - ramsize);
 117    memctl->memc_br2 = 0xC1;
 118
 119    memctl->memc_mbmr = temp | 0x08;
 120    memctl->memc_mcr  = 0x80804130;
 121
 122    delay_cnt = 0;
 123    while( delay_cnt++ < DRAM_DELAY )
 124        ;
 125
 126    /* Run MRS command in location 5-8 of UPMB */
 127
 128    memctl->memc_mbmr = temp | 0x04;
 129    memctl->memc_mar  = 0x88;
 130
 131    memctl->memc_mcr  = 0x80804105;
 132
 133    delay_cnt = 0;
 134    while( delay_cnt++ < DRAM_DELAY )
 135        ;
 136
 137#ifdef  CONFIG_CAN_DRIVER
 138    /* Initialize OR3 / BR3 */
 139    memctl->memc_or3 = CONFIG_SYS_OR3_CAN;
 140    memctl->memc_br3 = CONFIG_SYS_BR3_CAN;
 141
 142    /* Initialize MBMR */
 143    memctl->memc_mamr = MAMR_GPL_A4DIS; /* GPL_A4 ouput line Disable */
 144
 145    /* Initialize UPMB for CAN: single read */
 146    memctl->memc_mdr = 0xFFFFC004;
 147    memctl->memc_mcr = 0x0100 | UPMA;
 148
 149    memctl->memc_mdr = 0x0FFFD004;
 150    memctl->memc_mcr = 0x0101 | UPMA;
 151
 152    memctl->memc_mdr = 0x0FFFC000;
 153    memctl->memc_mcr = 0x0102 | UPMA;
 154
 155    memctl->memc_mdr = 0x3FFFC004;
 156    memctl->memc_mcr = 0x0103 | UPMA;
 157
 158    memctl->memc_mdr = 0xFFFFDC05;
 159    memctl->memc_mcr = 0x0104 | UPMA;
 160
 161    /* Initialize UPMB for CAN: single write */
 162    memctl->memc_mdr = 0xFFFCC004;
 163    memctl->memc_mcr = 0x0118 | UPMA;
 164
 165    memctl->memc_mdr = 0xCFFCD004;
 166    memctl->memc_mcr = 0x0119 | UPMA;
 167
 168    memctl->memc_mdr = 0x0FFCC000;
 169    memctl->memc_mcr = 0x011A | UPMA;
 170
 171    memctl->memc_mdr = 0x7FFCC004;
 172    memctl->memc_mcr = 0x011B | UPMA;
 173
 174    memctl->memc_mdr = 0xFFFDCC05;
 175    memctl->memc_mcr = 0x011C | UPMA;
 176#endif  /* CONFIG_CAN_DRIVER */
 177
 178    return (dram_size());
 179}
 180
 181/* ------------------------------------------------------------------------- */
 182
 183/*
 184 * Find size of RAM from configuration pins.
 185 * The input pins that contain the memory size are also the debug port
 186 * pins.  Normally they are configured as debug port pins.  To be able
 187 * to read the memory configuration, we must deactivate the debug port
 188 * and enable the pcmcia input pins.  Then return the register to
 189 * previous state.
 190 */
 191
 192static long int dram_size ()
 193{
 194    volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
 195    volatile sysconf8xx_t *siu = &immap->im_siu_conf;
 196    volatile pcmconf8xx_t *pcm = &immap->im_pcmcia;
 197    long int              i, memory=1;
 198    unsigned long siu_mcr;
 199
 200    siu_mcr = siu->sc_siumcr;
 201    siu->sc_siumcr = siu_mcr & 0xFF9FFFFF;
 202    for(i=0; i<10; i++) i = i;
 203
 204    memory = (pcm->pcmc_pipr>>12) & 0x3;
 205
 206    siu->sc_siumcr = siu_mcr;
 207
 208    switch( memory )
 209    {
 210        case 1:
 211            return( 32*MBYTE );
 212        case 2:
 213            return( 64*MBYTE );
 214        default:
 215            break;
 216    }
 217    return( 16*MBYTE );
 218}
 219