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29#include <common.h>
30#include <net.h>
31#include <malloc.h>
32#include <miiphy.h>
33#include <netdev.h>
34#include <asm/types.h>
35#include <asm/byteorder.h>
36#include <linux/err.h>
37#include <linux/mii.h>
38#include <asm/io.h>
39#include <asm/arch/armada100.h>
40#include "armada100_fec.h"
41
42#define PHY_ADR_REQ 0xFF
43
44#ifdef DEBUG
45static int eth_dump_regs(struct eth_device *dev)
46{
47 struct armdfec_device *darmdfec = to_darmdfec(dev);
48 struct armdfec_reg *regs = darmdfec->regs;
49 unsigned int i = 0;
50
51 printf("\noffset: phy_adr, value: 0x%x\n", readl(®s->phyadr));
52 printf("offset: smi, value: 0x%x\n", readl(®s->smi));
53 for (i = 0x400; i <= 0x4e4; i += 4)
54 printf("offset: 0x%x, value: 0x%x\n",
55 i, readl(ARMD1_FEC_BASE + i));
56 return 0;
57}
58#endif
59
60static int armdfec_phy_timeout(u32 *reg, u32 flag, int cond)
61{
62 u32 timeout = PHY_WAIT_ITERATIONS;
63 u32 reg_val;
64
65 while (--timeout) {
66 reg_val = readl(reg);
67 if (cond && (reg_val & flag))
68 break;
69 else if (!cond && !(reg_val & flag))
70 break;
71 udelay(PHY_WAIT_MICRO_SECONDS);
72 }
73 return !timeout;
74}
75
76static int smi_reg_read(const char *devname, u8 phy_addr, u8 phy_reg,
77 u16 *value)
78{
79 struct eth_device *dev = eth_get_dev_by_name(devname);
80 struct armdfec_device *darmdfec = to_darmdfec(dev);
81 struct armdfec_reg *regs = darmdfec->regs;
82 u32 val;
83
84 if (phy_addr == PHY_ADR_REQ && phy_reg == PHY_ADR_REQ) {
85 val = readl(®s->phyadr);
86 *value = val & 0x1f;
87 return 0;
88 }
89
90
91 if (phy_addr > PHY_MASK) {
92 printf("ARMD100 FEC: (%s) Invalid phy address: 0x%X\n",
93 __func__, phy_addr);
94 return -EINVAL;
95 }
96 if (phy_reg > PHY_MASK) {
97 printf("ARMD100 FEC: (%s) Invalid register offset: 0x%X\n",
98 __func__, phy_reg);
99 return -EINVAL;
100 }
101
102
103 if (armdfec_phy_timeout(®s->smi, SMI_BUSY, FALSE)) {
104 printf("ARMD100 FEC: (%s) PHY busy timeout\n", __func__);
105 return -1;
106 }
107
108 writel((phy_addr << 16) | (phy_reg << 21) | SMI_OP_R, ®s->smi);
109
110
111 if (armdfec_phy_timeout(®s->smi, SMI_R_VALID, TRUE)) {
112 val = readl(®s->smi);
113 printf("ARMD100 FEC: (%s) PHY Read timeout, val=0x%x\n",
114 __func__, val);
115 return -1;
116 }
117 val = readl(®s->smi);
118 *value = val & 0xffff;
119
120 return 0;
121}
122
123static int smi_reg_write(const char *devname,
124 u8 phy_addr, u8 phy_reg, u16 value)
125{
126 struct eth_device *dev = eth_get_dev_by_name(devname);
127 struct armdfec_device *darmdfec = to_darmdfec(dev);
128 struct armdfec_reg *regs = darmdfec->regs;
129
130 if (phy_addr == PHY_ADR_REQ && phy_reg == PHY_ADR_REQ) {
131 clrsetbits_le32(®s->phyadr, 0x1f, value & 0x1f);
132 return 0;
133 }
134
135
136 if (phy_addr > PHY_MASK) {
137 printf("ARMD100 FEC: (%s) Invalid phy address\n", __func__);
138 return -EINVAL;
139 }
140 if (phy_reg > PHY_MASK) {
141 printf("ARMD100 FEC: (%s) Invalid register offset\n", __func__);
142 return -EINVAL;
143 }
144
145
146 if (armdfec_phy_timeout(®s->smi, SMI_BUSY, FALSE)) {
147 printf("ARMD100 FEC: (%s) PHY busy timeout\n", __func__);
148 return -1;
149 }
150
151 writel((phy_addr << 16) | (phy_reg << 21) | SMI_OP_W | (value & 0xffff),
152 ®s->smi);
153 return 0;
154}
155
156
157
158
159
160
161static void abortdma(struct eth_device *dev)
162{
163 struct armdfec_device *darmdfec = to_darmdfec(dev);
164 struct armdfec_reg *regs = darmdfec->regs;
165 int delay;
166 int maxretries = 40;
167 u32 tmp;
168
169 while (--maxretries) {
170 writel(SDMA_CMD_AR | SDMA_CMD_AT, ®s->sdma_cmd);
171 udelay(100);
172
173 delay = 10;
174 while (--delay) {
175 tmp = readl(®s->sdma_cmd);
176 if (!(tmp & (SDMA_CMD_AR | SDMA_CMD_AT)))
177 break;
178 udelay(10);
179 }
180 if (delay)
181 break;
182 }
183
184 if (!maxretries)
185 printf("ARMD100 FEC: (%s) DMA Stuck\n", __func__);
186}
187
188static inline u32 nibble_swapping_32_bit(u32 x)
189{
190 return ((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4);
191}
192
193static inline u32 nibble_swapping_16_bit(u32 x)
194{
195 return ((x & 0x0000f0f0) >> 4) | ((x & 0x00000f0f) << 4);
196}
197
198static inline u32 flip_4_bits(u32 x)
199{
200 return ((x & 0x01) << 3) | ((x & 0x002) << 1)
201 | ((x & 0x04) >> 1) | ((x & 0x008) >> 3);
202}
203
204
205
206
207
208
209
210
211
212
213static u32 hash_function(u32 mach, u32 macl)
214{
215 u32 hashresult;
216 u32 addrh;
217 u32 addrl;
218 u32 addr0;
219 u32 addr1;
220 u32 addr2;
221 u32 addr3;
222 u32 addrhswapped;
223 u32 addrlswapped;
224
225 addrh = nibble_swapping_16_bit(mach);
226 addrl = nibble_swapping_32_bit(macl);
227
228 addrhswapped = flip_4_bits(addrh & 0xf)
229 + ((flip_4_bits((addrh >> 4) & 0xf)) << 4)
230 + ((flip_4_bits((addrh >> 8) & 0xf)) << 8)
231 + ((flip_4_bits((addrh >> 12) & 0xf)) << 12);
232
233 addrlswapped = flip_4_bits(addrl & 0xf)
234 + ((flip_4_bits((addrl >> 4) & 0xf)) << 4)
235 + ((flip_4_bits((addrl >> 8) & 0xf)) << 8)
236 + ((flip_4_bits((addrl >> 12) & 0xf)) << 12)
237 + ((flip_4_bits((addrl >> 16) & 0xf)) << 16)
238 + ((flip_4_bits((addrl >> 20) & 0xf)) << 20)
239 + ((flip_4_bits((addrl >> 24) & 0xf)) << 24)
240 + ((flip_4_bits((addrl >> 28) & 0xf)) << 28);
241
242 addrh = addrhswapped;
243 addrl = addrlswapped;
244
245 addr0 = (addrl >> 2) & 0x03f;
246 addr1 = (addrl & 0x003) | (((addrl >> 8) & 0x7f) << 2);
247 addr2 = (addrl >> 15) & 0x1ff;
248 addr3 = ((addrl >> 24) & 0x0ff) | ((addrh & 1) << 8);
249
250 hashresult = (addr0 << 9) | (addr1 ^ addr2 ^ addr3);
251 hashresult = hashresult & 0x07ff;
252 return hashresult;
253}
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268static int add_del_hash_entry(struct armdfec_device *darmdfec, u32 mach,
269 u32 macl, u32 rd, u32 skip, int del)
270{
271 struct addr_table_entry_t *entry, *start;
272 u32 newhi;
273 u32 newlo;
274 u32 i;
275
276 newlo = (((mach >> 4) & 0xf) << 15)
277 | (((mach >> 0) & 0xf) << 11)
278 | (((mach >> 12) & 0xf) << 7)
279 | (((mach >> 8) & 0xf) << 3)
280 | (((macl >> 20) & 0x1) << 31)
281 | (((macl >> 16) & 0xf) << 27)
282 | (((macl >> 28) & 0xf) << 23)
283 | (((macl >> 24) & 0xf) << 19)
284 | (skip << HTESKIP) | (rd << HTERDBIT)
285 | HTEVALID;
286
287 newhi = (((macl >> 4) & 0xf) << 15)
288 | (((macl >> 0) & 0xf) << 11)
289 | (((macl >> 12) & 0xf) << 7)
290 | (((macl >> 8) & 0xf) << 3)
291 | (((macl >> 21) & 0x7) << 0);
292
293
294
295
296
297 start = (struct addr_table_entry_t *)(darmdfec->htpr);
298 entry = start + hash_function(mach, macl);
299 for (i = 0; i < HOP_NUMBER; i++) {
300 if (!(entry->lo & HTEVALID)) {
301 break;
302 } else {
303
304 if (((entry->lo & 0xfffffff8) == (newlo & 0xfffffff8))
305 && (entry->hi == newhi))
306 break;
307 }
308 if (entry == start + 0x7ff)
309 entry = start;
310 else
311 entry++;
312 }
313
314 if (((entry->lo & 0xfffffff8) != (newlo & 0xfffffff8)) &&
315 (entry->hi != newhi) && del)
316 return 0;
317
318 if (i == HOP_NUMBER) {
319 if (!del) {
320 printf("ARMD100 FEC: (%s) table section is full\n",
321 __func__);
322 return -ENOSPC;
323 } else {
324 return 0;
325 }
326 }
327
328
329
330
331 if (del) {
332 entry->hi = 0;
333 entry->lo = 0;
334 } else {
335 entry->hi = newhi;
336 entry->lo = newlo;
337 }
338
339 return 0;
340}
341
342
343
344
345
346
347
348
349static void update_hash_table_mac_address(struct armdfec_device *darmdfec,
350 u8 *oaddr, u8 *addr)
351{
352 u32 mach;
353 u32 macl;
354
355
356 if (oaddr) {
357 mach = (oaddr[0] << 8) | oaddr[1];
358 macl = (oaddr[2] << 24) | (oaddr[3] << 16) |
359 (oaddr[4] << 8) | oaddr[5];
360 add_del_hash_entry(darmdfec, mach, macl, 1, 0, HASH_DELETE);
361 }
362
363
364 mach = (addr[0] << 8) | addr[1];
365 macl = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5];
366 add_del_hash_entry(darmdfec, mach, macl, 1, 0, HASH_ADD);
367}
368
369
370static void init_hashtable(struct eth_device *dev)
371{
372 struct armdfec_device *darmdfec = to_darmdfec(dev);
373 struct armdfec_reg *regs = darmdfec->regs;
374 memset(darmdfec->htpr, 0, HASH_ADDR_TABLE_SIZE);
375 writel((u32)darmdfec->htpr, ®s->htpr);
376}
377
378
379
380
381
382static int ethernet_phy_detect(struct eth_device *dev)
383{
384 u32 val;
385 u16 tmp, mii_status;
386 u8 addr;
387
388 for (addr = 0; addr < 32; addr++) {
389 if (miiphy_read(dev->name, addr, MII_BMSR, &mii_status) != 0)
390
391 continue;
392
393
394 if (mii_status == 0 || mii_status == 0xffff)
395
396 continue;
397
398 if (miiphy_read(dev->name, addr, MII_PHYSID1, &tmp) != 0)
399
400 continue;
401
402 val = tmp << 16;
403 if (miiphy_read(dev->name, addr, MII_PHYSID2, &tmp) != 0)
404
405 continue;
406
407 val |= tmp;
408
409 if ((val & 0xfffffff0) != 0)
410 return addr;
411 }
412 return -1;
413}
414
415static void armdfec_init_rx_desc_ring(struct armdfec_device *darmdfec)
416{
417 struct rx_desc *p_rx_desc;
418 int i;
419
420
421 p_rx_desc = darmdfec->p_rxdesc;
422 for (i = 0; i < RINGSZ; i++) {
423 p_rx_desc->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT;
424 p_rx_desc->buf_size = PKTSIZE_ALIGN;
425 p_rx_desc->byte_cnt = 0;
426 p_rx_desc->buf_ptr = darmdfec->p_rxbuf + i * PKTSIZE_ALIGN;
427 if (i == (RINGSZ - 1)) {
428 p_rx_desc->nxtdesc_p = darmdfec->p_rxdesc;
429 } else {
430 p_rx_desc->nxtdesc_p = (struct rx_desc *)
431 ((u32)p_rx_desc + ARMDFEC_RXQ_DESC_ALIGNED_SIZE);
432 p_rx_desc = p_rx_desc->nxtdesc_p;
433 }
434 }
435 darmdfec->p_rxdesc_curr = darmdfec->p_rxdesc;
436}
437
438static int armdfec_init(struct eth_device *dev, bd_t *bd)
439{
440 struct armdfec_device *darmdfec = to_darmdfec(dev);
441 struct armdfec_reg *regs = darmdfec->regs;
442 int phy_adr;
443 u32 temp;
444
445 armdfec_init_rx_desc_ring(darmdfec);
446
447
448 writel(0, ®s->im);
449 writel(0, ®s->ic);
450
451 writel(0, ®s->iwc);
452
453
454
455
456
457 abortdma(dev);
458
459
460 init_hashtable(dev);
461
462
463 writel(SDCR_BSZ8 |
464 SDCR_RIFB |
465 SDCR_BLMT |
466 SDCR_BLMR |
467 SDCR_RC_MAX_RETRANS,
468 ®s->sdma_conf);
469
470 writel(PCR_HS, ®s->pconf);
471
472
473 writel(PCXR_2BSM |
474 PCXR_DSCP_EN |
475 PCXR_MFL_1536 |
476 PCXR_FLP |
477 PCXR_TX_HIGH_PRI,
478 ®s->pconf_ext);
479
480 update_hash_table_mac_address(darmdfec, NULL, dev->enetaddr);
481
482
483 temp = (u32)®s->txcdp[TXQ];
484 writel((u32)darmdfec->p_txdesc, temp);
485 temp = (u32)®s->rxfdp[RXQ];
486 writel((u32)darmdfec->p_rxdesc, temp);
487 temp = (u32)®s->rxcdp[RXQ];
488 writel((u32)darmdfec->p_rxdesc_curr, temp);
489
490
491 writel(ALL_INTS, ®s->im);
492
493
494 setbits_le32(®s->pconf, PCR_EN);
495
496
497 setbits_le32(®s->sdma_cmd, SDMA_CMD_ERD);
498
499#ifdef DEBUG
500 eth_dump_regs(dev);
501#endif
502
503#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
504
505#if defined(CONFIG_PHY_BASE_ADR)
506 miiphy_write(dev->name, PHY_ADR_REQ, PHY_ADR_REQ, CONFIG_PHY_BASE_ADR);
507#else
508
509 phy_adr = ethernet_phy_detect(dev);
510 if (phy_adr < 0) {
511 printf("ARMD100 FEC: PHY not detected at address range 0-31\n");
512 return -1;
513 } else {
514 debug("ARMD100 FEC: PHY detected at addr %d\n", phy_adr);
515 miiphy_write(dev->name, PHY_ADR_REQ, PHY_ADR_REQ, phy_adr);
516 }
517#endif
518
519#if defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
520
521 for (i = 0; i < 5; i++) {
522 u16 phy_adr;
523
524 miiphy_read(dev->name, 0xFF, 0xFF, &phy_adr);
525
526 if (miiphy_link(dev->name, phy_adr))
527 return 0;
528 udelay(1000000);
529 }
530
531 printf("ARMD100 FEC: No link on %s\n", dev->name);
532 return -1;
533#endif
534#endif
535 return 0;
536}
537
538static void armdfec_halt(struct eth_device *dev)
539{
540 struct armdfec_device *darmdfec = to_darmdfec(dev);
541 struct armdfec_reg *regs = darmdfec->regs;
542
543
544 clrbits_le32(®s->sdma_cmd, SDMA_CMD_ERD);
545
546
547
548
549
550 abortdma(dev);
551
552
553 writel(0, ®s->im);
554 writel(0, ®s->ic);
555 writel(0, ®s->iwc);
556
557
558 clrbits_le32(®s->pconf, PCR_EN);
559}
560
561static int armdfec_send(struct eth_device *dev, void *dataptr, int datasize)
562{
563 struct armdfec_device *darmdfec = to_darmdfec(dev);
564 struct armdfec_reg *regs = darmdfec->regs;
565 struct tx_desc *p_txdesc = darmdfec->p_txdesc;
566 void *p = (void *)dataptr;
567 int retry = PHY_WAIT_ITERATIONS * PHY_WAIT_MICRO_SECONDS;
568 u32 cmd_sts, temp;
569
570
571 if ((u32)dataptr & 0x07) {
572 if (datasize > PKTSIZE_ALIGN) {
573 printf("ARMD100 FEC: Non-aligned data too large (%d)\n",
574 datasize);
575 return -1;
576 }
577 memcpy(darmdfec->p_aligned_txbuf, p, datasize);
578 p = darmdfec->p_aligned_txbuf;
579 }
580
581 p_txdesc->cmd_sts = TX_ZERO_PADDING | TX_GEN_CRC;
582 p_txdesc->cmd_sts |= TX_FIRST_DESC | TX_LAST_DESC;
583 p_txdesc->cmd_sts |= BUF_OWNED_BY_DMA;
584 p_txdesc->cmd_sts |= TX_EN_INT;
585 p_txdesc->buf_ptr = p;
586 p_txdesc->byte_cnt = datasize;
587
588
589 temp = (u32)®s->txcdp[TXQ];
590 writel((u32)p_txdesc, temp);
591 writel(SDMA_CMD_TXDL | SDMA_CMD_TXDH | SDMA_CMD_ERD, ®s->sdma_cmd);
592
593
594
595
596 cmd_sts = readl(&p_txdesc->cmd_sts);
597 while (cmd_sts & BUF_OWNED_BY_DMA) {
598
599 if ((cmd_sts & (TX_ERROR | TX_LAST_DESC)) ==
600 (TX_ERROR | TX_LAST_DESC)) {
601 printf("ARMD100 FEC: (%s) in xmit packet\n", __func__);
602 return -1;
603 }
604 cmd_sts = readl(&p_txdesc->cmd_sts);
605 if (!(retry--)) {
606 printf("ARMD100 FEC: (%s) xmit packet timeout!\n",
607 __func__);
608 return -1;
609 }
610 }
611
612 return 0;
613}
614
615static int armdfec_recv(struct eth_device *dev)
616{
617 struct armdfec_device *darmdfec = to_darmdfec(dev);
618 struct rx_desc *p_rxdesc_curr = darmdfec->p_rxdesc_curr;
619 u32 cmd_sts;
620 u32 timeout = 0;
621 u32 temp;
622
623
624 do {
625 if (timeout < PHY_WAIT_ITERATIONS * PHY_WAIT_MICRO_SECONDS) {
626 timeout++;
627 } else {
628 debug("ARMD100 FEC: %s time out...\n", __func__);
629 return -1;
630 }
631 } while (readl(&p_rxdesc_curr->cmd_sts) & BUF_OWNED_BY_DMA);
632
633 if (p_rxdesc_curr->byte_cnt != 0) {
634 debug("ARMD100 FEC: %s: Received %d byte Packet @ 0x%x"
635 "(cmd_sts= %08x)\n", __func__,
636 (u32)p_rxdesc_curr->byte_cnt,
637 (u32)p_rxdesc_curr->buf_ptr,
638 (u32)p_rxdesc_curr->cmd_sts);
639 }
640
641
642
643
644
645
646 cmd_sts = readl(&p_rxdesc_curr->cmd_sts);
647
648 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
649 (RX_FIRST_DESC | RX_LAST_DESC)) {
650 printf("ARMD100 FEC: (%s) Dropping packet spread on"
651 " multiple descriptors\n", __func__);
652 } else if (cmd_sts & RX_ERROR) {
653 printf("ARMD100 FEC: (%s) Dropping packet with errors\n",
654 __func__);
655 } else {
656
657 debug("ARMD100 FEC: (%s) Sending Received packet to"
658 " upper layer (NetReceive)\n", __func__);
659
660
661
662
663
664
665 NetReceive((p_rxdesc_curr->buf_ptr + RX_BUF_OFFSET),
666 (int)(p_rxdesc_curr->byte_cnt - RX_BUF_OFFSET));
667 }
668
669
670
671 p_rxdesc_curr->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT;
672 p_rxdesc_curr->buf_size = PKTSIZE_ALIGN;
673 p_rxdesc_curr->byte_cnt = 0;
674
675 temp = (u32)&darmdfec->p_rxdesc_curr;
676 writel((u32)p_rxdesc_curr->nxtdesc_p, temp);
677
678 return 0;
679}
680
681int armada100_fec_register(unsigned long base_addr)
682{
683 struct armdfec_device *darmdfec;
684 struct eth_device *dev;
685
686 darmdfec = malloc(sizeof(struct armdfec_device));
687 if (!darmdfec)
688 goto error;
689
690 memset(darmdfec, 0, sizeof(struct armdfec_device));
691
692 darmdfec->htpr = memalign(8, HASH_ADDR_TABLE_SIZE);
693 if (!darmdfec->htpr)
694 goto error1;
695
696 darmdfec->p_rxdesc = memalign(PKTALIGN,
697 ARMDFEC_RXQ_DESC_ALIGNED_SIZE * RINGSZ + 1);
698
699 if (!darmdfec->p_rxdesc)
700 goto error1;
701
702 darmdfec->p_rxbuf = memalign(PKTALIGN, RINGSZ * PKTSIZE_ALIGN + 1);
703 if (!darmdfec->p_rxbuf)
704 goto error1;
705
706 darmdfec->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN);
707 if (!darmdfec->p_aligned_txbuf)
708 goto error1;
709
710 darmdfec->p_txdesc = memalign(PKTALIGN, sizeof(struct tx_desc) + 1);
711 if (!darmdfec->p_txdesc)
712 goto error1;
713
714 dev = &darmdfec->dev;
715
716 darmdfec->regs = (void *)base_addr;
717
718
719 strcpy(dev->name, "armd-fec0");
720
721 dev->init = armdfec_init;
722 dev->halt = armdfec_halt;
723 dev->send = armdfec_send;
724 dev->recv = armdfec_recv;
725
726 eth_register(dev);
727
728#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
729 miiphy_register(dev->name, smi_reg_read, smi_reg_write);
730#endif
731 return 0;
732
733error1:
734 free(darmdfec->p_aligned_txbuf);
735 free(darmdfec->p_rxbuf);
736 free(darmdfec->p_rxdesc);
737 free(darmdfec->htpr);
738error:
739 free(darmdfec);
740 printf("AMD100 FEC: (%s) Failed to allocate memory\n", __func__);
741 return -1;
742}
743