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23#include <common.h>
24#include <lcd.h>
25#include <linux/err.h>
26#include <asm/arch/dsim.h>
27#include <asm/arch/mipi_dsim.h>
28
29#include "exynos_mipi_dsi_lowlevel.h"
30
31#define MHZ (1000 * 1000)
32#define FIN_HZ (24 * MHZ)
33
34#define DFIN_PLL_MIN_HZ (6 * MHZ)
35#define DFIN_PLL_MAX_HZ (12 * MHZ)
36
37#define DFVCO_MIN_HZ (500 * MHZ)
38#define DFVCO_MAX_HZ (1000 * MHZ)
39
40#define TRY_GET_FIFO_TIMEOUT (5000 * 2)
41
42
43enum {
44 DSIM_STATE_INIT,
45 DSIM_STATE_STOP,
46 DSIM_STATE_HSCLKEN,
47 DSIM_STATE_ULPS
48};
49
50
51enum {
52 DSIM_LANE_CLOCK = (1 << 0),
53 DSIM_LANE_DATA0 = (1 << 1),
54 DSIM_LANE_DATA1 = (1 << 2),
55 DSIM_LANE_DATA2 = (1 << 3),
56 DSIM_LANE_DATA3 = (1 << 4)
57};
58
59static unsigned int dpll_table[15] = {
60 100, 120, 170, 220, 270,
61 320, 390, 450, 510, 560,
62 640, 690, 770, 870, 950
63};
64
65static void exynos_mipi_dsi_long_data_wr(struct mipi_dsim_device *dsim,
66 unsigned int data0, unsigned int data1)
67{
68 unsigned int data_cnt = 0, payload = 0;
69
70
71 for (data_cnt = 0; data_cnt < data1; data_cnt += 4) {
72
73
74
75
76 if ((data1 - data_cnt) < 4) {
77 if ((data1 - data_cnt) == 3) {
78 payload = *(u8 *)(data0 + data_cnt) |
79 (*(u8 *)(data0 + (data_cnt + 1))) << 8 |
80 (*(u8 *)(data0 + (data_cnt + 2))) << 16;
81 debug("count = 3 payload = %x, %x %x %x\n",
82 payload, *(u8 *)(data0 + data_cnt),
83 *(u8 *)(data0 + (data_cnt + 1)),
84 *(u8 *)(data0 + (data_cnt + 2)));
85 } else if ((data1 - data_cnt) == 2) {
86 payload = *(u8 *)(data0 + data_cnt) |
87 (*(u8 *)(data0 + (data_cnt + 1))) << 8;
88 debug("count = 2 payload = %x, %x %x\n", payload,
89 *(u8 *)(data0 + data_cnt),
90 *(u8 *)(data0 + (data_cnt + 1)));
91 } else if ((data1 - data_cnt) == 1) {
92 payload = *(u8 *)(data0 + data_cnt);
93 }
94 } else {
95
96 payload = *(u8 *)(data0 + data_cnt) |
97 (*(u8 *)(data0 + (data_cnt + 1))) << 8 |
98 (*(u8 *)(data0 + (data_cnt + 2))) << 16 |
99 (*(u8 *)(data0 + (data_cnt + 3))) << 24;
100
101 debug("count = 4 payload = %x, %x %x %x %x\n",
102 payload, *(u8 *)(data0 + data_cnt),
103 *(u8 *)(data0 + (data_cnt + 1)),
104 *(u8 *)(data0 + (data_cnt + 2)),
105 *(u8 *)(data0 + (data_cnt + 3)));
106
107 }
108 exynos_mipi_dsi_wr_tx_data(dsim, payload);
109 }
110}
111
112int exynos_mipi_dsi_wr_data(struct mipi_dsim_device *dsim, unsigned int data_id,
113 unsigned int data0, unsigned int data1)
114{
115 unsigned int timeout = TRY_GET_FIFO_TIMEOUT;
116 unsigned long delay_val, delay;
117 unsigned int check_rx_ack = 0;
118
119 if (dsim->state == DSIM_STATE_ULPS) {
120 debug("state is ULPS.\n");
121
122 return -EINVAL;
123 }
124
125 delay_val = MHZ / dsim->dsim_config->esc_clk;
126 delay = 10 * delay_val;
127
128 mdelay(delay);
129
130
131 if (dsim->state == DSIM_STATE_STOP) {
132 while (!(exynos_mipi_dsi_get_fifo_state(dsim) &
133 SFR_HEADER_EMPTY)) {
134 if ((timeout--) > 0)
135 mdelay(1);
136 else {
137 debug("SRF header fifo is not empty.\n");
138 return -EINVAL;
139 }
140 }
141 }
142
143 switch (data_id) {
144
145 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
146 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
147 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
148 case MIPI_DSI_DCS_SHORT_WRITE:
149 case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
150 case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
151 debug("data0 = %x data1 = %x\n",
152 data0, data1);
153 exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0, data1);
154 if (check_rx_ack) {
155
156 return 0;
157 } else {
158 return -EINVAL;
159 }
160
161
162 case MIPI_DSI_COLOR_MODE_OFF:
163 case MIPI_DSI_COLOR_MODE_ON:
164 case MIPI_DSI_SHUTDOWN_PERIPHERAL:
165 case MIPI_DSI_TURN_ON_PERIPHERAL:
166 exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0, data1);
167 if (check_rx_ack) {
168
169 return 0;
170 } else {
171 return -EINVAL;
172 }
173
174
175 case MIPI_DSI_V_SYNC_START:
176 case MIPI_DSI_V_SYNC_END:
177 case MIPI_DSI_H_SYNC_START:
178 case MIPI_DSI_H_SYNC_END:
179 case MIPI_DSI_END_OF_TRANSMISSION:
180 return 0;
181
182
183 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
184 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
185 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
186 case MIPI_DSI_DCS_READ:
187 exynos_mipi_dsi_clear_all_interrupt(dsim);
188 exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0, data1);
189
190 return 0;
191
192
193 case MIPI_DSI_NULL_PACKET:
194 case MIPI_DSI_BLANKING_PACKET:
195 return 0;
196 case MIPI_DSI_GENERIC_LONG_WRITE:
197 case MIPI_DSI_DCS_LONG_WRITE:
198 {
199 unsigned int data_cnt = 0, payload = 0;
200
201
202 if (data1 < 4) {
203 payload = *(u8 *)(data0) |
204 *(u8 *)(data0 + 1) << 8 |
205 *(u8 *)(data0 + 2) << 16;
206
207 exynos_mipi_dsi_wr_tx_data(dsim, payload);
208
209 debug("count = %d payload = %x,%x %x %x\n",
210 data1, payload,
211 *(u8 *)(data0 + data_cnt),
212 *(u8 *)(data0 + (data_cnt + 1)),
213 *(u8 *)(data0 + (data_cnt + 2)));
214 } else {
215
216 exynos_mipi_dsi_long_data_wr(dsim, data0, data1);
217 }
218
219
220 exynos_mipi_dsi_wr_tx_header(dsim, data_id, data1 & 0xff,
221 (data1 & 0xff00) >> 8);
222
223 }
224 if (check_rx_ack)
225
226 return 0;
227 else
228 return -EINVAL;
229
230
231 case MIPI_DSI_PACKED_PIXEL_STREAM_16:
232 case MIPI_DSI_PACKED_PIXEL_STREAM_18:
233 case MIPI_DSI_PIXEL_STREAM_3BYTE_18:
234 case MIPI_DSI_PACKED_PIXEL_STREAM_24:
235 if (check_rx_ack) {
236
237 return 0;
238 } else {
239 return -EINVAL;
240 }
241 default:
242 debug("data id %x is not supported current DSI spec.\n",
243 data_id);
244
245 return -EINVAL;
246 }
247
248 return 0;
249}
250
251int exynos_mipi_dsi_pll_on(struct mipi_dsim_device *dsim, unsigned int enable)
252{
253 int sw_timeout;
254
255 if (enable) {
256 sw_timeout = 1000;
257
258 exynos_mipi_dsi_clear_interrupt(dsim);
259 exynos_mipi_dsi_enable_pll(dsim, 1);
260 while (1) {
261 sw_timeout--;
262 if (exynos_mipi_dsi_is_pll_stable(dsim))
263 return 0;
264 if (sw_timeout == 0)
265 return -EINVAL;
266 }
267 } else
268 exynos_mipi_dsi_enable_pll(dsim, 0);
269
270 return 0;
271}
272
273unsigned long exynos_mipi_dsi_change_pll(struct mipi_dsim_device *dsim,
274 unsigned int pre_divider, unsigned int main_divider,
275 unsigned int scaler)
276{
277 unsigned long dfin_pll, dfvco, dpll_out;
278 unsigned int i, freq_band = 0xf;
279
280 dfin_pll = (FIN_HZ / pre_divider);
281
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300
301
302 if (dfin_pll < DFIN_PLL_MIN_HZ || dfin_pll > DFIN_PLL_MAX_HZ) {
303 debug("fin_pll range should be 6MHz ~ 12MHz\n");
304 exynos_mipi_dsi_enable_afc(dsim, 0, 0);
305 } else {
306 if (dfin_pll < 7 * MHZ)
307 exynos_mipi_dsi_enable_afc(dsim, 1, 0x1);
308 else if (dfin_pll < 8 * MHZ)
309 exynos_mipi_dsi_enable_afc(dsim, 1, 0x0);
310 else if (dfin_pll < 9 * MHZ)
311 exynos_mipi_dsi_enable_afc(dsim, 1, 0x3);
312 else if (dfin_pll < 10 * MHZ)
313 exynos_mipi_dsi_enable_afc(dsim, 1, 0x2);
314 else if (dfin_pll < 11 * MHZ)
315 exynos_mipi_dsi_enable_afc(dsim, 1, 0x5);
316 else
317 exynos_mipi_dsi_enable_afc(dsim, 1, 0x4);
318 }
319
320 dfvco = dfin_pll * main_divider;
321 debug("dfvco = %lu, dfin_pll = %lu, main_divider = %d\n",
322 dfvco, dfin_pll, main_divider);
323 if (dfvco < DFVCO_MIN_HZ || dfvco > DFVCO_MAX_HZ)
324 debug("fvco range should be 500MHz ~ 1000MHz\n");
325
326 dpll_out = dfvco / (1 << scaler);
327 debug("dpll_out = %lu, dfvco = %lu, scaler = %d\n",
328 dpll_out, dfvco, scaler);
329
330 for (i = 0; i < ARRAY_SIZE(dpll_table); i++) {
331 if (dpll_out < dpll_table[i] * MHZ) {
332 freq_band = i;
333 break;
334 }
335 }
336
337 debug("freq_band = %d\n", freq_band);
338
339 exynos_mipi_dsi_pll_freq(dsim, pre_divider, main_divider, scaler);
340
341 exynos_mipi_dsi_hs_zero_ctrl(dsim, 0);
342 exynos_mipi_dsi_prep_ctrl(dsim, 0);
343
344
345 exynos_mipi_dsi_pll_freq_band(dsim, freq_band);
346
347
348 exynos_mipi_dsi_pll_stable_time(dsim,
349 dsim->dsim_config->pll_stable_time);
350
351
352 debug("FOUT of mipi dphy pll is %luMHz\n",
353 (dpll_out / MHZ));
354
355 return dpll_out;
356}
357
358int exynos_mipi_dsi_set_clock(struct mipi_dsim_device *dsim,
359 unsigned int byte_clk_sel, unsigned int enable)
360{
361 unsigned int esc_div;
362 unsigned long esc_clk_error_rate;
363 unsigned long hs_clk = 0, byte_clk = 0, escape_clk = 0;
364
365 if (enable) {
366 dsim->e_clk_src = byte_clk_sel;
367
368
369 exynos_mipi_dsi_set_byte_clock_src(dsim, byte_clk_sel);
370
371
372 if (byte_clk_sel == DSIM_PLL_OUT_DIV8) {
373 hs_clk = exynos_mipi_dsi_change_pll(dsim,
374 dsim->dsim_config->p, dsim->dsim_config->m,
375 dsim->dsim_config->s);
376 if (hs_clk == 0) {
377 debug("failed to get hs clock.\n");
378 return -EINVAL;
379 }
380
381 byte_clk = hs_clk / 8;
382 exynos_mipi_dsi_enable_pll_bypass(dsim, 0);
383 exynos_mipi_dsi_pll_on(dsim, 1);
384
385 } else if (byte_clk_sel == DSIM_EXT_CLK_DIV8)
386 debug("not support EXT CLK source for MIPI DSIM\n");
387 else if (byte_clk_sel == DSIM_EXT_CLK_BYPASS)
388 debug("not support EXT CLK source for MIPI DSIM\n");
389
390
391 esc_div = byte_clk / (dsim->dsim_config->esc_clk);
392 debug("esc_div = %d, byte_clk = %lu, esc_clk = %lu\n",
393 esc_div, byte_clk, dsim->dsim_config->esc_clk);
394 if ((byte_clk / esc_div) >= (20 * MHZ) ||
395 (byte_clk / esc_div) > dsim->dsim_config->esc_clk)
396 esc_div += 1;
397
398 escape_clk = byte_clk / esc_div;
399 debug("escape_clk = %lu, byte_clk = %lu, esc_div = %d\n",
400 escape_clk, byte_clk, esc_div);
401
402
403 exynos_mipi_dsi_enable_byte_clock(dsim, 1);
404
405
406 exynos_mipi_dsi_set_esc_clk_prs(dsim, 1, esc_div);
407
408 exynos_mipi_dsi_enable_esc_clk_on_lane(dsim,
409 (DSIM_LANE_CLOCK | dsim->data_lane), 1);
410
411 debug("byte clock is %luMHz\n",
412 (byte_clk / MHZ));
413 debug("escape clock that user's need is %lu\n",
414 (dsim->dsim_config->esc_clk / MHZ));
415 debug("escape clock divider is %x\n", esc_div);
416 debug("escape clock is %luMHz\n",
417 ((byte_clk / esc_div) / MHZ));
418
419 if ((byte_clk / esc_div) > escape_clk) {
420 esc_clk_error_rate = escape_clk /
421 (byte_clk / esc_div);
422 debug("error rate is %lu over.\n",
423 (esc_clk_error_rate / 100));
424 } else if ((byte_clk / esc_div) < (escape_clk)) {
425 esc_clk_error_rate = (byte_clk / esc_div) /
426 escape_clk;
427 debug("error rate is %lu under.\n",
428 (esc_clk_error_rate / 100));
429 }
430 } else {
431 exynos_mipi_dsi_enable_esc_clk_on_lane(dsim,
432 (DSIM_LANE_CLOCK | dsim->data_lane), 0);
433 exynos_mipi_dsi_set_esc_clk_prs(dsim, 0, 0);
434
435
436 exynos_mipi_dsi_enable_byte_clock(dsim, 0);
437
438 if (byte_clk_sel == DSIM_PLL_OUT_DIV8)
439 exynos_mipi_dsi_pll_on(dsim, 0);
440 }
441
442 return 0;
443}
444
445int exynos_mipi_dsi_init_dsim(struct mipi_dsim_device *dsim)
446{
447 dsim->state = DSIM_STATE_INIT;
448
449 switch (dsim->dsim_config->e_no_data_lane) {
450 case DSIM_DATA_LANE_1:
451 dsim->data_lane = DSIM_LANE_DATA0;
452 break;
453 case DSIM_DATA_LANE_2:
454 dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1;
455 break;
456 case DSIM_DATA_LANE_3:
457 dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 |
458 DSIM_LANE_DATA2;
459 break;
460 case DSIM_DATA_LANE_4:
461 dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 |
462 DSIM_LANE_DATA2 | DSIM_LANE_DATA3;
463 break;
464 default:
465 debug("data lane is invalid.\n");
466 return -EINVAL;
467 };
468
469 exynos_mipi_dsi_sw_reset(dsim);
470 exynos_mipi_dsi_dp_dn_swap(dsim, 0);
471
472 return 0;
473}
474
475int exynos_mipi_dsi_enable_frame_done_int(struct mipi_dsim_device *dsim,
476 unsigned int enable)
477{
478
479 exynos_mipi_dsi_set_interrupt_mask(dsim, INTMSK_FRAME_DONE, enable);
480
481 return 0;
482}
483
484static void convert_to_fb_videomode(struct fb_videomode *mode1,
485 vidinfo_t *mode2)
486{
487 mode1->xres = mode2->vl_width;
488 mode1->yres = mode2->vl_height;
489 mode1->upper_margin = mode2->vl_vfpd;
490 mode1->lower_margin = mode2->vl_vbpd;
491 mode1->left_margin = mode2->vl_hfpd;
492 mode1->right_margin = mode2->vl_hbpd;
493 mode1->vsync_len = mode2->vl_vspw;
494 mode1->hsync_len = mode2->vl_hspw;
495}
496
497int exynos_mipi_dsi_set_display_mode(struct mipi_dsim_device *dsim,
498 struct mipi_dsim_config *dsim_config)
499{
500 struct exynos_platform_mipi_dsim *dsim_pd;
501 struct fb_videomode lcd_video;
502 vidinfo_t *vid;
503
504 dsim_pd = (struct exynos_platform_mipi_dsim *)dsim->pd;
505 vid = (vidinfo_t *)dsim_pd->lcd_panel_info;
506
507 convert_to_fb_videomode(&lcd_video, vid);
508
509
510 if (dsim->dsim_config->e_interface == (u32) DSIM_VIDEO) {
511 if (dsim->dsim_config->auto_vertical_cnt == 0) {
512 exynos_mipi_dsi_set_main_disp_vporch(dsim,
513 vid->vl_cmd_allow_len,
514 lcd_video.upper_margin,
515 lcd_video.lower_margin);
516 exynos_mipi_dsi_set_main_disp_hporch(dsim,
517 lcd_video.left_margin,
518 lcd_video.right_margin);
519 exynos_mipi_dsi_set_main_disp_sync_area(dsim,
520 lcd_video.vsync_len,
521 lcd_video.hsync_len);
522 }
523 }
524
525 exynos_mipi_dsi_set_main_disp_resol(dsim, lcd_video.xres,
526 lcd_video.yres);
527
528 exynos_mipi_dsi_display_config(dsim, dsim->dsim_config);
529
530 debug("lcd panel ==> width = %d, height = %d\n",
531 lcd_video.xres, lcd_video.yres);
532
533 return 0;
534}
535
536int exynos_mipi_dsi_init_link(struct mipi_dsim_device *dsim)
537{
538 unsigned int time_out = 100;
539
540 switch (dsim->state) {
541 case DSIM_STATE_INIT:
542 exynos_mipi_dsi_init_fifo_pointer(dsim, 0x1f);
543
544
545 exynos_mipi_dsi_init_config(dsim);
546 exynos_mipi_dsi_enable_lane(dsim, DSIM_LANE_CLOCK, 1);
547 exynos_mipi_dsi_enable_lane(dsim, dsim->data_lane, 1);
548
549
550 exynos_mipi_dsi_set_clock(dsim,
551 dsim->dsim_config->e_byte_clk, 1);
552
553
554 while (!(exynos_mipi_dsi_is_lane_state(dsim))) {
555 time_out--;
556 if (time_out == 0) {
557 debug("DSI Master is not stop state.\n");
558 debug("Check initialization process\n");
559
560 return -EINVAL;
561 }
562 }
563
564 dsim->state = DSIM_STATE_STOP;
565
566
567 exynos_mipi_dsi_set_stop_state_counter(dsim,
568 dsim->dsim_config->stop_holding_cnt);
569 exynos_mipi_dsi_set_bta_timeout(dsim,
570 dsim->dsim_config->bta_timeout);
571 exynos_mipi_dsi_set_lpdr_timeout(dsim,
572 dsim->dsim_config->rx_timeout);
573
574 return 0;
575 default:
576 debug("DSI Master is already init.\n");
577 return 0;
578 }
579
580 return 0;
581}
582
583int exynos_mipi_dsi_set_hs_enable(struct mipi_dsim_device *dsim)
584{
585 if (dsim->state == DSIM_STATE_STOP) {
586 if (dsim->e_clk_src != DSIM_EXT_CLK_BYPASS) {
587 dsim->state = DSIM_STATE_HSCLKEN;
588
589
590 exynos_mipi_dsi_set_lcdc_transfer_mode(dsim, 0);
591 exynos_mipi_dsi_set_cpu_transfer_mode(dsim, 0);
592
593 exynos_mipi_dsi_enable_hs_clock(dsim, 1);
594
595 return 0;
596 } else
597 debug("clock source is external bypass.\n");
598 } else
599 debug("DSIM is not stop state.\n");
600
601 return 0;
602}
603
604int exynos_mipi_dsi_set_data_transfer_mode(struct mipi_dsim_device *dsim,
605 unsigned int mode)
606{
607 if (mode) {
608 if (dsim->state != DSIM_STATE_HSCLKEN) {
609 debug("HS Clock lane is not enabled.\n");
610 return -EINVAL;
611 }
612
613 exynos_mipi_dsi_set_lcdc_transfer_mode(dsim, 0);
614 } else {
615 if (dsim->state == DSIM_STATE_INIT || dsim->state ==
616 DSIM_STATE_ULPS) {
617 debug("DSI Master is not STOP or HSDT state.\n");
618 return -EINVAL;
619 }
620
621 exynos_mipi_dsi_set_cpu_transfer_mode(dsim, 0);
622 }
623
624 return 0;
625}
626
627int exynos_mipi_dsi_get_frame_done_status(struct mipi_dsim_device *dsim)
628{
629 return _exynos_mipi_dsi_get_frame_done_status(dsim);
630}
631
632int exynos_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim)
633{
634 _exynos_mipi_dsi_clear_frame_done(dsim);
635
636 return 0;
637}
638
