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29#include <common.h>
30
31#include <asm/io.h>
32#include <pci.h>
33#include <video_fb.h>
34#include "videomodes.h"
35#include <mb862xx.h>
36
37#if defined(CONFIG_POST)
38#include <post.h>
39#endif
40
41
42
43
44GraphicDevice mb862xx;
45
46
47
48
49#define VIDEO_MEM_SIZE 0x01FC0000
50
51#if defined(CONFIG_PCI)
52#if defined(CONFIG_VIDEO_CORALP)
53
54static struct pci_device_id supported[] = {
55 { PCI_VENDOR_ID_FUJITSU, PCI_DEVICE_ID_CORAL_P },
56 { PCI_VENDOR_ID_FUJITSU, PCI_DEVICE_ID_CORAL_PA },
57 { }
58};
59
60
61unsigned int fr_div[] = { 0x00000f00, 0x00000900, 0x00000500 };
62#endif
63#endif
64
65#if defined(CONFIG_VIDEO_CORALP)
66#define rd_io in32r
67#define wr_io out32r
68#else
69#define rd_io(addr) in_be32((volatile unsigned *)(addr))
70#define wr_io(addr, val) out_be32((volatile unsigned *)(addr), (val))
71#endif
72
73#define HOST_RD_REG(off) rd_io((dev->frameAdrs + GC_HOST_BASE + (off)))
74#define HOST_WR_REG(off, val) wr_io((dev->frameAdrs + GC_HOST_BASE + (off)), \
75 (val))
76#define DISP_RD_REG(off) rd_io((dev->frameAdrs + GC_DISP_BASE + (off)))
77#define DISP_WR_REG(off, val) wr_io((dev->frameAdrs + GC_DISP_BASE + (off)), \
78 (val))
79#define DE_RD_REG(off) rd_io((dev->dprBase + (off)))
80#define DE_WR_REG(off, val) wr_io((dev->dprBase + (off)), (val))
81
82#if defined(CONFIG_VIDEO_CORALP)
83#define DE_WR_FIFO(val) wr_io((dev->dprBase + (GC_GEO_FIFO)), (val))
84#else
85#define DE_WR_FIFO(val) wr_io((dev->dprBase + (GC_FIFO)), (val))
86#endif
87
88#define L0PAL_WR_REG(idx, val) wr_io((dev->frameAdrs + \
89 (GC_DISP_BASE | GC_L0PAL0) + \
90 ((idx) << 2)), (val))
91
92#if defined(CONFIG_VIDEO_MB862xx_ACCEL)
93static void gdc_sw_reset (void)
94{
95 GraphicDevice *dev = &mb862xx;
96
97 HOST_WR_REG (GC_SRST, 0x1);
98 udelay (500);
99 video_hw_init ();
100}
101
102
103static void de_wait (void)
104{
105 GraphicDevice *dev = &mb862xx;
106 int lc = 0x10000;
107
108
109
110
111
112 while (DE_RD_REG (GC_CTR) & 0x00000131)
113 if (lc-- < 0) {
114 gdc_sw_reset ();
115 puts ("gdc reset done after drawing engine lock.\n");
116 break;
117 }
118}
119
120static void de_wait_slots (int slots)
121{
122 GraphicDevice *dev = &mb862xx;
123 int lc = 0x10000;
124
125
126 while (DE_RD_REG (GC_IFCNT) < slots)
127 if (lc-- < 0) {
128 gdc_sw_reset ();
129 puts ("gdc reset done after drawing engine lock.\n");
130 break;
131 }
132}
133#endif
134
135#if !defined(CONFIG_VIDEO_CORALP)
136static void board_disp_init (void)
137{
138 GraphicDevice *dev = &mb862xx;
139 const gdc_regs *regs = board_get_regs ();
140
141 while (regs->index) {
142 DISP_WR_REG (regs->index, regs->value);
143 regs++;
144 }
145}
146#endif
147
148
149
150
151
152static void de_init (void)
153{
154 GraphicDevice *dev = &mb862xx;
155#if defined(CONFIG_VIDEO_MB862xx_ACCEL)
156 int cf = (dev->gdfBytesPP == 1) ? 0x0000 : 0x8000;
157
158 dev->dprBase = dev->frameAdrs + GC_DRAW_BASE;
159
160
161 de_wait_slots (2);
162 DE_WR_FIFO (0xf1010108);
163 DE_WR_FIFO (cf | 0x0300);
164 DE_WR_REG (GC_FBR, 0x0);
165 DE_WR_REG (GC_XRES, dev->winSizeX);
166 DE_WR_REG (GC_FC, 0x0);
167 DE_WR_REG (GC_BC, 0x0);
168
169 DE_WR_REG (GC_CXMIN, 0x0);
170 DE_WR_REG (GC_CXMAX, dev->winSizeX);
171 DE_WR_REG (GC_CYMIN, 0x0);
172 DE_WR_REG (GC_CYMAX, dev->winSizeY);
173
174
175 de_wait_slots (3);
176 DE_WR_FIFO (0x09410000);
177 DE_WR_FIFO (0x00000000);
178 DE_WR_FIFO (dev->winSizeY << 16 | dev->winSizeX);
179
180 de_wait ();
181#else
182 unsigned int i, *p;
183
184 i = dev->winSizeX * dev->winSizeY;
185 p = (unsigned int *)dev->frameAdrs;
186 while (i--)
187 *p++ = 0;
188#endif
189}
190
191#if defined(CONFIG_VIDEO_CORALP)
192
193#ifndef CONFIG_SYS_MB862xx_CCF
194#define CONFIG_SYS_MB862xx_CCF 0x00090000
195#endif
196#ifndef CONFIG_SYS_MB862xx_MMR
197#define CONFIG_SYS_MB862xx_MMR 0x11d7fa13
198#endif
199
200unsigned int pci_video_init (void)
201{
202 GraphicDevice *dev = &mb862xx;
203 pci_dev_t devbusfn;
204 u16 device;
205
206 if ((devbusfn = pci_find_devices (supported, 0)) < 0) {
207 puts("controller not present\n");
208 return 0;
209 }
210
211
212 pci_write_config_dword (devbusfn, PCI_COMMAND,
213 (PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
214 pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &dev->frameAdrs);
215 dev->frameAdrs = pci_mem_to_phys (devbusfn, dev->frameAdrs);
216
217 if (dev->frameAdrs == 0) {
218 puts ("PCI config: failed to get base address\n");
219 return 0;
220 }
221
222 dev->pciBase = dev->frameAdrs;
223
224 puts("Coral-");
225
226 pci_read_config_word(devbusfn, PCI_DEVICE_ID, &device);
227 switch (device) {
228 case PCI_DEVICE_ID_CORAL_P:
229 puts("P\n");
230 break;
231 case PCI_DEVICE_ID_CORAL_PA:
232 puts("PA\n");
233 break;
234 default:
235 puts("Unknown\n");
236 return 0;
237 }
238
239
240 HOST_WR_REG(GC_CCF, CONFIG_SYS_MB862xx_CCF);
241 udelay (200);
242 HOST_WR_REG(GC_MMR, CONFIG_SYS_MB862xx_MMR);
243 udelay (100);
244 return dev->frameAdrs;
245}
246
247unsigned int card_init (void)
248{
249 GraphicDevice *dev = &mb862xx;
250 unsigned int cf, videomode, div = 0;
251 unsigned long t1, hsync, vsync;
252 char *penv;
253 int tmp, i, bpp;
254 struct ctfb_res_modes *res_mode;
255 struct ctfb_res_modes var_mode;
256
257 memset (dev, 0, sizeof (GraphicDevice));
258
259 if (!pci_video_init ())
260 return 0;
261
262 tmp = 0;
263 videomode = 0x310;
264
265 if ((penv = getenv ("videomode")) != NULL) {
266
267 if (penv[0] <= '9') {
268 videomode = (int) simple_strtoul (penv, NULL, 16);
269 tmp = 1;
270 }
271 } else {
272 tmp = 1;
273 }
274
275 if (tmp) {
276
277 for (i = 0; i < VESA_MODES_COUNT; i++) {
278 if (vesa_modes[i].vesanr == videomode)
279 break;
280 }
281 if (i == VESA_MODES_COUNT) {
282 printf ("\tno VESA Mode found, fallback to mode 0x%x\n",
283 videomode);
284 i = 0;
285 }
286 res_mode = (struct ctfb_res_modes *)
287 &res_mode_init[vesa_modes[i].resindex];
288 if (vesa_modes[i].resindex > 2) {
289 puts ("\tUnsupported resolution, using default\n");
290 bpp = vesa_modes[1].bits_per_pixel;
291 div = fr_div[1];
292 }
293 bpp = vesa_modes[i].bits_per_pixel;
294 div = fr_div[vesa_modes[i].resindex];
295 } else {
296 res_mode = (struct ctfb_res_modes *) &var_mode;
297 bpp = video_get_params (res_mode, penv);
298 }
299
300
301 t1 = (res_mode->left_margin + res_mode->xres +
302 res_mode->right_margin + res_mode->hsync_len) / 8;
303 t1 *= 8;
304 t1 *= res_mode->pixclock;
305 t1 /= 1000;
306 hsync = 1000000000L / t1;
307 t1 *= (res_mode->upper_margin + res_mode->yres +
308 res_mode->lower_margin + res_mode->vsync_len);
309 t1 /= 1000;
310 vsync = 1000000000L / t1;
311
312
313 sprintf (dev->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres,
314 res_mode->yres, bpp, (hsync / 1000), (vsync / 1000));
315 printf ("\t%s\n", dev->modeIdent);
316 dev->winSizeX = res_mode->xres;
317 dev->winSizeY = res_mode->yres;
318 dev->memSize = VIDEO_MEM_SIZE;
319
320 switch (bpp) {
321 case 8:
322 dev->gdfIndex = GDF__8BIT_INDEX;
323 dev->gdfBytesPP = 1;
324 break;
325 case 15:
326 case 16:
327 dev->gdfIndex = GDF_15BIT_555RGB;
328 dev->gdfBytesPP = 2;
329 break;
330 default:
331 printf ("\t%d bpp configured, but only 8,15 and 16 supported\n",
332 bpp);
333 puts ("\tfallback to 15bpp\n");
334 dev->gdfIndex = GDF_15BIT_555RGB;
335 dev->gdfBytesPP = 2;
336 }
337
338
339 DISP_WR_REG (GC_DCM1, div);
340
341 cf = (dev->gdfBytesPP == 1) ? 0x00000000 : 0x80000000;
342 DISP_WR_REG (GC_L0M, ((dev->winSizeX * dev->gdfBytesPP) / 64) << 16 |
343 (dev->winSizeY - 1) | cf);
344 DISP_WR_REG (GC_L0OA0, 0x0);
345 DISP_WR_REG (GC_L0DA0, 0x0);
346 DISP_WR_REG (GC_L0DY_L0DX, 0x0);
347 DISP_WR_REG (GC_L0EM, 0x0);
348 DISP_WR_REG (GC_L0WY_L0WX, 0x0);
349 DISP_WR_REG (GC_L0WH_L0WW, (dev->winSizeY - 1) << 16 | dev->winSizeX);
350
351
352 DISP_WR_REG (GC_HTP_A, (dev->winSizeX +
353 res_mode->left_margin +
354 res_mode->right_margin +
355 res_mode->hsync_len - 1) << 16);
356 DISP_WR_REG (GC_HDB_HDP_A, (dev->winSizeX - 1) << 16 |
357 (dev->winSizeX - 1));
358 DISP_WR_REG (GC_VSW_HSW_HSP_A, (res_mode->vsync_len - 1) << 24 |
359 (res_mode->hsync_len - 1) << 16 |
360 (dev->winSizeX +
361 res_mode->right_margin - 1));
362 DISP_WR_REG (GC_VTR_A, (dev->winSizeY + res_mode->lower_margin +
363 res_mode->upper_margin +
364 res_mode->vsync_len - 1) << 16);
365 DISP_WR_REG (GC_VDP_VSP_A, (dev->winSizeY-1) << 16 |
366 (dev->winSizeY +
367 res_mode->lower_margin - 1));
368 DISP_WR_REG (GC_WY_WX, 0x0);
369 DISP_WR_REG (GC_WH_WW, dev->winSizeY << 16 | dev->winSizeX);
370
371 DISP_WR_REG (GC_DCM1, 0x80010000 | div);
372
373 return dev->frameAdrs;
374}
375#endif
376
377
378#if !defined(CONFIG_VIDEO_CORALP)
379int mb862xx_probe(unsigned int addr)
380{
381 GraphicDevice *dev = &mb862xx;
382 unsigned int reg;
383
384 dev->frameAdrs = addr;
385 dev->dprBase = dev->frameAdrs + GC_DRAW_BASE;
386
387
388 reg = HOST_RD_REG (GC_CID);
389 reg = HOST_RD_REG (GC_CID);
390 if (reg == 0x303) {
391 reg = DE_RD_REG(GC_REV);
392 reg = DE_RD_REG(GC_REV);
393 if ((reg & ~0xff) == 0x20050100)
394 return MB862XX_TYPE_LIME;
395 }
396
397 return 0;
398}
399#endif
400
401void *video_hw_init (void)
402{
403 GraphicDevice *dev = &mb862xx;
404
405 puts ("Video: Fujitsu ");
406
407 memset (dev, 0, sizeof (GraphicDevice));
408
409#if defined(CONFIG_VIDEO_CORALP)
410 if (card_init () == 0)
411 return NULL;
412#else
413
414
415
416
417 if ((dev->frameAdrs = board_video_init ()) == 0) {
418 puts ("Controller not found!\n");
419 return NULL;
420 } else {
421 puts ("Lime\n");
422
423
424 HOST_WR_REG (GC_CCF, CONFIG_SYS_MB862xx_CCF);
425
426 udelay(300);
427
428 HOST_WR_REG (GC_MMR, CONFIG_SYS_MB862xx_MMR);
429 }
430#endif
431
432 de_init ();
433
434#if !defined(CONFIG_VIDEO_CORALP)
435 board_disp_init ();
436#endif
437
438#if (defined(CONFIG_LWMON5) || \
439 defined(CONFIG_SOCRATES)) && !(CONFIG_POST & CONFIG_SYS_POST_SYSMON)
440
441 board_backlight_switch (1);
442#endif
443
444 return dev;
445}
446
447
448
449
450void video_set_lut (unsigned int index, unsigned char r,
451 unsigned char g, unsigned char b)
452{
453 GraphicDevice *dev = &mb862xx;
454
455 L0PAL_WR_REG (index, (r << 16) | (g << 8) | (b));
456}
457
458#if defined(CONFIG_VIDEO_MB862xx_ACCEL)
459
460
461
462void video_hw_rectfill (unsigned int bpp, unsigned int dst_x,
463 unsigned int dst_y, unsigned int dim_x,
464 unsigned int dim_y, unsigned int color)
465{
466 GraphicDevice *dev = &mb862xx;
467
468 de_wait_slots (3);
469 DE_WR_REG (GC_FC, color);
470 DE_WR_FIFO (0x09410000);
471 DE_WR_FIFO ((dst_y << 16) | dst_x);
472 DE_WR_FIFO ((dim_y << 16) | dim_x);
473 de_wait ();
474}
475
476void video_hw_bitblt (unsigned int bpp, unsigned int src_x,
477 unsigned int src_y, unsigned int dst_x,
478 unsigned int dst_y, unsigned int width,
479 unsigned int height)
480{
481 GraphicDevice *dev = &mb862xx;
482 unsigned int ctrl = 0x0d000000L;
483
484 if (src_x >= dst_x && src_y >= dst_y)
485 ctrl |= 0x00440000L;
486 else if (src_x >= dst_x && src_y <= dst_y)
487 ctrl |= 0x00460000L;
488 else if (src_x <= dst_x && src_y >= dst_y)
489 ctrl |= 0x00450000L;
490 else
491 ctrl |= 0x00470000L;
492
493 de_wait_slots (4);
494 DE_WR_FIFO (ctrl);
495 DE_WR_FIFO ((src_y << 16) | src_x);
496 DE_WR_FIFO ((dst_y << 16) | dst_x);
497 DE_WR_FIFO ((height << 16) | width);
498 de_wait ();
499}
500#endif
501
