1/* 2 * (C) Copyright 2001-2003 3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* 25 * board/config.h - configuration options, board specific 26 */ 27 28#ifndef __CONFIG_H 29#define __CONFIG_H 30 31/* 32 * High Level Configuration Options 33 * (easy to change) 34 */ 35 36#define CONFIG_405EP 1 /* This is a PPC405 CPU */ 37#define CONFIG_4xx 1 /* ...member of PPC4xx family */ 38#define CONFIG_ASH405 1 /* ...on a ASH405 board */ 39 40#define CONFIG_SYS_TEXT_BASE 0xFFFC0000 41 42#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ 43#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ 44 45#define CONFIG_SYS_CLK_FREQ 33333300 /* external frequency to pll */ 46 47#define CONFIG_BAUDRATE 9600 48#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ 49 50#undef CONFIG_BOOTARGS 51#undef CONFIG_BOOTCOMMAND 52 53#define CONFIG_PREBOOT /* enable preboot variable */ 54 55#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 56#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 57 58#undef CONFIG_HAS_ETH1 59 60#define CONFIG_PPC4xx_EMAC 61#define CONFIG_MII 1 /* MII PHY management */ 62#define CONFIG_PHY_ADDR 0 /* PHY address */ 63#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ 64#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ 65 66#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ 67 68 69/* 70 * BOOTP options 71 */ 72#define CONFIG_BOOTP_BOOTFILESIZE 73#define CONFIG_BOOTP_BOOTPATH 74#define CONFIG_BOOTP_GATEWAY 75#define CONFIG_BOOTP_HOSTNAME 76 77 78/* 79 * Command line configuration. 80 */ 81#include <config_cmd_default.h> 82 83#define CONFIG_CMD_DHCP 84#define CONFIG_CMD_IRQ 85#define CONFIG_CMD_ELF 86#define CONFIG_CMD_NAND 87#define CONFIG_CMD_DATE 88#define CONFIG_CMD_I2C 89#define CONFIG_CMD_MII 90#define CONFIG_CMD_PING 91#define CONFIG_CMD_EEPROM 92 93 94#undef CONFIG_WATCHDOG /* watchdog disabled */ 95 96#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ 97#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ 98 99#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ 100 101/* 102 * Miscellaneous configurable options 103 */ 104#define CONFIG_SYS_LONGHELP /* undef to save memory */ 105#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 106 107#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 108 109#if defined(CONFIG_CMD_KGDB) 110#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 111#else 112#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 113#endif 114#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 115#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 116#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 117 118#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ 119 120#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ 121 122#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 123#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 124 125#define CONFIG_CONS_INDEX 1 /* Use UART0 */ 126#define CONFIG_SYS_NS16550 127#define CONFIG_SYS_NS16550_SERIAL 128#define CONFIG_SYS_NS16550_REG_SIZE 1 129#define CONFIG_SYS_NS16550_CLK get_serial_clock() 130 131#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ 132#define CONFIG_SYS_BASE_BAUD 691200 133 134/* The following table includes the supported baudrates */ 135#define CONFIG_SYS_BAUDRATE_TABLE \ 136 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ 137 57600, 115200, 230400, 460800, 921600 } 138 139#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 140#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ 141 142#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 143 144#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ 145 146#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ 147 148#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ 149 150/*----------------------------------------------------------------------- 151 * NAND-FLASH stuff 152 *----------------------------------------------------------------------- 153 */ 154#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 155#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ 156#define NAND_BIG_DELAY_US 25 157 158#define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ 159#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ 160#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ 161#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ 162 163#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ 164#define CONFIG_SYS_NAND_QUIET 1 165 166/*----------------------------------------------------------------------- 167 * PCI stuff 168 *----------------------------------------------------------------------- 169 */ 170#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ 171#define PCI_HOST_FORCE 1 /* configure as pci host */ 172#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ 173 174#define CONFIG_PCI /* include pci support */ 175#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */ 176#undef CONFIG_PCI_PNP /* do pci plug-and-play */ 177 /* resource configuration */ 178 179#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ 180 181#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ 182#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ 183#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ 184#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ 185#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ 186#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ 187#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ 188#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ 189#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ 190 191/*----------------------------------------------------------------------- 192 * Start addresses for the final memory configuration 193 * (Set up by the startup code) 194 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 195 */ 196#define CONFIG_SYS_SDRAM_BASE 0x00000000 197#define CONFIG_SYS_FLASH_BASE 0xFFFC0000 198#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 199#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ 200#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ 201 202/* 203 * For booting Linux, the board info and command line data 204 * have to be in the first 8 MB of memory, since this is 205 * the maximum mapped by the Linux kernel during initialization. 206 */ 207#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 208/*----------------------------------------------------------------------- 209 * FLASH organization 210 */ 211#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 212#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 213 214#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 215#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ 216 217#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ 218#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ 219#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ 220/* 221 * The following defines are added for buggy IOP480 byte interface. 222 * All other boards should use the standard values (CPCI405 etc.) 223 */ 224#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ 225#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ 226#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ 227 228#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ 229 230#if 0 /* test-only */ 231#define CONFIG_SYS_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ 232#define CONFIG_SYS_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ 233#endif 234 235/*----------------------------------------------------------------------- 236 * Environment Variable setup 237 */ 238#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ 239#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ 240#define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ 241 /* total size of a CAT24WC16 is 2048 bytes */ 242 243#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ 244#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */ 245 246/*----------------------------------------------------------------------- 247 * I2C EEPROM (CAT24WC16) for environment 248 */ 249#define CONFIG_HARD_I2C /* I2c with hardware support */ 250#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ 251#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 252#define CONFIG_SYS_I2C_SLAVE 0x7F 253 254#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ 255#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ 256/* mask of address bits that overflow into the "EEPROM chip address" */ 257#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 258#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ 259 /* 16 byte page write mode using*/ 260 /* last 4 bits of the address */ 261#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ 262 263/* 264 * Init Memory Controller: 265 * 266 * BR0/1 and OR0/1 (FLASH) 267 */ 268 269#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ 270 271/*----------------------------------------------------------------------- 272 * External Bus Controller (EBC) Setup 273 */ 274 275/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ 276#define CONFIG_SYS_EBC_PB0AP 0x92015480 277/*#define CONFIG_SYS_EBC_PB0AP 0x08055880 /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */ 278#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ 279 280/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */ 281#define CONFIG_SYS_EBC_PB1AP 0x92015480 282#define CONFIG_SYS_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */ 283 284/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */ 285#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ 286#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ 287 288/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */ 289#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ 290#define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ 291 292#define CAN_BA 0xF0000000 /* CAN Base Address */ 293#define DUART0_BA 0xF0000400 /* DUART Base Address */ 294#define DUART1_BA 0xF0000408 /* DUART Base Address */ 295#define DUART2_BA 0xF0000410 /* DUART Base Address */ 296#define DUART3_BA 0xF0000418 /* DUART Base Address */ 297#define RTC_BA 0xF0000500 /* RTC Base Address */ 298#define CONFIG_SYS_NAND_BASE 0xF4000000 299 300/*----------------------------------------------------------------------- 301 * FPGA stuff 302 */ 303#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ 304#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/ 305 306/* FPGA program pin configuration */ 307#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ 308#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ 309#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ 310#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ 311#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ 312 313/*----------------------------------------------------------------------- 314 * Definitions for initial stack pointer and data area (in data cache) 315 */ 316/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ 317#define CONFIG_SYS_TEMP_STACK_OCM 1 318 319/* On Chip Memory location */ 320#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 321#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 322#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ 323#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ 324 325#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 326#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 327 328/*----------------------------------------------------------------------- 329 * Definitions for GPIO setup (PPC405EP specific) 330 * 331 * GPIO0[0] - External Bus Controller BLAST output 332 * GPIO0[1-9] - Instruction trace outputs -> GPIO 333 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs 334 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO 335 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs 336 * GPIO0[24-27] - UART0 control signal inputs/outputs 337 * GPIO0[28-29] - UART1 data signal input/output 338 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs 339 */ 340#define CONFIG_SYS_GPIO0_OSRL 0x40000550 341#define CONFIG_SYS_GPIO0_OSRH 0x00000110 342#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 343#define CONFIG_SYS_GPIO0_ISR1H 0x15555445 344#define CONFIG_SYS_GPIO0_TSRL 0x00000000 345#define CONFIG_SYS_GPIO0_TSRH 0x00000000 346#define CONFIG_SYS_GPIO0_TCR 0xF7FE0014 347 348#define CONFIG_SYS_DUART_RST (0x80000000 >> 14) 349 350/* 351 * Default speed selection (cpu_plb_opb_ebc) in mhz. 352 * This value will be set if iic boot eprom is disabled. 353 */ 354#if 0 355#define PLLMR0_DEFAULT PLLMR0_266_133_66_33 356#define PLLMR1_DEFAULT PLLMR1_266_133_66_33 357#endif 358#if 1 359#define PLLMR0_DEFAULT PLLMR0_200_100_50_33 360#define PLLMR1_DEFAULT PLLMR1_200_100_50_33 361#endif 362#if 0 363#define PLLMR0_DEFAULT PLLMR0_133_66_66_33 364#define PLLMR1_DEFAULT PLLMR1_133_66_66_33 365#endif 366 367#endif /* __CONFIG_H */ 368