LXR uboot/include/configs/BC3450.h

   1/*
   2 * -- Version 1.1 --
   3 *
   4 * (C) Copyright 2003-2005
   5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   6 *
   7 * (C) Copyright 2004-2005
   8 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
   9 *
  10 * (C) Copyright 2005
  11 * Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de.
  12 *
  13 * History:
  14 *      1.1 - add define CONFIG_ZERO_BOOTDELAY_CHECK
  15 *
  16 * See file CREDITS for list of people who contributed to this
  17 * project.
  18 *
  19 * This program is free software; you can redistribute it and/or
  20 * modify it under the terms of the GNU General Public License as
  21 * published by the Free Software Foundation; either version 2 of
  22 * the License, or (at your option) any later version.
  23 *
  24 * This program is distributed in the hope that it will be useful,
  25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  27 * GNU General Public License for more details.
  28 *
  29 * You should have received a copy of the GNU General Public License
  30 * along with this program; if not, write to the Free Software
  31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  32 * MA 02111-1307 USA
  33 */
  34
  35#ifndef __CONFIG_H
  36#define __CONFIG_H
  37
  38/*
  39 * High Level Configuration Options
  40 */
  41#define CONFIG_MPC5xxx          1       /* This is an MPC5xxx CPU           */
  42#define CONFIG_MPC5200          1       /* (more precisely a MPC5200 CPU)   */
  43#define CONFIG_TQM5200          1       /* ... on a TQM5200 module          */
  44
  45#define CONFIG_BC3450           1       /* ... on a BC3450 mainboard        */
  46#define CONFIG_BC3450_PS2       1       /*  + a PS/2 converter onboard      */
  47#define CONFIG_BC3450_IDE       1       /*  + IDE drives (Compact Flash)    */
  48#define CONFIG_BC3450_USB       1       /*  + USB support                   */
  49# define CONFIG_FAT             1       /*    + FAT support                 */
  50# define CONFIG_EXT2            1       /*    + EXT2 support                */
  51#undef CONFIG_BC3450_BUZZER             /*  + Buzzer onboard                */
  52#undef CONFIG_BC3450_CAN                /*  + CAN transceiver               */
  53#undef CONFIG_BC3450_DS1340             /*  + a RTC DS1340 onboard          */
  54#undef CONFIG_BC3450_DS3231             /*  + a RTC DS3231 onboard      tbd */
  55#undef CONFIG_BC3450_AC97               /*  + AC97 on PSC2,             tbd */
  56#define CONFIG_BC3450_FP        1       /*  + enable FP O/P                 */
  57#undef CONFIG_BC3450_CRT                /*  + enable CRT O/P (Debug only!)  */
  58
  59/*
  60 * Valid values for CONFIG_SYS_TEXT_BASE are:
  61 * 0xFC000000   boot low (standard configuration with room for
  62 *              max 64 MByte Flash ROM)
  63 * 0x00100000   boot from RAM (for testing only)
  64 */
  65#ifndef CONFIG_SYS_TEXT_BASE
  66#define CONFIG_SYS_TEXT_BASE    0xFC000000
  67#endif
  68
  69#define CONFIG_SYS_MPC5XXX_CLKIN        33000000 /* ... running at 33.000000MHz     */
  70
  71#define CONFIG_HIGH_BATS        1       /* High BATs supported              */
  72
  73/*
  74 * Serial console configuration
  75 */
  76#define CONFIG_PSC_CONSOLE      1       /* console is on PSC1           */
  77#define CONFIG_BAUDRATE         115200  /* ... at 115200 bps            */
  78#define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
  79
  80/*
  81 * AT-PS/2 Multiplexer
  82 */
  83#ifdef CONFIG_BC3450_PS2
  84# define CONFIG_PS2KBD                  /* AT-PS/2 Keyboard             */
  85# define CONFIG_PS2MULT                 /* .. on PS/2 Multiplexer       */
  86# define CONFIG_PS2SERIAL       6               /* .. on PSC6           */
  87# define CONFIG_PS2MULT_DELAY   (CONFIG_SYS_HZ/2)       /* Initial delay        */
  88# define CONFIG_BOARD_EARLY_INIT_R
  89#endif /* CONFIG_BC3450_PS2 */
  90
  91/*
  92 * PCI Mapping:
  93 * 0x40000000 - 0x4fffffff - PCI Memory
  94 * 0x50000000 - 0x50ffffff - PCI IO Space
  95 */
  96# define CONFIG_PCI             1
  97# define CONFIG_PCI_PNP         1
  98/* #define CONFIG_PCI_SCAN_SHOW 1 */
  99#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
 100
 101#define CONFIG_PCI_MEM_BUS      0x40000000
 102#define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
 103#define CONFIG_PCI_MEM_SIZE     0x10000000
 104
 105#define CONFIG_PCI_IO_BUS       0x50000000
 106#define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
 107#define CONFIG_PCI_IO_SIZE      0x01000000
 108
 109/*#define CONFIG_EEPRO100       XXX - FIXME: conflicts when CONFIG_MII is enabled */
 110#define CONFIG_SYS_RX_ETH_BUFFER        8       /* use 8 rx buffer on eepro100  */
 111#define CONFIG_NS8382X          1
 112
 113/*
 114 * Video console
 115 */
 116# define CONFIG_VIDEO
 117# define CONFIG_VIDEO_SM501
 118# define CONFIG_VIDEO_SM501_32BPP
 119# define CONFIG_CFB_CONSOLE
 120# define CONFIG_VIDEO_LOGO
 121# define CONFIG_VGA_AS_SINGLE_DEVICE
 122# define CONFIG_CONSOLE_EXTRA_INFO      /* display Board/Device-Infos */
 123# define CONFIG_VIDEO_SW_CURSOR
 124# define CONFIG_SPLASH_SCREEN
 125# define CONFIG_SYS_CONSOLE_IS_IN_ENV
 126
 127/*
 128 * Partitions
 129 */
 130#define CONFIG_MAC_PARTITION
 131#define CONFIG_DOS_PARTITION
 132#define CONFIG_ISO_PARTITION
 133
 134/*
 135 * USB
 136 */
 137#ifdef CONFIG_BC3450_USB
 138# define CONFIG_USB_OHCI
 139# define CONFIG_USB_STORAGE
 140#endif /* CONFIG_BC3450_USB */
 141
 142/*
 143 * POST support
 144 */
 145#define CONFIG_POST             (CONFIG_SYS_POST_MEMORY   | \
 146                                 CONFIG_SYS_POST_CPU       | \
 147                                 CONFIG_SYS_POST_I2C)
 148
 149#ifdef CONFIG_POST
 150/* preserve space for the post_word at end of on-chip SRAM */
 151# define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
 152#endif /* CONFIG_POST */
 153
 154
 155/*
 156 * BOOTP options
 157 */
 158#define CONFIG_BOOTP_BOOTFILESIZE
 159#define CONFIG_BOOTP_BOOTPATH
 160#define CONFIG_BOOTP_GATEWAY
 161#define CONFIG_BOOTP_HOSTNAME
 162
 163
 164/*
 165 * Command line configuration.
 166 */
 167#include <config_cmd_default.h>
 168
 169#define CONFIG_CMD_ASKENV
 170#define CONFIG_CMD_DATE
 171#define CONFIG_CMD_DHCP
 172#define CONFIG_CMD_ECHO
 173#define CONFIG_CMD_EEPROM
 174#define CONFIG_CMD_I2C
 175#define CONFIG_CMD_JFFS2
 176#define CONFIG_CMD_MII
 177#define CONFIG_CMD_NFS
 178#define CONFIG_CMD_PING
 179#define CONFIG_CMD_REGINFO
 180#define CONFIG_CMD_SNTP
 181#define CONFIG_CMD_BSP
 182
 183#ifdef CONFIG_VIDEO
 184    #define CONFIG_CMD_BMP
 185#endif
 186
 187#ifdef CONFIG_BC3450_IDE
 188    #define CONFIG_CMD_IDE
 189#endif
 190
 191#if defined(CONFIG_BC3450_IDE) || defined(CONFIG_BC3450_USB)
 192    #ifdef CONFIG_FAT
 193        #define CONFIG_CMD_FAT
 194    #endif
 195
 196    #ifdef CONFIG_EXT2
 197        #define CONFIG_CMD_EXT2
 198    #endif
 199#endif
 200
 201#ifdef CONFIG_BC3450_USB
 202    #define CONFIG_CMD_USB
 203#endif
 204
 205#ifdef CONFIG_PCI
 206    #define CONFIG_CMD_PCI
 207#endif
 208
 209#ifdef CONFIG_POST
 210    #define CONFIG_CMD_DIAG
 211#endif
 212
 213
 214#define CONFIG_TIMESTAMP                /* display image timestamps */
 215
 216#if (CONFIG_SYS_TEXT_BASE == 0xFC000000)                /* Boot low */
 217#   define CONFIG_SYS_LOWBOOT           1
 218#endif
 219
 220/*
 221 * Autobooting
 222 */
 223#define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
 224#define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 225
 226#define CONFIG_PREBOOT  "echo;" \
 227        "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 228        "echo;"
 229
 230#undef  CONFIG_BOOTARGS
 231
 232#define CONFIG_EXTRA_ENV_SETTINGS                                       \
 233        "netdev=eth0\0"                                                 \
 234        "ipaddr=192.168.1.10\0"                                         \
 235        "serverip=192.168.1.3\0"                                        \
 236        "netmask=255.255.255.0\0"                                       \
 237        "hostname=bc3450\0"                                             \
 238        "rootpath=/opt/eldk/ppc_6xx\0"                                  \
 239        "kernel_addr=fc0a0000\0"                                        \
 240        "ramdisk_addr=fc1c0000\0"                                       \
 241        "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 242        "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 243                "nfsroot=$(serverip):$(rootpath)\0"                     \
 244        "ideargs=setenv bootargs root=/dev/hda2 ro\0"                   \
 245        "addip=setenv bootargs $(bootargs) "                            \
 246                "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"      \
 247                ":$(hostname):$(netdev):off panic=1\0"                  \
 248        "addcons=setenv bootargs $(bootargs) "                          \
 249                "console=ttyS0,$(baudrate) console=tty0\0"              \
 250        "flash_self=run ramargs addip addcons;"                         \
 251                "bootm $(kernel_addr) $(ramdisk_addr)\0"                \
 252        "flash_nfs=run nfsargs addip addcons; bootm $(kernel_addr)\0"   \
 253        "net_nfs=tftp 200000 $(bootfile); "                             \
 254                "run nfsargs addip addcons; bootm\0"                    \
 255        "ide_nfs=run nfsargs addip addcons; "                           \
 256                "disk 200000 0:1; bootm\0"                              \
 257        "ide_ide=run ideargs addip addcons; "                           \
 258                "disk 200000 0:1; bootm\0"                              \
 259        "usb_self=run usbload; run ramargs addip addcons; "             \
 260                "bootm 200000 400000\0"                                 \
 261        "usbload=usb reset; usb scan; usbboot 200000 0:1; "             \
 262                "usbboot 400000 0:2\0"                                  \
 263        "bootfile=uImage\0"                                             \
 264        "load=tftp 200000 $(u-boot)\0"                                  \
 265        "u-boot=u-boot.bin\0"                                           \
 266        "update=protect off FC000000 FC05FFFF;"                         \
 267                "erase FC000000 FC05FFFF;"                              \
 268                "cp.b 200000 FC000000 $(filesize);"                     \
 269                "protect on FC000000 FC05FFFF\0"                        \
 270        ""
 271
 272#define CONFIG_BOOTCOMMAND      "run flash_self"
 273
 274/*
 275 * IPB Bus clocking configuration.
 276 */
 277#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK         /* define for 133MHz speed */
 278
 279/*
 280 * PCI Bus clocking configuration
 281 *
 282 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
 283 * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
 284 *  of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
 285 */
 286#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
 287# define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2   /* define for 66MHz speed */
 288#endif
 289
 290/*
 291 * I2C configuration
 292 */
 293#define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 294#define CONFIG_SYS_I2C_MODULE           2       /* Select I2C module #2 */
 295
 296/*
 297 * I2C clock frequency
 298 *
 299 * Please notice, that the resulting clock frequency could differ from the
 300 * configured value. This is because the I2C clock is derived from system
 301 * clock over a frequency divider with only a few divider values. U-boot
 302 * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
 303 * approximation allways lies below the configured value, never above.
 304 */
 305#define CONFIG_SYS_I2C_SPEED            100000 /* 100 kHz */
 306#define CONFIG_SYS_I2C_SLAVE            0x7F
 307
 308/*
 309 * EEPROM configuration for I²C EEPROM M24C32
 310 * M24C64 should work also. For other EEPROMs config should be verified.
 311 *
 312 * The TQM5200 module may hold an EEPROM at address 0x50.
 313 */
 314#define CONFIG_SYS_I2C_EEPROM_ADDR              0x50    /* 1010000x (TQM) */
 315#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 316#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       5       /* =32 Bytes per write */
 317#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   70
 318
 319/*
 320 * RTC configuration
 321 */
 322#if defined (CONFIG_BC3450_DS1340) && !defined (CONFIG_BC3450_DS3231)
 323# define CONFIG_RTC_M41T11      1
 324# define CONFIG_SYS_I2C_RTC_ADDR        0x68
 325#else
 326# define CONFIG_RTC_MPC5200     1       /* use MPC5200 internal RTC */
 327# define CONFIG_BOARD_EARLY_INIT_R
 328#endif
 329
 330/*
 331 * Flash configuration
 332 */
 333#define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_TEXT_BASE /* 0xFC000000 */
 334
 335/* use CFI flash driver if no module variant is spezified */
 336#define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant */
 337#define CONFIG_FLASH_CFI_DRIVER 1       /* Use the common driver */
 338#define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_BOOTCS_START }
 339#define CONFIG_SYS_FLASH_EMPTY_INFO
 340#define CONFIG_SYS_FLASH_SIZE           0x04000000 /* 64 MByte */
 341#define CONFIG_SYS_MAX_FLASH_SECT       512     /* max num of sects on one chip */
 342#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE        /* not supported yet for AMD */
 343
 344#if !defined(CONFIG_SYS_LOWBOOT)
 345#define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000)
 346#else   /* CONFIG_SYS_LOWBOOT */
 347#define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x00060000)
 348#endif  /* CONFIG_SYS_LOWBOOT */
 349#define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of flash banks
 350                                           (= chip selects) */
 351#define CONFIG_SYS_FLASH_ERASE_TOUT     240000  /* Flash Erase Timeout (in ms)  */
 352#define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (in ms)  */
 353
 354/* Dynamic MTD partition support */
 355#define CONFIG_CMD_MTDPARTS
 356#define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
 357#define CONFIG_FLASH_CFI_MTD
 358#define MTDIDS_DEFAULT          "nor0=TQM5200-0"
 359#define MTDPARTS_DEFAULT        "mtdparts=TQM5200-0:640k(firmware),"    \
 360                                                "1408k(kernel),"        \
 361                                                "2m(initrd),"           \
 362                                                "4m(small-fs),"         \
 363                                                "16m(big-fs),"          \
 364                                                "8m(misc)"
 365
 366/*
 367 * Environment settings
 368 */
 369#define CONFIG_ENV_IS_IN_FLASH  1
 370#define CONFIG_ENV_SIZE         0x10000
 371#define CONFIG_ENV_SECT_SIZE    0x20000
 372#define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 373#define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 374
 375/*
 376 * Memory map
 377 */
 378#define CONFIG_SYS_MBAR         0xF0000000
 379#define CONFIG_SYS_SDRAM_BASE           0x00000000
 380#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
 381
 382/* Use ON-Chip SRAM until RAM will be available */
 383#define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 384#ifdef CONFIG_POST
 385/* preserve space for the post_word at end of on-chip SRAM */
 386# define CONFIG_SYS_INIT_RAM_SIZE       MPC5XXX_SRAM_POST_SIZE
 387#else
 388# define CONFIG_SYS_INIT_RAM_SIZE       MPC5XXX_SRAM_SIZE
 389#endif /*CONFIG_POST*/
 390
 391#define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 392#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 393
 394#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 395#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 396#   define CONFIG_SYS_RAMBOOT           1
 397#endif
 398
 399#define CONFIG_SYS_MONITOR_LEN          (384 << 10) /* Reserve 384 kB for Monitor   */
 400#define CONFIG_SYS_MALLOC_LEN           (128 << 10) /* Reserve 128 kB for malloc()  */
 401#define CONFIG_SYS_BOOTMAPSZ            (8 << 20)   /* Initial Memory map for Linux */
 402
 403/*
 404 * Ethernet configuration
 405 *
 406 * Define CONFIG_MPC5xxx_MII10 to force FEC at 10MBIT
 407 */
 408#define CONFIG_MPC5xxx_FEC      1
 409#define CONFIG_MPC5xxx_FEC_MII100
 410#undef CONFIG_MPC5xxx_MII10
 411#define CONFIG_PHY_ADDR         0x00
 412
 413/*
 414 * GPIO configuration on BC3450
 415 *
 416 *  PSC1:   UART1 (Service-UART)         [0x xxxxxxx4]
 417 *  PSC2:   UART2                        [0x xxxxxx4x]
 418 *    or:   AC/97 if CONFIG_BC3450_AC97  [0x xxxxxx2x]
 419 *  PSC3:   USB2                         [0x xxxxx1xx]
 420 *  USB:    UART4(ext.)/UART5(int.)      [0x xxxx2xxx]
 421 *            (this has to match
 422 *            CONFIG_USB_CONFIG which is
 423 *            used by usb_ohci.c to set
 424 *            the USB ports)
 425 *  Eth:    10/100Mbit Ethernet          [0x xxx0xxxx]
 426 *            (this is reset to '5'
 427 *            in FEC driver: fec.c)
 428 *  PSC6:   UART6 (int. to PS/2 contr.)  [0x xx5xxxxx]
 429 *  ATA/CS: ???                          [0x x1xxxxxx]
 430 *          FIXME! UM Fig 2-10 suggests  [0x x0xxxxxx]
 431 *  CS1:    Use Pin gpio_wkup_6 as second
 432 *          SDRAM chip select (mem_cs1)
 433 *  Timer:  CAN2 / SPI
 434 *  I2C:    CAN1 / I²C2           [0x bxxxxxxx]
 435 */
 436#ifdef CONFIG_BC3450_AC97
 437# define CONFIG_SYS_GPS_PORT_CONFIG     0xb1502124
 438#else /* PSC2=UART2 */
 439# define CONFIG_SYS_GPS_PORT_CONFIG     0xb1502144
 440#endif
 441
 442/*
 443 * Miscellaneous configurable options
 444 */
 445#define CONFIG_SYS_LONGHELP                             /* undef to save memory     */
 446#define CONFIG_SYS_PROMPT               "=> "           /* Monitor Command Prompt   */
 447#if defined(CONFIG_CMD_KGDB)
 448#define CONFIG_SYS_CBSIZE               1024            /* Console I/O Buffer Size  */
 449#else
 450#define CONFIG_SYS_CBSIZE               256             /* Console I/O Buffer Size  */
 451#endif
 452#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size  */
 453#define CONFIG_SYS_MAXARGS              16              /* max no of command args   */
 454#define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Arg. Buffer Size    */
 455
 456#define CONFIG_SYS_ALT_MEMTEST                          /* Enable an alternative,   */
 457                                                /*  more extensive mem test */
 458
 459#define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on         */
 460#define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 1 ... 15 MB in DRAM      */
 461
 462#define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address     */
 463
 464#define CONFIG_SYS_HZ                   1000            /* dec freq: 1ms ticks      */
 465
 466#define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC5xxx CPUs                 */
 467#if defined(CONFIG_CMD_KGDB)
 468#  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value    */
 469#endif
 470
 471/*
 472 * Enable loopw command.
 473 */
 474#define CONFIG_LOOPW
 475
 476/*
 477 * Various low-level settings
 478 */
 479#define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 480#define CONFIG_SYS_HID0_FINAL           HID0_ICE
 481
 482#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
 483#define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 484#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
 485# define CONFIG_SYS_BOOTCS_CFG          0x0008DF30      /* for pci_clk  = 66 MHz */
 486#else
 487# define CONFIG_SYS_BOOTCS_CFG          0x0004DF30      /* for pci_clk = 33 MHz  */
 488#endif
 489#define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 490#define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 491
 492/* automatic configuration of chip selects */
 493#ifdef CONFIG_TQM5200
 494# define CONFIG_LAST_STAGE_INIT
 495#endif /* CONFIG_TQM5200 */
 496
 497/*
 498 * SRAM - Do not map below 2 GB in address space, because this area is used
 499 * for SDRAM autosizing.
 500 */
 501#ifdef CONFIG_TQM5200
 502# define CONFIG_SYS_CS2_START           0xE5000000
 503# define CONFIG_SYS_CS2_SIZE            0x100000        /* 1 MByte */
 504# define CONFIG_SYS_CS2_CFG             0x0004D930
 505#endif /* CONFIG_TQM5200 */
 506
 507/*
 508 * Grafic controller - Do not map below 2 GB in address space, because this
 509 * area is used for SDRAM autosizing.
 510 */
 511#ifdef CONFIG_TQM5200
 512# define SM501_FB_BASE          0xE0000000
 513# define CONFIG_SYS_CS1_START           (SM501_FB_BASE)
 514# define CONFIG_SYS_CS1_SIZE            0x4000000       /* 64 MByte */
 515# define CONFIG_SYS_CS1_CFG             0x8F48FF70
 516# define SM501_MMIO_BASE        CONFIG_SYS_CS1_START + 0x03E00000
 517#endif /* CONFIG_TQM5200 */
 518
 519#define CONFIG_SYS_CS_BURST             0x00000000
 520#define CONFIG_SYS_CS_DEADCYCLE 0x33333311      /* 1 dead cycle for     */
 521                                                /*  flash and SM501     */
 522
 523#define CONFIG_SYS_RESET_ADDRESS        0xff000000
 524
 525/*
 526 * USB stuff
 527 */
 528#define CONFIG_USB_CLOCK        0x0001BBBB
 529#define CONFIG_USB_CONFIG       0x00002000      /* we're using Port 2   */
 530
 531/*
 532 * IDE/ATA stuff Supports IDE harddisk
 533 */
 534#undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
 535
 536#undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE     not supported */
 537#undef  CONFIG_IDE_LED                  /* LED for ide    not supported */
 538
 539#define CONFIG_IDE_RESET                /* reset for ide      supported */
 540#define CONFIG_IDE_PREINIT
 541
 542#define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 543#define CONFIG_SYS_IDE_MAXDEVICE        2       /* max. 2 drives per IDE bus    */
 544
 545#define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 546
 547#define CONFIG_SYS_ATA_BASE_ADDR        MPC5XXX_ATA
 548
 549/* Offset for data I/O */
 550#define CONFIG_SYS_ATA_DATA_OFFSET      (0x0060)
 551
 552/* Offset for normal register accesses */
 553#define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_ATA_DATA_OFFSET)
 554
 555/* Offset for alternate registers */
 556#define CONFIG_SYS_ATA_ALT_OFFSET       (0x005C)
 557
 558/* Interval between registers */
 559#define CONFIG_SYS_ATA_STRIDE           4
 560
 561#endif /* __CONFIG_H */
 562