1/* 2 * (C) Copyright 2005 3 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* 25 * CMS700.h - configuration options, board specific 26 */ 27 28#ifndef __CONFIG_H 29#define __CONFIG_H 30 31/* 32 * High Level Configuration Options 33 * (easy to change) 34 */ 35 36#define CONFIG_405EP 1 /* This is a PPC405 CPU */ 37#define CONFIG_4xx 1 /* ...member of PPC4xx family */ 38#define CONFIG_VOM405 1 /* ...on a VOM405 board */ 39 40#define CONFIG_SYS_TEXT_BASE 0xFFFC8000 41 42#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ 43#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ 44 45#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ 46 47#define CONFIG_BAUDRATE 9600 48#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ 49 50#undef CONFIG_BOOTARGS 51#undef CONFIG_BOOTCOMMAND 52 53#define CONFIG_PREBOOT /* enable preboot variable */ 54 55#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 56 57#define CONFIG_PPC4xx_EMAC 58#undef CONFIG_HAS_ETH1 59 60#define CONFIG_MII 1 /* MII PHY management */ 61#define CONFIG_PHY_ADDR 0 /* PHY address */ 62#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ 63#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ 64 65/* 66 * BOOTP options 67 */ 68#define CONFIG_BOOTP_SUBNETMASK 69#define CONFIG_BOOTP_GATEWAY 70#define CONFIG_BOOTP_HOSTNAME 71#define CONFIG_BOOTP_BOOTPATH 72#define CONFIG_BOOTP_DNS 73#define CONFIG_BOOTP_DNS2 74#define CONFIG_BOOTP_SEND_HOSTNAME 75 76 77/* 78 * Command line configuration. 79 */ 80#include <config_cmd_default.h> 81 82#define CONFIG_CMD_DHCP 83#define CONFIG_CMD_BSP 84#define CONFIG_CMD_ELF 85#define CONFIG_CMD_NAND 86#define CONFIG_CMD_I2C 87#define CONFIG_CMD_DATE 88#define CONFIG_CMD_MII 89#define CONFIG_CMD_PING 90#define CONFIG_CMD_EEPROM 91 92 93#undef CONFIG_WATCHDOG /* watchdog disabled */ 94 95#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ 96 97#undef CONFIG_PRAM /* no "protected RAM" */ 98 99/* 100 * Miscellaneous configurable options 101 */ 102#define CONFIG_SYS_LONGHELP /* undef to save memory */ 103#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 104 105#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 106 107#if defined(CONFIG_CMD_KGDB) 108#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 109#else 110#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 111#endif 112#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 113#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 114#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 115 116#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ 117 118#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ 119 120#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 121#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 122 123#define CONFIG_CONS_INDEX 2 /* Use UART1 */ 124#define CONFIG_SYS_NS16550 125#define CONFIG_SYS_NS16550_SERIAL 126#define CONFIG_SYS_NS16550_REG_SIZE 1 127#define CONFIG_SYS_NS16550_CLK get_serial_clock() 128 129#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ 130#define CONFIG_SYS_BASE_BAUD 691200 131 132/* The following table includes the supported baudrates */ 133#define CONFIG_SYS_BAUDRATE_TABLE \ 134 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ 135 57600, 115200, 230400, 460800, 921600 } 136 137#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 138#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ 139 140#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 141 142#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ 143 144#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ 145 146#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ 147 148/*----------------------------------------------------------------------- 149 * RTC stuff 150 *----------------------------------------------------------------------- 151 */ 152#define CONFIG_RTC_DS1337 153#define CONFIG_SYS_I2C_RTC_ADDR 0x68 154 155/*----------------------------------------------------------------------- 156 * NAND-FLASH stuff 157 *----------------------------------------------------------------------- 158 */ 159#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 160#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ 161#define NAND_BIG_DELAY_US 25 162 163#define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ 164#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ 165#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ 166#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ 167 168#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ 169#define CONFIG_SYS_NAND_QUIET 1 170 171/* 172 * For booting Linux, the board info and command line data 173 * have to be in the first 8 MB of memory, since this is 174 * the maximum mapped by the Linux kernel during initialization. 175 */ 176#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 177/*----------------------------------------------------------------------- 178 * FLASH organization 179 */ 180#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ 181 182#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 183#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 184 185#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 186#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ 187 188#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ 189#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ 190#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ 191/* 192 * The following defines are added for buggy IOP480 byte interface. 193 * All other boards should use the standard values (CPCI405 etc.) 194 */ 195#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ 196#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ 197#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ 198 199#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ 200 201/*----------------------------------------------------------------------- 202 * Start addresses for the final memory configuration 203 * (Set up by the startup code) 204 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 205 */ 206#define CONFIG_SYS_SDRAM_BASE 0x00000000 207#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE 208#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 209#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1) 210#define CONFIG_SYS_MALLOC_LEN (256 * 1024) 211 212#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM) 213# define CONFIG_SYS_RAMBOOT 1 214#else 215# undef CONFIG_SYS_RAMBOOT 216#endif 217 218/*----------------------------------------------------------------------- 219 * Environment Variable setup 220 */ 221#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ 222#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ 223#define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ 224 /* total size of a CAT24WC16 is 2048 bytes */ 225 226/*----------------------------------------------------------------------- 227 * I2C EEPROM (CAT24WC16) for environment 228 */ 229#define CONFIG_HARD_I2C /* I2c with hardware support */ 230#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ 231#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ 232#define CONFIG_SYS_I2C_SLAVE 0x7F 233 234#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ 235#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ 236/* mask of address bits that overflow into the "EEPROM chip address" */ 237#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 238#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ 239 /* 16 byte page write mode using*/ 240 /* last 4 bits of the address */ 241#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ 242 243#define CONFIG_SYS_EEPROM_WREN 1 244 245/*----------------------------------------------------------------------- 246 * External Bus Controller (EBC) Setup 247 */ 248#define CONFIG_SYS_PLD_BASE 0xf0000000 249#define CONFIG_SYS_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */ 250 251/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ 252#define CONFIG_SYS_EBC_PB0AP 0x92015480 253#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ 254 255/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */ 256#define CONFIG_SYS_EBC_PB1AP 0x92015480 257#define CONFIG_SYS_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */ 258 259/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */ 260#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ 261#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ 262 263/*----------------------------------------------------------------------- 264 * FPGA stuff 265 */ 266#define CONFIG_SYS_XSVF_DEFAULT_ADDR 0xfffc0000 267 268/* FPGA program pin configuration */ 269#define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */ 270#define CONFIG_SYS_FPGA_CLK 0x02000000 /* JTAG TCK pin (ppc output) */ 271#define CONFIG_SYS_FPGA_DATA 0x01000000 /* JTAG TDO->TDI data pin (ppc output) */ 272#define CONFIG_SYS_FPGA_INIT 0x00010000 /* unused (ppc input) */ 273#define CONFIG_SYS_FPGA_DONE 0x00008000 /* JTAG TDI->TDO pin (ppc input) */ 274 275/*----------------------------------------------------------------------- 276 * Definitions for initial stack pointer and data area (in data cache) 277 */ 278/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ 279#define CONFIG_SYS_TEMP_STACK_OCM 1 280 281/* On Chip Memory location */ 282#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 283#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 284#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ 285#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ 286 287#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 288#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 289 290/*----------------------------------------------------------------------- 291 * Definitions for GPIO setup (PPC405EP specific) 292 * 293 * GPIO0[0] - External Bus Controller BLAST output 294 * GPIO0[1-9] - Instruction trace outputs -> GPIO 295 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs 296 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO 297 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs 298 * GPIO0[24-27] - UART0 control signal inputs/outputs 299 * GPIO0[28-29] - UART1 data signal input/output 300 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs 301 */ 302/* GPIO Input: OSR=00, ISR=00, TSR=00, TCR=0 */ 303/* GPIO Output: OSR=00, ISR=00, TSR=00, TCR=1 */ 304/* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */ 305/* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */ 306#define CONFIG_SYS_GPIO0_OSRL 0x40000500 /* 0 ... 15 */ 307#define CONFIG_SYS_GPIO0_OSRH 0x00000110 /* 16 ... 31 */ 308#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 /* 0 ... 15 */ 309#define CONFIG_SYS_GPIO0_ISR1H 0x14000045 /* 16 ... 31 */ 310#define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 0 ... 15 */ 311#define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 16 ... 31 */ 312#define CONFIG_SYS_GPIO0_TCR 0xF7FE0014 /* 0 ... 31 */ 313 314#define CONFIG_SYS_EEPROM_WP (0x80000000 >> 8) /* GPIO8 */ 315#define CONFIG_SYS_PLD_RESET (0x80000000 >> 12) /* GPIO12 */ 316 317/* 318 * Default speed selection (cpu_plb_opb_ebc) in mhz. 319 * This value will be set if iic boot eprom is disabled. 320 */ 321#define PLLMR0_DEFAULT PLLMR0_133_66_66_33 322#define PLLMR1_DEFAULT PLLMR1_133_66_66_33 323 324#endif /* __CONFIG_H */ 325