1 /* 2 * A collection of structures, addresses, and values associated with 3 * the Motorola 860T FADS board. Copied from the MBX stuff. 4 * Magnus Damm added defines for 8xxrom and extended bd_info. 5 * Helmut Buchsbaum added bitvalues for BCSRx 6 * 7 * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) 8 */ 9 10/* 11 * 1999-nov-26: The FADS is using the following physical memorymap: 12 * 13 * ff020000 -> ff02ffff : pcmcia io remapping 14 * ff010000 -> ff01ffff : BCSR connected to CS1, setup by U-Boot 15 * ff000000 -> ff00ffff : IMAP internal in the cpu 16 * e0000000 -> f3ffffff : pcmcia memory remapping by m8xx_pcmcia 17 * fe000000 -> fe1fffff : flash connected to CS0, setup by U-Boot 18 * 00000000 -> nnnnnnnn : sdram/dram setup by U-Boot 19*/ 20 21#define CONFIG_SYS_PCMCIA_IO_ADDR 0xff020000 22#define CONFIG_SYS_PCMCIA_IO_SIZE 0x10000 23#define CONFIG_SYS_PCMCIA_MEM_ADDR 0xe0000000 24#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x10000 25#define CONFIG_SYS_IMMR 0xFF000000 26#define CONFIG_SYS_SDRAM_SIZE (4<<20) /* standard FADS has 4M */ 27#define CONFIG_SYS_SDRAM_BASE 0x00000000 28#define CONFIG_SYS_FLASH_BASE 0x02800000 29#define BCSR_ADDR ((uint) 0xff010000) 30#define FLASH_BASE0_PRELIM 0x02800000 /* FLASH bank #0 */ 31 32/* ------------------------------------------------------------------------- */ 33 34/* 35 * board/config.h - configuration options, board specific 36 */ 37 38#ifndef __CONFIG_H 39#define __CONFIG_H 40 41#define CONFIG_SYS_TEXT_BASE 0xFE000000 42 43#define CONFIG_ETHADDR 08:00:22:50:70:63 /* Ethernet address */ 44#define CONFIG_ENV_OVERWRITE 1 /* Overwrite the environment */ 45 46#define CONFIG_VIDEO 1 /* To enable video controller support */ 47#define CONFIG_HARD_I2C 1 /* To I2C with hardware support */ 48#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 49#define CONFIG_SYS_I2C_SLAVE 0x7F 50 51/*#define CONFIG_PCMCIA 1 / * To enable PCMCIA support */ 52 53/* Video related */ 54 55#define CONFIG_VIDEO_LOGO 1 /* Show the logo */ 56#define CONFIG_VIDEO_ENCODER_AD7176 1 /* Enable this encoder */ 57#define CONFIG_VIDEO_ENCODER_AD7176_ADDR 0x54 /* Default on fads */ 58#define CONFIG_VIDEO_SIZE (2*1024*1024) 59/* #define CONFIG_VIDEO_ADDR (gd->bd->bi_memsize - CONFIG_VIDEO_SIZE) Frame buffer address */ 60 61/* Wireless 56Khz 4PPM keyboard on SMCx */ 62 63/*#define CONFIG_KEYBOARD 1 */ 64#define CONFIG_WL_4PPM_KEYBOARD_SMC 0 /* SMC to use (0 indexed) */ 65 66/* 67 * High Level Configuration Options 68 * (easy to change) 69 */ 70#define CONFIG_MPC823 1 71#define CONFIG_MPC823FADS 1 72#define CONFIG_FADS 1 73 74#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 75#undef CONFIG_8xx_CONS_SMC2 76#undef CONFIG_8xx_CONS_NONE 77#define CONFIG_BAUDRATE 115200 78 79/* Set the CPU speed to 50Mhz on the FADS */ 80 81#if 0 82#define MPC8XX_FACT 10 /* Multiply by 10 */ 83#define MPC8XX_XIN 5000000 /* 5 MHz in */ 84#else 85#define MPC8XX_FACT 10 /* Multiply by 10 */ 86#define MPC8XX_XIN 5000000 /* 5 MHz in */ 87#define CONFIG_SYS_PLPRCR_MF (MPC8XX_FACT-1) << 20 /* From 0 to 4095 */ 88#endif 89#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) 90 91#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ 92 93#if 1 94#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ 95#define CONFIG_LOADS_ECHO 0 /* Dont echoes received characters */ 96#define CONFIG_BOOTARGS "" 97#define CONFIG_BOOTCOMMAND \ 98"bootp ;" \ 99"setenv bootargs console=tty0 console=ttyS0 " \ 100"root=/dev/nfs nfsroot=${serverip}:${rootpath} " \ 101"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off ;" \ 102"bootm" 103#else 104#define CONFIG_BOOTDELAY 0 /* autoboot disabled */ 105#endif 106 107#undef CONFIG_WATCHDOG /* watchdog disabled */ 108 109 110/* 111 * BOOTP options 112 */ 113#define CONFIG_BOOTP_SUBNETMASK 114#define CONFIG_BOOTP_GATEWAY 115#define CONFIG_BOOTP_HOSTNAME 116#define CONFIG_BOOTP_BOOTPATH 117#define CONFIG_BOOTP_BOOTFILESIZE 118#define CONFIG_BOOTP_SUBNETMASK 119#define CONFIG_BOOTP_GATEWAY 120#define CONFIG_BOOTP_HOSTNAME 121#define CONFIG_BOOTP_NISDOMAIN 122#define CONFIG_BOOTP_BOOTPATH 123#define CONFIG_BOOTP_DNS 124#define CONFIG_BOOTP_DNS2 125#define CONFIG_BOOTP_SEND_HOSTNAME 126#define CONFIG_BOOTP_NTPSERVER 127#define CONFIG_BOOTP_TIMEOFFSET 128 129 130/* 131 * Command line configuration. 132 */ 133#include <config_cmd_default.h> 134 135 136/* 137 * Miscellaneous configurable options 138 */ 139#define CONFIG_SYS_LONGHELP /* undef to save memory */ 140#define CONFIG_SYS_PROMPT ":>" /* Monitor Command Prompt */ 141#if defined(CONFIG_CMD_KGDB) 142#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 143#else 144#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 145#endif 146#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 147#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 148#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 149 150#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ 151#define CONFIG_SYS_MEMTEST_END 0x01000000 /* 0 ... 16 MB in DRAM */ 152 153#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ 154 155#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 156 157/* 158 * Low Level Configuration Settings 159 * (address mappings, register initial values, etc.) 160 * You should know what you are doing if you make changes here. 161 */ 162/*----------------------------------------------------------------------- 163 * Internal Memory Mapped Register 164 */ 165#define CONFIG_SYS_IMMR_SIZE ((uint)(64 * 1024)) 166 167/*----------------------------------------------------------------------- 168 * Definitions for initial stack pointer and data area (in DPRAM) 169 */ 170#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 171#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ 172#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 173#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 174 175/*----------------------------------------------------------------------- 176 * Start addresses for the final memory configuration 177 * (Set up by the startup code) 178 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 179 * Also NOTE that it doesn't mean SDRAM - it means MEMORY. 180 */ 181#define CONFIG_SYS_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */ 182#if 0 183#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 184#else 185#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ 186#endif 187#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 188#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 189 190/* 191 * For booting Linux, the board info and command line data 192 * have to be in the first 8 MB of memory, since this is 193 * the maximum mapped by the Linux kernel during initialization. 194 */ 195#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 196/*----------------------------------------------------------------------- 197 * FLASH organization 198 */ 199#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 200#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ 201 202#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 203#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 204 205#define CONFIG_ENV_IS_IN_FLASH 1 206#define CONFIG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */ 207#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ 208#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ 209 210/*----------------------------------------------------------------------- 211 * Cache Configuration 212 */ 213#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 214#if defined(CONFIG_CMD_KGDB) 215#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 216#endif 217 218/*----------------------------------------------------------------------- 219 * SYPCR - System Protection Control 11-9 220 * SYPCR can only be written once after reset! 221 *----------------------------------------------------------------------- 222 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 223 */ 224#if defined(CONFIG_WATCHDOG) 225#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 226 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 227#else 228#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 229#endif 230 231/*----------------------------------------------------------------------- 232 * SIUMCR - SIU Module Configuration 11-6 233 *----------------------------------------------------------------------- 234 * PCMCIA config., multi-function pin tri-state 235 */ 236#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 237 238/*----------------------------------------------------------------------- 239 * TBSCR - Time Base Status and Control 11-26 240 *----------------------------------------------------------------------- 241 * Clear Reference Interrupt Status, Timebase freezing enabled 242 */ 243#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) 244 245/*----------------------------------------------------------------------- 246 * PISCR - Periodic Interrupt Status and Control 11-31 247 *----------------------------------------------------------------------- 248 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 249 */ 250#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 251 252/*----------------------------------------------------------------------- 253 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 254 *----------------------------------------------------------------------- 255 * Reset PLL lock status sticky bit, timer expired status bit and timer * 256 * interrupt status bit - leave PLL multiplication factor unchanged ! 257 */ 258#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | CONFIG_SYS_PLPRCR_MF) 259 260/*----------------------------------------------------------------------- 261 * SCCR - System Clock and reset Control Register 15-27 262 *----------------------------------------------------------------------- 263 * Set clock output, timebase and RTC source and divider, 264 * power management and some other internal clocks 265 */ 266#define SCCR_MASK SCCR_EBDF11 267#define CONFIG_SYS_SCCR (SCCR_TBS | \ 268 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 269 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 270 SCCR_DFALCD00) 271 272 /*----------------------------------------------------------------------- 273 * 274 *----------------------------------------------------------------------- 275 * 276 */ 277#define CONFIG_SYS_DER 0 278 279/* Because of the way the 860 starts up and assigns CS0 the 280* entire address space, we have to set the memory controller 281* differently. Normally, you write the option register 282* first, and then enable the chip select by writing the 283* base register. For CS0, you must write the base register 284* first, followed by the option register. 285*/ 286 287/* 288 * Init Memory Controller: 289 * 290 * BR0/1 and OR0/1 (FLASH) 291 */ 292/* the other CS:s are determined by looking at parameters in BCSRx */ 293 294#define BCSR_SIZE ((uint)(64 * 1024)) 295 296#define FLASH_BASE1_PRELIM 0x00000000 /* FLASH bank #1 */ 297 298#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 299#define CONFIG_SYS_PRELIM_OR_AM 0xFFE00000 /* OR addr mask */ 300 301/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ 302#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) 303 304#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 305#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) /* 1 Mbyte until detected and only 1 Mbyte is needed*/ 306#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) 307 308/* BCSRx - Board Control and Status Registers */ 309#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP 310#define CONFIG_SYS_OR1_PRELIM 0xffff8110 /* 64Kbyte address space */ 311#define CONFIG_SYS_BR1_PRELIM ((BCSR_ADDR) | BR_V ) 312 313 314/* 315 * Memory Periodic Timer Prescaler 316 */ 317 318/* periodic timer for refresh */ 319#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */ 320 321/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ 322#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 323#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 324 325/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 326#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 327#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 328 329/* 330 * MAMR settings for SDRAM 331 */ 332 333/* 8 column SDRAM */ 334#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 335 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 336 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 337/* 9 column SDRAM */ 338#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 339 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 340 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 341 342#define CONFIG_SYS_MAMR 0x13a01114 343 344/* values according to the manual */ 345 346#define BCSR0 ((uint) (BCSR_ADDR + 00)) 347#define BCSR1 ((uint) (BCSR_ADDR + 0x04)) 348#define BCSR2 ((uint) (BCSR_ADDR + 0x08)) 349#define BCSR3 ((uint) (BCSR_ADDR + 0x0c)) 350#define BCSR4 ((uint) (BCSR_ADDR + 0x10)) 351 352/* FADS bitvalues by Helmut Buchsbaum 353 * see MPC8xxADS User's Manual for a proper description 354 * of the following structures 355 */ 356 357#define BCSR0_ERB ((uint)0x80000000) 358#define BCSR0_IP ((uint)0x40000000) 359#define BCSR0_BDIS ((uint)0x10000000) 360#define BCSR0_BPS_MASK ((uint)0x0C000000) 361#define BCSR0_ISB_MASK ((uint)0x01800000) 362#define BCSR0_DBGC_MASK ((uint)0x00600000) 363#define BCSR0_DBPC_MASK ((uint)0x00180000) 364#define BCSR0_EBDF_MASK ((uint)0x00060000) 365 366#define BCSR1_FLASH_EN ((uint)0x80000000) 367#define BCSR1_DRAM_EN ((uint)0x40000000) 368#define BCSR1_ETHEN ((uint)0x20000000) 369#define BCSR1_IRDEN ((uint)0x10000000) 370#define BCSR1_FLASH_CFG_EN ((uint)0x08000000) 371#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000) 372#define BCSR1_BCSR_EN ((uint)0x02000000) 373#define BCSR1_RS232EN_1 ((uint)0x01000000) 374#define BCSR1_PCCEN ((uint)0x00800000) 375#define BCSR1_PCCVCC0 ((uint)0x00400000) 376#define BCSR1_PCCVPP_MASK ((uint)0x00300000) 377#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000) 378#define BCSR1_RS232EN_2 ((uint)0x00040000) 379#define BCSR1_SDRAM_EN ((uint)0x00020000) 380#define BCSR1_PCCVCC1 ((uint)0x00010000) 381 382#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000) 383#define BCSR2_FLASH_PD_SHIFT 28 384#define BCSR2_DRAM_PD_MASK ((uint)0x07800000) 385#define BCSR2_DRAM_PD_SHIFT 23 386#define BCSR2_EXTTOLI_MASK ((uint)0x00780000) 387#define BCSR2_DBREVNR_MASK ((uint)0x00030000) 388 389#define BCSR3_DBID_MASK ((ushort)0x3800) 390#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400) 391#define BCSR3_BREVNR0 ((ushort)0x0080) 392#define BCSR3_FLASH_PD_MASK ((ushort)0x0070) 393#define BCSR3_BREVN1 ((ushort)0x0008) 394#define BCSR3_BREVN2_MASK ((ushort)0x0003) 395 396#define BCSR4_ETHLOOP ((uint)0x80000000) 397#define BCSR4_TFPLDL ((uint)0x40000000) 398#define BCSR4_TPSQEL ((uint)0x20000000) 399#define BCSR4_SIGNAL_LAMP ((uint)0x10000000) 400#ifdef CONFIG_MPC823 401#define BCSR4_USB_EN ((uint)0x08000000) 402#endif /* CONFIG_MPC823 */ 403#ifdef CONFIG_MPC860SAR 404#define BCSR4_UTOPIA_EN ((uint)0x08000000) 405#endif /* CONFIG_MPC860SAR */ 406#ifdef CONFIG_MPC860T 407#define BCSR4_FETH_EN ((uint)0x08000000) 408#endif /* CONFIG_MPC860T */ 409#ifdef CONFIG_MPC823 410#define BCSR4_USB_SPEED ((uint)0x04000000) 411#endif /* CONFIG_MPC823 */ 412#ifdef CONFIG_MPC860T 413#define BCSR4_FETHCFG0 ((uint)0x04000000) 414#endif /* CONFIG_MPC860T */ 415#ifdef CONFIG_MPC823 416#define BCSR4_VCCO ((uint)0x02000000) 417#endif /* CONFIG_MPC823 */ 418#ifdef CONFIG_MPC860T 419#define BCSR4_FETHFDE ((uint)0x02000000) 420#endif /* CONFIG_MPC860T */ 421#ifdef CONFIG_MPC823 422#define BCSR4_VIDEO_ON ((uint)0x00800000) 423#endif /* CONFIG_MPC823 */ 424#ifdef CONFIG_MPC823 425#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000) 426#endif /* CONFIG_MPC823 */ 427#ifdef CONFIG_MPC860T 428#define BCSR4_FETHCFG1 ((uint)0x00400000) 429#endif /* CONFIG_MPC860T */ 430#ifdef CONFIG_MPC823 431#define BCSR4_VIDEO_RST ((uint)0x00200000) 432#endif /* CONFIG_MPC823 */ 433#ifdef CONFIG_MPC860T 434#define BCSR4_FETHRST ((uint)0x00200000) 435#endif /* CONFIG_MPC860T */ 436#ifdef CONFIG_MPC823 437#define BCSR4_MODEM_EN ((uint)0x00100000) 438#endif /* CONFIG_MPC823 */ 439#ifdef CONFIG_MPC823 440#define BCSR4_DATA_VOICE ((uint)0x00080000) 441#endif /* CONFIG_MPC823 */ 442#ifdef CONFIG_MPC850 443#define BCSR4_DATA_VOICE ((uint)0x00080000) 444#endif /* CONFIG_MPC850 */ 445 446#define CONFIG_DRAM_50MHZ 1 447#define CONFIG_SDRAM_50MHZ 448 449/* We don't use the 8259. 450*/ 451#define NR_8259_INTS 0 452 453/* 454 * MPC8xx CPM Options 455 */ 456#define CONFIG_SCC_ENET 1 457#define CONFIG_SCC2_ENET 1 458#undef CONFIG_FEC_ENET 459#undef CONFIG_CPM_IIC 460#undef CONFIG_UCODE_PATCH 461 462#define CONFIG_DISK_SPINUP_TIME 1000000 463 464/* PCMCIA configuration */ 465 466#define PCMCIA_MAX_SLOTS 1 467 468#ifdef CONFIG_MPC860 469#define PCMCIA_SLOT_A 1 470#endif 471 472#define CONFIG_SYS_DAUGHTERBOARD 473 474#endif /* __CONFIG_H */ 475