1/* 2 * Configuation settings for the Freescale MCF54451 EVB board. 3 * 4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26/* 27 * board/config.h - configuration options, board specific 28 */ 29 30#ifndef _M54451EVB_H 31#define _M54451EVB_H 32 33/* 34 * High Level Configuration Options 35 * (easy to change) 36 */ 37#define CONFIG_MCF5445x /* define processor family */ 38#define CONFIG_M54451 /* define processor type */ 39#define CONFIG_M54451EVB /* M54451EVB board */ 40 41#define CONFIG_MCFUART 42#define CONFIG_SYS_UART_PORT (0) 43#define CONFIG_BAUDRATE 115200 44 45#undef CONFIG_WATCHDOG 46 47#define CONFIG_TIMESTAMP /* Print image info with timestamp */ 48 49/* 50 * BOOTP options 51 */ 52#define CONFIG_BOOTP_BOOTFILESIZE 53#define CONFIG_BOOTP_BOOTPATH 54#define CONFIG_BOOTP_GATEWAY 55#define CONFIG_BOOTP_HOSTNAME 56 57/* Command line configuration */ 58#include <config_cmd_default.h> 59 60#define CONFIG_CMD_BOOTD 61#define CONFIG_CMD_CACHE 62#define CONFIG_CMD_DATE 63#define CONFIG_CMD_DHCP 64#define CONFIG_CMD_ELF 65#define CONFIG_CMD_FLASH 66#define CONFIG_CMD_I2C 67#undef CONFIG_CMD_JFFS2 68#define CONFIG_CMD_MEMORY 69#define CONFIG_CMD_MISC 70#define CONFIG_CMD_MII 71#define CONFIG_CMD_NET 72#define CONFIG_CMD_NFS 73#define CONFIG_CMD_PING 74#define CONFIG_CMD_REGINFO 75#define CONFIG_CMD_SPI 76#define CONFIG_CMD_SF 77 78#undef CONFIG_CMD_LOADB 79#undef CONFIG_CMD_LOADS 80 81/* Network configuration */ 82#define CONFIG_MCFFEC 83#ifdef CONFIG_MCFFEC 84# define CONFIG_MII 1 85# define CONFIG_MII_INIT 1 86# define CONFIG_SYS_DISCOVER_PHY 87# define CONFIG_SYS_RX_ETH_BUFFER 8 88# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 89 90# define CONFIG_SYS_FEC0_PINMUX 0 91# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 92# define MCFFEC_TOUT_LOOP 50000 93 94# define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 95# define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:2M(kernel)ro,-(jffs2)" 96# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 97# define CONFIG_ETHPRIME "FEC0" 98# define CONFIG_IPADDR 192.162.1.2 99# define CONFIG_NETMASK 255.255.255.0 100# define CONFIG_SERVERIP 192.162.1.1 101# define CONFIG_GATEWAYIP 192.162.1.1 102# define CONFIG_OVERWRITE_ETHADDR_ONCE 103 104/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 105# ifndef CONFIG_SYS_DISCOVER_PHY 106# define FECDUPLEX FULL 107# define FECSPEED _100BASET 108# else 109# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 110# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 111# endif 112# endif /* CONFIG_SYS_DISCOVER_PHY */ 113#endif 114 115#define CONFIG_HOSTNAME M54451EVB 116#ifdef CONFIG_SYS_STMICRO_BOOT 117/* ST Micro serial flash */ 118#define CONFIG_SYS_LOAD_ADDR2 0x40010007 119#define CONFIG_EXTRA_ENV_SETTINGS \ 120 "netdev=eth0\0" \ 121 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 122 "loadaddr=0x40010000\0" \ 123 "sbfhdr=sbfhdr.bin\0" \ 124 "uboot=u-boot.bin\0" \ 125 "load=tftp ${loadaddr} ${sbfhdr};" \ 126 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ 127 "upd=run load; run prog\0" \ 128 "prog=sf probe 0:1 1000000 3;" \ 129 "sf erase 0 30000;" \ 130 "sf write ${loadaddr} 0 30000;" \ 131 "save\0" \ 132 "" 133#else 134#define CONFIG_SYS_UBOOT_END 0x3FFFF 135#define CONFIG_EXTRA_ENV_SETTINGS \ 136 "netdev=eth0\0" \ 137 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 138 "loadaddr=40010000\0" \ 139 "u-boot=u-boot.bin\0" \ 140 "load=tftp ${loadaddr) ${u-boot}\0" \ 141 "upd=run load; run prog\0" \ 142 "prog=prot off 0 " __stringify(CONFIG_SYS_UBOOT_END) \ 143 "; era 0 " __stringify(CONFIG_SYS_UBOOT_END) " ;" \ 144 "cp.b ${loadaddr} 0 ${filesize};" \ 145 "save\0" \ 146 "" 147#endif 148 149/* Realtime clock */ 150#define CONFIG_MCFRTC 151#undef RTC_DEBUG 152#define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) 153 154/* Timer */ 155#define CONFIG_MCFTMR 156#undef CONFIG_MCFPIT 157 158/* I2c */ 159#define CONFIG_FSL_I2C 160#define CONFIG_HARD_I2C /* I2C with hardware support */ 161#undef CONFIG_SOFT_I2C /* I2C bit-banged */ 162#define CONFIG_SYS_I2C_SPEED 80000 /* I2C speed and slave address */ 163#define CONFIG_SYS_I2C_SLAVE 0x7F 164#define CONFIG_SYS_I2C_OFFSET 0x58000 165#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 166 167/* DSPI and Serial Flash */ 168#define CONFIG_CF_SPI 169#define CONFIG_CF_DSPI 170#define CONFIG_SERIAL_FLASH 171#define CONFIG_HARD_SPI 172#define CONFIG_SYS_SBFHDR_SIZE 0x7 173#ifdef CONFIG_CMD_SPI 174# define CONFIG_SPI_FLASH 175# define CONFIG_SPI_FLASH_STMICRO 176 177# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ 178 DSPI_CTAR_PCSSCK_1CLK | \ 179 DSPI_CTAR_PASC(0) | \ 180 DSPI_CTAR_PDT(0) | \ 181 DSPI_CTAR_CSSCK(0) | \ 182 DSPI_CTAR_ASC(0) | \ 183 DSPI_CTAR_DT(1)) 184# define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0) 185# define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0) 186#endif 187 188/* Input, PCI, Flexbus, and VCO */ 189#define CONFIG_EXTRA_CLOCK 190 191#define CONFIG_PRAM 2048 /* 2048 KB */ 192 193#define CONFIG_SYS_PROMPT "-> " 194#define CONFIG_SYS_LONGHELP /* undef to save memory */ 195 196#if defined(CONFIG_CMD_KGDB) 197#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 198#else 199#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 200#endif 201#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 202#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 203#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 204 205#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 206 207#define CONFIG_SYS_HZ 1000 208 209#define CONFIG_SYS_MBAR 0xFC000000 210 211/* 212 * Low Level Configuration Settings 213 * (address mappings, register initial values, etc.) 214 * You should know what you are doing if you make changes here. 215 */ 216 217/*----------------------------------------------------------------------- 218 * Definitions for initial stack pointer and data area (in DPRAM) 219 */ 220#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 221#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 222#define CONFIG_SYS_INIT_RAM_CTRL 0x221 223#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) 224#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 225#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 226 227/*----------------------------------------------------------------------- 228 * Start addresses for the final memory configuration 229 * (Set up by the startup code) 230 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 231 */ 232#define CONFIG_SYS_SDRAM_BASE 0x40000000 233#define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ 234#define CONFIG_SYS_SDRAM_CFG1 0x33633F30 235#define CONFIG_SYS_SDRAM_CFG2 0x57670000 236#define CONFIG_SYS_SDRAM_CTRL 0xE20D2C00 237#define CONFIG_SYS_SDRAM_EMOD 0x80810000 238#define CONFIG_SYS_SDRAM_MODE 0x008D0000 239#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x44 240 241#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 242#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 243 244#ifdef CONFIG_CF_SBF 245# define CONFIG_SERIAL_BOOT 246# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 247#else 248# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 249#endif 250#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 251#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 252 253/* Reserve 256 kB for malloc() */ 254#define CONFIG_SYS_MALLOC_LEN (256 << 10) 255/* 256 * For booting Linux, the board info and command line data 257 * have to be in the first 8 MB of memory, since this is 258 * the maximum mapped by the Linux kernel during initialization ?? 259 */ 260/* Initial Memory map for Linux */ 261#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 262 263/* Configuration for environment 264 * Environment is not embedded in u-boot. First time runing may have env 265 * crc error warning if there is no correct environment on the flash. 266 */ 267#if defined(CONFIG_SYS_STMICRO_BOOT) 268# define CONFIG_ENV_IS_IN_SPI_FLASH 1 269# define CONFIG_ENV_SPI_CS 1 270# define CONFIG_ENV_OFFSET 0x20000 271# define CONFIG_ENV_SIZE 0x2000 272# define CONFIG_ENV_SECT_SIZE 0x10000 273#else 274# define CONFIG_ENV_IS_IN_FLASH 1 275# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) 276# define CONFIG_ENV_SIZE 0x2000 277# define CONFIG_ENV_SECT_SIZE 0x20000 278#endif 279#undef CONFIG_ENV_OVERWRITE 280 281/* FLASH organization */ 282#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 283 284#define CONFIG_SYS_FLASH_CFI 285#ifdef CONFIG_SYS_FLASH_CFI 286 287# define CONFIG_FLASH_CFI_DRIVER 1 288# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 289# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 290# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 291# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 292# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 293# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 294# define CONFIG_SYS_FLASH_CHECKSUM 295# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } 296 297#endif 298 299/* 300 * This is setting for JFFS2 support in u-boot. 301 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 302 */ 303#ifdef CONFIG_CMD_JFFS2 304# define CONFIG_JFFS2_DEV "nor0" 305# define CONFIG_JFFS2_PART_SIZE 0x01000000 306# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000) 307#endif 308 309/* Cache Configuration */ 310#define CONFIG_SYS_CACHELINE_SIZE 16 311 312#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 313 CONFIG_SYS_INIT_RAM_SIZE - 8) 314#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 315 CONFIG_SYS_INIT_RAM_SIZE - 4) 316#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) 317#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 318#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 319 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 320 CF_ACR_EN | CF_ACR_SM_ALL) 321#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ 322 CF_CACR_ICINVA | CF_CACR_EUSP) 323#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 324 CF_CACR_DEC | CF_CACR_DDCM_P | \ 325 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 326 327/*----------------------------------------------------------------------- 328 * Memory bank definitions 329 */ 330/* 331 * CS0 - NOR Flash 16MB 332 * CS1 - Available 333 * CS2 - Available 334 * CS3 - Available 335 * CS4 - Available 336 * CS5 - Available 337 */ 338 339 /* Flash */ 340#define CONFIG_SYS_CS0_BASE 0x00000000 341#define CONFIG_SYS_CS0_MASK 0x00FF0001 342#define CONFIG_SYS_CS0_CTRL 0x00004D80 343 344#define CONFIG_SYS_SPANSION_BASE CONFIG_SYS_CS0_BASE 345 346#endif /* _M54451EVB_H */ 347