1/* 2 * Configuation settings for the Freescale MCF54455 EVB board. 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26/* 27 * board/config.h - configuration options, board specific 28 */ 29 30#ifndef _M54455EVB_H 31#define _M54455EVB_H 32 33/* 34 * High Level Configuration Options 35 * (easy to change) 36 */ 37#define CONFIG_MCF5445x /* define processor family */ 38#define CONFIG_M54455 /* define processor type */ 39#define CONFIG_M54455EVB /* M54455EVB board */ 40 41#define CONFIG_MCFUART 42#define CONFIG_SYS_UART_PORT (0) 43#define CONFIG_BAUDRATE 115200 44 45#undef CONFIG_WATCHDOG 46 47#define CONFIG_TIMESTAMP /* Print image info with timestamp */ 48 49/* 50 * BOOTP options 51 */ 52#define CONFIG_BOOTP_BOOTFILESIZE 53#define CONFIG_BOOTP_BOOTPATH 54#define CONFIG_BOOTP_GATEWAY 55#define CONFIG_BOOTP_HOSTNAME 56 57/* Command line configuration */ 58#include <config_cmd_default.h> 59 60#define CONFIG_CMD_BOOTD 61#define CONFIG_CMD_CACHE 62#define CONFIG_CMD_DATE 63#define CONFIG_CMD_DHCP 64#define CONFIG_CMD_ELF 65#define CONFIG_CMD_EXT2 66#define CONFIG_CMD_FAT 67#define CONFIG_CMD_FLASH 68#define CONFIG_CMD_I2C 69#define CONFIG_CMD_IDE 70#define CONFIG_CMD_JFFS2 71#define CONFIG_CMD_MEMORY 72#define CONFIG_CMD_MISC 73#define CONFIG_CMD_MII 74#define CONFIG_CMD_NET 75#undef CONFIG_CMD_PCI 76#define CONFIG_CMD_PING 77#define CONFIG_CMD_REGINFO 78#define CONFIG_CMD_SPI 79#define CONFIG_CMD_SF 80 81#undef CONFIG_CMD_LOADB 82#undef CONFIG_CMD_LOADS 83 84/* Network configuration */ 85#define CONFIG_MCFFEC 86#ifdef CONFIG_MCFFEC 87# define CONFIG_MII 1 88# define CONFIG_MII_INIT 1 89# define CONFIG_SYS_DISCOVER_PHY 90# define CONFIG_SYS_RX_ETH_BUFFER 8 91# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 92 93# define CONFIG_SYS_FEC0_PINMUX 0 94# define CONFIG_SYS_FEC1_PINMUX 0 95# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 96# define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE 97# define MCFFEC_TOUT_LOOP 50000 98# define CONFIG_HAS_ETH1 99 100# define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 101# define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)" 102# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 103# define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61 104# define CONFIG_ETHPRIME "FEC0" 105# define CONFIG_IPADDR 192.162.1.2 106# define CONFIG_NETMASK 255.255.255.0 107# define CONFIG_SERVERIP 192.162.1.1 108# define CONFIG_GATEWAYIP 192.162.1.1 109# define CONFIG_OVERWRITE_ETHADDR_ONCE 110 111/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 112# ifndef CONFIG_SYS_DISCOVER_PHY 113# define FECDUPLEX FULL 114# define FECSPEED _100BASET 115# else 116# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 117# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 118# endif 119# endif /* CONFIG_SYS_DISCOVER_PHY */ 120#endif 121 122#define CONFIG_HOSTNAME M54455EVB 123#ifdef CONFIG_SYS_STMICRO_BOOT 124/* ST Micro serial flash */ 125#define CONFIG_SYS_LOAD_ADDR2 0x40010013 126#define CONFIG_EXTRA_ENV_SETTINGS \ 127 "netdev=eth0\0" \ 128 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 129 "loadaddr=0x40010000\0" \ 130 "sbfhdr=sbfhdr.bin\0" \ 131 "uboot=u-boot.bin\0" \ 132 "load=tftp ${loadaddr} ${sbfhdr};" \ 133 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ 134 "upd=run load; run prog\0" \ 135 "prog=sf probe 0:1 1000000 3;" \ 136 "sf erase 0 30000;" \ 137 "sf write ${loadaddr} 0 0x30000;" \ 138 "save\0" \ 139 "" 140#else 141/* Atmel and Intel */ 142#ifdef CONFIG_SYS_ATMEL_BOOT 143# define CONFIG_SYS_UBOOT_END 0x0403FFFF 144#elif defined(CONFIG_SYS_INTEL_BOOT) 145# define CONFIG_SYS_UBOOT_END 0x3FFFF 146#endif 147#define CONFIG_EXTRA_ENV_SETTINGS \ 148 "netdev=eth0\0" \ 149 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 150 "loadaddr=0x40010000\0" \ 151 "uboot=u-boot.bin\0" \ 152 "load=tftp ${loadaddr} ${uboot}\0" \ 153 "upd=run load; run prog\0" \ 154 "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \ 155 " " __stringify(CONFIG_SYS_UBOOT_END) ";" \ 156 "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \ 157 __stringify(CONFIG_SYS_UBOOT_END) ";" \ 158 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \ 159 " ${filesize}; save\0" \ 160 "" 161#endif 162 163/* ATA configuration */ 164#define CONFIG_ISO_PARTITION 165#define CONFIG_DOS_PARTITION 166#define CONFIG_IDE_RESET 1 167#define CONFIG_IDE_PREINIT 1 168#define CONFIG_ATAPI 169#undef CONFIG_LBA48 170 171#define CONFIG_SYS_IDE_MAXBUS 1 172#define CONFIG_SYS_IDE_MAXDEVICE 2 173 174#define CONFIG_SYS_ATA_BASE_ADDR 0x90000000 175#define CONFIG_SYS_ATA_IDE0_OFFSET 0 176 177#define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ 178#define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ 179#define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ 180#define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ 181 182/* Realtime clock */ 183#define CONFIG_MCFRTC 184#undef RTC_DEBUG 185#define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) 186 187/* Timer */ 188#define CONFIG_MCFTMR 189#undef CONFIG_MCFPIT 190 191/* I2c */ 192#define CONFIG_FSL_I2C 193#define CONFIG_HARD_I2C /* I2C with hardware support */ 194#undef CONFIG_SOFT_I2C /* I2C bit-banged */ 195#define CONFIG_SYS_I2C_SPEED 80000 /* I2C speed and slave address */ 196#define CONFIG_SYS_I2C_SLAVE 0x7F 197#define CONFIG_SYS_I2C_OFFSET 0x58000 198#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 199 200/* DSPI and Serial Flash */ 201#define CONFIG_CF_SPI 202#define CONFIG_CF_DSPI 203#define CONFIG_HARD_SPI 204#define CONFIG_SYS_SBFHDR_SIZE 0x13 205#ifdef CONFIG_CMD_SPI 206# define CONFIG_SPI_FLASH 207# define CONFIG_SPI_FLASH_STMICRO 208 209# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ 210 DSPI_CTAR_PCSSCK_1CLK | \ 211 DSPI_CTAR_PASC(0) | \ 212 DSPI_CTAR_PDT(0) | \ 213 DSPI_CTAR_CSSCK(0) | \ 214 DSPI_CTAR_ASC(0) | \ 215 DSPI_CTAR_DT(1)) 216#endif 217 218/* PCI */ 219#ifdef CONFIG_CMD_PCI 220#define CONFIG_PCI 1 221#define CONFIG_PCI_PNP 1 222#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 223 224#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 4 225 226#define CONFIG_SYS_PCI_MEM_BUS 0xA0000000 227#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS 228#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 229 230#define CONFIG_SYS_PCI_IO_BUS 0xB1000000 231#define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS 232#define CONFIG_SYS_PCI_IO_SIZE 0x01000000 233 234#define CONFIG_SYS_PCI_CFG_BUS 0xB0000000 235#define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS 236#define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 237#endif 238 239/* FPGA - Spartan 2 */ 240/* experiment 241#define CONFIG_FPGA CONFIG_SYS_SPARTAN3 242#define CONFIG_FPGA_COUNT 1 243#define CONFIG_SYS_FPGA_PROG_FEEDBACK 244#define CONFIG_SYS_FPGA_CHECK_CTRLC 245*/ 246 247/* Input, PCI, Flexbus, and VCO */ 248#define CONFIG_EXTRA_CLOCK 249 250#define CONFIG_PRAM 2048 /* 2048 KB */ 251 252#define CONFIG_SYS_PROMPT "-> " 253#define CONFIG_SYS_LONGHELP /* undef to save memory */ 254 255#if defined(CONFIG_CMD_KGDB) 256#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 257#else 258#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 259#endif 260#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 261#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 262#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 263 264#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 265 266#define CONFIG_SYS_HZ 1000 267 268#define CONFIG_SYS_MBAR 0xFC000000 269 270/* 271 * Low Level Configuration Settings 272 * (address mappings, register initial values, etc.) 273 * You should know what you are doing if you make changes here. 274 */ 275 276/*----------------------------------------------------------------------- 277 * Definitions for initial stack pointer and data area (in DPRAM) 278 */ 279#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 280#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 281#define CONFIG_SYS_INIT_RAM_CTRL 0x221 282#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) 283#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 284#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 285 286/*----------------------------------------------------------------------- 287 * Start addresses for the final memory configuration 288 * (Set up by the startup code) 289 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 290 */ 291#define CONFIG_SYS_SDRAM_BASE 0x40000000 292#define CONFIG_SYS_SDRAM_BASE1 0x48000000 293#define CONFIG_SYS_SDRAM_SIZE 256 /* SDRAM size in MB */ 294#define CONFIG_SYS_SDRAM_CFG1 0x65311610 295#define CONFIG_SYS_SDRAM_CFG2 0x59670000 296#define CONFIG_SYS_SDRAM_CTRL 0xEA0B2000 297#define CONFIG_SYS_SDRAM_EMOD 0x40010000 298#define CONFIG_SYS_SDRAM_MODE 0x00010033 299#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0xAA 300 301#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 302#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 303 304#ifdef CONFIG_CF_SBF 305# define CONFIG_SERIAL_BOOT 306# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 307#else 308# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 309#endif 310#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 311#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 312 313/* Reserve 256 kB for malloc() */ 314#define CONFIG_SYS_MALLOC_LEN (256 << 10) 315 316/* 317 * For booting Linux, the board info and command line data 318 * have to be in the first 8 MB of memory, since this is 319 * the maximum mapped by the Linux kernel during initialization ?? 320 */ 321/* Initial Memory map for Linux */ 322#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 323 324/* 325 * Configuration for environment 326 * Environment is not embedded in u-boot. First time runing may have env 327 * crc error warning if there is no correct environment on the flash. 328 */ 329#ifdef CONFIG_CF_SBF 330# define CONFIG_ENV_IS_IN_SPI_FLASH 331# define CONFIG_ENV_SPI_CS 1 332#else 333# define CONFIG_ENV_IS_IN_FLASH 1 334#endif 335#undef CONFIG_ENV_OVERWRITE 336 337/*----------------------------------------------------------------------- 338 * FLASH organization 339 */ 340#ifdef CONFIG_SYS_STMICRO_BOOT 341# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 342# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS1_BASE 343# define CONFIG_ENV_OFFSET 0x30000 344# define CONFIG_ENV_SIZE 0x2000 345# define CONFIG_ENV_SECT_SIZE 0x10000 346#endif 347#ifdef CONFIG_SYS_ATMEL_BOOT 348# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 349# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE 350# define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE 351# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) 352# define CONFIG_ENV_SIZE 0x2000 353# define CONFIG_ENV_SECT_SIZE 0x10000 354#endif 355#ifdef CONFIG_SYS_INTEL_BOOT 356# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 357# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE 358# define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE 359# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) 360# define CONFIG_ENV_SIZE 0x2000 361# define CONFIG_ENV_SECT_SIZE 0x20000 362#endif 363 364#define CONFIG_SYS_FLASH_CFI 365#ifdef CONFIG_SYS_FLASH_CFI 366 367# define CONFIG_FLASH_CFI_DRIVER 1 368# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 369# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 370# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT 371# define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 372# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 373# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 374# define CONFIG_SYS_FLASH_CHECKSUM 375# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } 376# define CONFIG_FLASH_CFI_LEGACY 377 378#ifdef CONFIG_FLASH_CFI_LEGACY 379# define CONFIG_SYS_ATMEL_REGION 4 380# define CONFIG_SYS_ATMEL_TOTALSECT 11 381# define CONFIG_SYS_ATMEL_SECT {1, 2, 1, 7} 382# define CONFIG_SYS_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000} 383#endif 384#endif 385 386/* 387 * This is setting for JFFS2 support in u-boot. 388 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 389 */ 390#ifdef CONFIG_CMD_JFFS2 391#ifdef CF_STMICRO_BOOT 392# define CONFIG_JFFS2_DEV "nor1" 393# define CONFIG_JFFS2_PART_SIZE 0x01000000 394# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH2_BASE + 0x500000) 395#endif 396#ifdef CONFIG_SYS_ATMEL_BOOT 397# define CONFIG_JFFS2_DEV "nor1" 398# define CONFIG_JFFS2_PART_SIZE 0x01000000 399# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH1_BASE + 0x500000) 400#endif 401#ifdef CONFIG_SYS_INTEL_BOOT 402# define CONFIG_JFFS2_DEV "nor0" 403# define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000) 404# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000) 405#endif 406#endif 407 408/*----------------------------------------------------------------------- 409 * Cache Configuration 410 */ 411#define CONFIG_SYS_CACHELINE_SIZE 16 412 413#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 414 CONFIG_SYS_INIT_RAM_SIZE - 8) 415#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 416 CONFIG_SYS_INIT_RAM_SIZE - 4) 417#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) 418#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 419#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 420 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 421 CF_ACR_EN | CF_ACR_SM_ALL) 422#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ 423 CF_CACR_ICINVA | CF_CACR_EUSP) 424#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 425 CF_CACR_DEC | CF_CACR_DDCM_P | \ 426 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 427 428/*----------------------------------------------------------------------- 429 * Memory bank definitions 430 */ 431/* 432 * CS0 - NOR Flash 1, 2, 4, or 8MB 433 * CS1 - CompactFlash and registers 434 * CS2 - CPLD 435 * CS3 - FPGA 436 * CS4 - Available 437 * CS5 - Available 438 */ 439 440#if defined(CONFIG_SYS_ATMEL_BOOT) || defined(CONFIG_SYS_STMICRO_BOOT) 441 /* Atmel Flash */ 442#define CONFIG_SYS_CS0_BASE 0x04000000 443#define CONFIG_SYS_CS0_MASK 0x00070001 444#define CONFIG_SYS_CS0_CTRL 0x00001140 445/* Intel Flash */ 446#define CONFIG_SYS_CS1_BASE 0x00000000 447#define CONFIG_SYS_CS1_MASK 0x01FF0001 448#define CONFIG_SYS_CS1_CTRL 0x00000D60 449 450#define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS0_BASE 451#else 452/* Intel Flash */ 453#define CONFIG_SYS_CS0_BASE 0x00000000 454#define CONFIG_SYS_CS0_MASK 0x01FF0001 455#define CONFIG_SYS_CS0_CTRL 0x00000D60 456 /* Atmel Flash */ 457#define CONFIG_SYS_CS1_BASE 0x04000000 458#define CONFIG_SYS_CS1_MASK 0x00070001 459#define CONFIG_SYS_CS1_CTRL 0x00001140 460 461#define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS1_BASE 462#endif 463 464/* CPLD */ 465#define CONFIG_SYS_CS2_BASE 0x08000000 466#define CONFIG_SYS_CS2_MASK 0x00070001 467#define CONFIG_SYS_CS2_CTRL 0x003f1140 468 469/* FPGA */ 470#define CONFIG_SYS_CS3_BASE 0x09000000 471#define CONFIG_SYS_CS3_MASK 0x00070001 472#define CONFIG_SYS_CS3_CTRL 0x00000020 473 474#endif /* _M54455EVB_H */ 475