1/* 2 * Copyright (C) 2011 Andes Technology Corporation 3 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> 4 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 22 */ 23 24#ifndef __CONFIG_H 25#define __CONFIG_H 26 27#include <asm/arch/ag101.h> 28 29/* 30 * CPU and Board Configuration Options 31 */ 32#define CONFIG_ADP_AG101P 33 34#define CONFIG_USE_INTERRUPT 35 36#define CONFIG_SKIP_LOWLEVEL_INIT 37 38#ifndef CONFIG_SKIP_LOWLEVEL_INIT 39#define CONFIG_MEM_REMAP 40#endif 41 42#ifdef CONFIG_SKIP_LOWLEVEL_INIT 43#define CONFIG_SYS_TEXT_BASE 0x03200000 44#else 45#define CONFIG_SYS_TEXT_BASE 0x00000000 46#endif 47 48/* 49 * Timer 50 */ 51 52/* 53 * According to the discussion in u-boot mailing list before, 54 * CONFIG_SYS_HZ at 1000 is mandatory. 55 */ 56#define CONFIG_SYS_HZ 1000 57#define CONFIG_SYS_CLK_FREQ 39062500 58#define VERSION_CLOCK CONFIG_SYS_CLK_FREQ 59 60/* 61 * Use Externel CLOCK or PCLK 62 */ 63#undef CONFIG_FTRTC010_EXTCLK 64 65#ifndef CONFIG_FTRTC010_EXTCLK 66#define CONFIG_FTRTC010_PCLK 67#endif 68 69#ifdef CONFIG_FTRTC010_EXTCLK 70#define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */ 71#else 72#define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */ 73#endif 74 75#define TIMER_LOAD_VAL 0xffffffff 76 77/* 78 * Real Time Clock 79 */ 80#define CONFIG_RTC_FTRTC010 81 82/* 83 * Real Time Clock Divider 84 * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) 85 */ 86#define OSC_5MHZ (5*1000000) 87#define OSC_CLK (4*OSC_5MHZ) 88#define RTC_DIV_COUNT (0.5) /* Why?? */ 89 90/* 91 * Serial console configuration 92 */ 93 94/* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */ 95#define CONFIG_BAUDRATE 38400 96#define CONFIG_CONS_INDEX 1 97#define CONFIG_SYS_NS16550 98#define CONFIG_SYS_NS16550_SERIAL 99#define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE 100#define CONFIG_SYS_NS16550_REG_SIZE -4 101#define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */ 102 103/* 104 * Ethernet 105 */ 106#define CONFIG_FTMAC100 107 108#define CONFIG_BOOTDELAY 3 109 110/* 111 * SD (MMC) controller 112 */ 113#define CONFIG_MMC 114#define CONFIG_CMD_MMC 115#define CONFIG_GENERIC_MMC 116#define CONFIG_DOS_PARTITION 117#define CONFIG_FTSDC010 118#define CONFIG_FTSDC010_NUMBER 1 119#define CONFIG_CMD_FAT 120 121/* 122 * Command line configuration. 123 */ 124#include <config_cmd_default.h> 125 126#define CONFIG_CMD_CACHE 127#define CONFIG_CMD_DATE 128#define CONFIG_CMD_PING 129 130/* 131 * Miscellaneous configurable options 132 */ 133#define CONFIG_SYS_LONGHELP /* undef to save memory */ 134#define CONFIG_SYS_PROMPT "NDS32 # " /* Monitor Command Prompt */ 135#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 136 137/* Print Buffer Size */ 138#define CONFIG_SYS_PBSIZE \ 139 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 140 141/* max number of command args */ 142#define CONFIG_SYS_MAXARGS 16 143 144/* Boot Argument Buffer Size */ 145#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 146 147/* 148 * Size of malloc() pool 149 */ 150/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ 151#define CONFIG_SYS_MALLOC_LEN (512 << 10) 152 153/* 154 * size in bytes reserved for initial data 155 */ 156#define CONFIG_SYS_GBL_DATA_SIZE 128 157 158/* 159 * AHB Controller configuration 160 */ 161#define CONFIG_FTAHBC020S 162 163#ifdef CONFIG_FTAHBC020S 164#include <faraday/ftahbc020s.h> 165 166/* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */ 167#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100 168 169/* 170 * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S, 171 * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote 172 * in C language. 173 */ 174#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \ 175 (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \ 176 FTAHBC020S_SLAVE_BSR_SIZE(0xb)) 177#endif 178 179/* 180 * Watchdog 181 */ 182#define CONFIG_FTWDT010_WATCHDOG 183 184/* 185 * PMU Power controller configuration 186 */ 187#define CONFIG_PMU 188#define CONFIG_FTPMU010_POWER 189 190#ifdef CONFIG_FTPMU010_POWER 191#include <faraday/ftpmu010.h> 192#define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E 193#define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \ 194 FTPMU010_SDRAMHTC_EBIDATA_DCSR | \ 195 FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \ 196 FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \ 197 FTPMU010_SDRAMHTC_CKE_DCSR | \ 198 FTPMU010_SDRAMHTC_DQM_DCSR | \ 199 FTPMU010_SDRAMHTC_SDCLK_DCSR) 200#endif 201 202/* 203 * SDRAM controller configuration 204 */ 205#define CONFIG_FTSDMC021 206 207#ifdef CONFIG_FTSDMC021 208#include <faraday/ftsdmc021.h> 209 210#define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRAS(2) | \ 211 FTSDMC021_TP1_TRP(1) | \ 212 FTSDMC021_TP1_TRCD(1) | \ 213 FTSDMC021_TP1_TRF(3) | \ 214 FTSDMC021_TP1_TWR(1) | \ 215 FTSDMC021_TP1_TCL(2)) 216 217#define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \ 218 FTSDMC021_TP2_INI_REFT(8) | \ 219 FTSDMC021_TP2_REF_INTV(0x180)) 220 221/* 222 * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S, 223 * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in 224 * C language. 225 */ 226#define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \ 227 FTSDMC021_CR1_DSZ(3) | \ 228 FTSDMC021_CR1_MBW(2) | \ 229 FTSDMC021_CR1_BNKSIZE(6)) 230 231#define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \ 232 FTSDMC021_CR2_IREF | \ 233 FTSDMC021_CR2_ISMR) 234 235#define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 236#define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \ 237 CONFIG_SYS_FTSDMC021_BANK0_BASE) 238 239#endif 240 241/* 242 * Physical Memory Map 243 */ 244#if defined(CONFIG_MEM_REMAP) || defined(CONFIG_SKIP_LOWLEVEL_INIT) 245#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ 246#if defined(CONFIG_MEM_REMAP) 247#define PHYS_SDRAM_0_AT_INIT 0x10000000 /* SDRAM Bank #1 before remap*/ 248#endif 249#else /* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */ 250#define PHYS_SDRAM_0 0x10000000 /* SDRAM Bank #1 */ 251#endif 252 253#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ 254#define PHYS_SDRAM_0_SIZE 0x04000000 /* 64 MB */ 255 256#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 257 258#ifdef CONFIG_MEM_REMAP 259#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \ 260 GENERATED_GBL_DATA_SIZE) 261#else 262#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ 263 GENERATED_GBL_DATA_SIZE) 264#endif /* CONFIG_MEM_REMAP */ 265 266/* 267 * Load address and memory test area should agree with 268 * arch/nds32/config.mk. Be careful not to overwrite U-boot itself. 269 */ 270#define CONFIG_SYS_LOAD_ADDR 0x300000 271 272/* memtest works on 63 MB in DRAM */ 273#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 274#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000) 275 276/* 277 * Static memory controller configuration 278 */ 279#define CONFIG_FTSMC020 280 281#ifdef CONFIG_FTSMC020 282#include <faraday/ftsmc020.h> 283 284#define CONFIG_SYS_FTSMC020_CONFIGS { \ 285 { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ 286 { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ 287} 288 289#ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */ 290#define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \ 291 FTSMC020_BANK_SIZE_32M | \ 292 FTSMC020_BANK_MBW_32) 293 294#define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \ 295 FTSMC020_TPR_AST(1) | \ 296 FTSMC020_TPR_CTW(1) | \ 297 FTSMC020_TPR_ATI(1) | \ 298 FTSMC020_TPR_AT2(1) | \ 299 FTSMC020_TPR_WTC(1) | \ 300 FTSMC020_TPR_AHT(1) | \ 301 FTSMC020_TPR_TRNA(1)) 302#endif 303 304/* 305 * FLASH on ADP_AG101P is connected to BANK0 306 * Just disalbe the other BANK to avoid detection error. 307 */ 308#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ 309 FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ 310 FTSMC020_BANK_SIZE_32M | \ 311 FTSMC020_BANK_MBW_32) 312 313#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \ 314 FTSMC020_TPR_CTW(3) | \ 315 FTSMC020_TPR_ATI(0xf) | \ 316 FTSMC020_TPR_AT2(3) | \ 317 FTSMC020_TPR_WTC(3) | \ 318 FTSMC020_TPR_AHT(3) | \ 319 FTSMC020_TPR_TRNA(0xf)) 320 321#define FTSMC020_BANK1_CONFIG (0x00) 322#define FTSMC020_BANK1_TIMING (0x00) 323#endif /* CONFIG_FTSMC020 */ 324 325/* 326 * FLASH and environment organization 327 */ 328/* use CFI framework */ 329#define CONFIG_SYS_FLASH_CFI 330#define CONFIG_FLASH_CFI_DRIVER 331 332#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 333#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 334 335/* support JEDEC */ 336 337/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */ 338#ifdef CONFIG_SKIP_LOWLEVEL_INIT 339#define PHYS_FLASH_1 0x80400000 /* BANK 1 */ 340#else /* !CONFIG_SKIP_LOWLEVEL_INIT */ 341#ifdef CONFIG_MEM_REMAP 342#define PHYS_FLASH_1 0x80000000 /* BANK 0 */ 343#else 344#define PHYS_FLASH_1 0x00000000 /* BANK 0 */ 345#endif /* CONFIG_MEM_REMAP */ 346#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 347 348#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 349#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } 350#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 351 352#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ 353#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ 354 355/* max number of memory banks */ 356/* 357 * There are 4 banks supported for this Controller, 358 * but we have only 1 bank connected to flash on board 359 */ 360#define CONFIG_SYS_MAX_FLASH_BANKS 1 361 362/* max number of sectors on one chip */ 363#define CONFIG_FLASH_SECTOR_SIZE (0x10000*2*2) 364#define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE 365#define CONFIG_SYS_MAX_FLASH_SECT 128 366 367/* environments */ 368#define CONFIG_ENV_IS_IN_FLASH 369#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000) 370#define CONFIG_ENV_SIZE 8192 371#define CONFIG_ENV_OVERWRITE 372 373#endif /* __CONFIG_H */ 374