1/* 2 * (C) Copyright 2001, 2002 3 * Sangmoon Kim, Etin Systems, dogoil@etinsys.com. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* ------------------------------------------------------------------------- */ 25 26/* 27 * board/config.h - configuration options, board specific 28 */ 29 30#ifndef __CONFIG_H 31#define __CONFIG_H 32 33#define CONFIG_SYS_TEXT_BASE 0xFFF00000 34 35/* Environments */ 36 37/* bootargs */ 38#define CONFIG_BOOTARGS \ 39 "console=ttyS0,9600 init=/linuxrc " \ 40 "root=/dev/nfs rw nfsroot=192.168.0.1:" \ 41 "/tftpboot/target " \ 42 "ip=192.168.0.2:192.168.0.1:192.168.0.1:" \ 43 "255.255.255.0:debris:eth0:none " \ 44 "mtdparts=phys:12m(root),-(kernel)" 45 46/* bootcmd */ 47#define CONFIG_BOOTCOMMAND \ 48 "tftp 800000 pImage; " \ 49 "setenv bootargs console=ttyS0,9600 init=/linuxrc " \ 50 "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ 51 "ip=${ipaddr}:${serverip}:${gatewayip}:" \ 52 "${netmask}:${hostname}:eth0:none " \ 53 "mtdparts=phys:12m(root),-(kernel); " \ 54 "bootm 800000" 55 56/* bootdelay */ 57#define CONFIG_BOOTDELAY 5 /* autoboot 5s */ 58 59/* baudrate */ 60#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */ 61 62/* loads_echo */ 63#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ 64 65/* ethaddr */ 66#undef CONFIG_ETHADDR 67 68/* eth2addr */ 69#undef CONFIG_ETH2ADDR 70 71/* eth3addr */ 72#undef CONFIG_ETH3ADDR 73 74/* ipaddr */ 75#define CONFIG_IPADDR 192.168.0.2 76 77/* serverip */ 78#define CONFIG_SERVERIP 192.168.0.1 79 80/* autoload */ 81#undef CONFIG_SYS_AUTOLOAD 82 83/* rootpath */ 84#define CONFIG_ROOTPATH "/tftpboot/target" 85 86/* gatewayip */ 87#define CONFIG_GATEWAYIP 192.168.0.1 88 89/* netmask */ 90#define CONFIG_NETMASK 255.255.255.0 91 92/* hostname */ 93#define CONFIG_HOSTNAME debris 94 95/* bootfile */ 96#define CONFIG_BOOTFILE "pImage" 97 98/* loadaddr */ 99#define CONFIG_LOADADDR 800000 100 101/* preboot */ 102#undef CONFIG_PREBOOT 103 104/* clocks_in_mhz */ 105#undef CONFIG_CLOCKS_IN_MHZ 106 107 108/* 109 * High Level Configuration Options 110 * (easy to change) 111 */ 112 113#define CONFIG_MPC824X 1 114#define CONFIG_MPC8245 1 115#define CONFIG_DEBRIS 1 116 117#if 0 118#define USE_DINK32 1 119#else 120#undef USE_DINK32 121#endif 122 123#define CONFIG_CONS_INDEX 1 124#define CONFIG_BAUDRATE 9600 125#define CONFIG_DRAM_SPEED 100 /* MHz */ 126 127 128/* 129 * BOOTP options 130 */ 131#define CONFIG_BOOTP_BOOTFILESIZE 132#define CONFIG_BOOTP_BOOTPATH 133#define CONFIG_BOOTP_GATEWAY 134#define CONFIG_BOOTP_HOSTNAME 135 136 137/* 138 * Command line configuration. 139 */ 140#include <config_cmd_default.h> 141 142#define CONFIG_CMD_ASKENV 143#define CONFIG_CMD_CACHE 144#define CONFIG_CMD_DATE 145#define CONFIG_CMD_DHCP 146#define CONFIG_CMD_DIAG 147#define CONFIG_CMD_EEPROM 148#define CONFIG_CMD_ELF 149#define CONFIG_CMD_I2C 150#define CONFIG_CMD_JFFS2 151#define CONFIG_CMD_KGDB 152#define CONFIG_CMD_PCI 153#define CONFIG_CMD_PING 154#define CONFIG_CMD_SAVES 155#define CONFIG_CMD_SDRAM 156 157 158/* 159 * Miscellaneous configurable options 160 */ 161#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */ 162#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 163#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 164#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 165#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 166#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 167#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ 168#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 169 170/*----------------------------------------------------------------------- 171 * PCI stuff 172 *----------------------------------------------------------------------- 173 */ 174#define CONFIG_PCI /* include pci support */ 175#define CONFIG_PCI_PNP 176 177#define CONFIG_EEPRO100 178#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ 179#define CONFIG_EEPRO100_SROM_WRITE 180 181#define PCI_ENET0_IOADDR 0x80000000 182#define PCI_ENET0_MEMADDR 0x80000000 183#define PCI_ENET1_IOADDR 0x81000000 184#define PCI_ENET1_MEMADDR 0x81000000 185/*----------------------------------------------------------------------- 186 * Start addresses for the final memory configuration 187 * (Set up by the startup code) 188 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 189 */ 190#define CONFIG_SYS_SDRAM_BASE 0x00000000 191#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000 192#define CONFIG_VERY_BIG_RAM 193 194#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 195 196#if defined (USE_DINK32) 197#define CONFIG_SYS_MONITOR_LEN 0x00040000 198#define CONFIG_SYS_MONITOR_BASE 0x00090000 199#define CONFIG_SYS_RAMBOOT 1 200#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 201#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 202#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 203#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 204#else 205#undef CONFIG_SYS_RAMBOOT 206#define CONFIG_SYS_MONITOR_LEN 0x00040000 207#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 208 209 210#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 211#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 212#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 213 214#endif 215 216#define CONFIG_SYS_FLASH_BASE 0x7C000000 217#define CONFIG_SYS_FLASH_SIZE (16*1024*1024) /* debris has tiny eeprom */ 218 219#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ 220 221#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ 222#define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */ 223 224#define CONFIG_SYS_EUMB_ADDR 0xFC000000 225 226#define CONFIG_SYS_FLASH_RANGE_BASE 0xFF000000 /* flash memory address range */ 227#define CONFIG_SYS_FLASH_RANGE_SIZE 0x01000000 228#define FLASH_BASE0_PRELIM 0x7C000000 /* debris flash */ 229 230/* 231 * JFFS2 partitions 232 * 233 */ 234/* No command line, one static partition, whole device */ 235#undef CONFIG_CMD_MTDPARTS 236#define CONFIG_JFFS2_DEV "nor0" 237#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF 238#define CONFIG_JFFS2_PART_OFFSET 0x00000000 239 240/* mtdparts command line support */ 241 242/* Use first bank for JFFS2, second bank contains U-Boot. 243 * 244 * Note: fake mtd_id's used, no linux mtd map file. 245 */ 246/* 247#define CONFIG_CMD_MTDPARTS 248#define MTDIDS_DEFAULT "nor0=debris-0" 249#define MTDPARTS_DEFAULT "mtdparts=debris-0:-(jffs2)" 250*/ 251 252#define CONFIG_ENV_IS_IN_NVRAM 1 253#define CONFIG_ENV_OVERWRITE 1 254#define CONFIG_SYS_NVRAM_ACCESS_ROUTINE 1 255#define CONFIG_ENV_ADDR 0xFF000000 /* right at the start of NVRAM */ 256#define CONFIG_ENV_SIZE 0x400 /* Size of the Environment - 8K */ 257#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */ 258 259#define CONFIG_SYS_NVRAM_BASE_ADDR 0xff000000 260 261/* 262 * CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_VXWORKS_OFFS = 263 * NV_RAM_ADDRS + NV_BOOT_OFFSET + NV_ENET_OFFSET 264 */ 265#define CONFIG_SYS_NVRAM_VXWORKS_OFFS 0x6900 266 267/* 268 * select i2c support configuration 269 * 270 * Supported configurations are {none, software, hardware} drivers. 271 * If the software driver is chosen, there are some additional 272 * configuration items that the driver uses to drive the port pins. 273 */ 274#define CONFIG_HARD_I2C 1 /* To enable I2C support */ 275#undef CONFIG_SOFT_I2C /* I2C bit-banged */ 276#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 277#define CONFIG_SYS_I2C_SLAVE 0x7F 278 279#ifdef CONFIG_SOFT_I2C 280#error "Soft I2C is not configured properly. Please review!" 281#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ 282#define I2C_ACTIVE (iop->pdir |= 0x00010000) 283#define I2C_TRISTATE (iop->pdir &= ~0x00010000) 284#define I2C_READ ((iop->pdat & 0x00010000) != 0) 285#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ 286 else iop->pdat &= ~0x00010000 287#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ 288 else iop->pdat &= ~0x00020000 289#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ 290#endif /* CONFIG_SOFT_I2C */ 291 292#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */ 293#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ 294#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 295#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ 296 297#define CONFIG_SYS_FLASH_BANKS { FLASH_BASE0_PRELIM } 298 299/*----------------------------------------------------------------------- 300 * Definitions for initial stack pointer and data area (in DPRAM) 301 */ 302 303/* 304 * NS16550 Configuration 305 */ 306#define CONFIG_SYS_NS16550 307#define CONFIG_SYS_NS16550_SERIAL 308 309#define CONFIG_SYS_NS16550_REG_SIZE 1 310 311#define CONFIG_SYS_NS16550_CLK 7372800 312 313#define CONFIG_SYS_NS16550_COM1 0xFF080000 314#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_NS16550_COM1 + 8) 315#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_NS16550_COM1 + 16) 316#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_NS16550_COM1 + 24) 317 318/* 319 * Low Level Configuration Settings 320 * (address mappings, register initial values, etc.) 321 * You should know what you are doing if you make changes here. 322 */ 323 324#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ 325#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 3 326 327#define CONFIG_SYS_DLL_EXTEND 0x00 328#define CONFIG_SYS_PCI_HOLD_DEL 0x20 329 330#define CONFIG_SYS_ROMNAL 15 /* rom/flash next access time */ 331#define CONFIG_SYS_ROMFAL 31 /* rom/flash access time */ 332 333#define CONFIG_SYS_REFINT 430 /* # of clocks between CBR refresh cycles */ 334 335#define CONFIG_SYS_DBUS_SIZE2 1 /* set for 8-bit RCS1, clear for 32,64 */ 336 337/* the following are for SDRAM only*/ 338#define CONFIG_SYS_BSTOPRE 121 /* Burst To Precharge, sets open page interval */ 339#define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */ 340#define CONFIG_SYS_RDLAT 4 /* data latency from read command */ 341#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */ 342#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */ 343#define CONFIG_SYS_ACTORW 3 /* Activate to R/W */ 344#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ 345#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */ 346#if 0 347#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* OBSOLETE! SDMODE Burst length 2=4, 3=8 */ 348#endif 349 350#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 351#define CONFIG_SYS_EXTROM 1 352#define CONFIG_SYS_REGDIMM 0 353 354 355/* memory bank settings*/ 356/* 357 * only bits 20-29 are actually used from these vales to set the 358 * start/end address the upper two bits will be 0, and the lower 20 359 * bits will be set to 0x00000 for a start address, or 0xfffff for an 360 * end address 361 */ 362#define CONFIG_SYS_BANK0_START 0x00000000 363#define CONFIG_SYS_BANK0_END (0x4000000 - 1) 364#define CONFIG_SYS_BANK0_ENABLE 1 365#define CONFIG_SYS_BANK1_START 0x04000000 366#define CONFIG_SYS_BANK1_END (0x8000000 - 1) 367#define CONFIG_SYS_BANK1_ENABLE 1 368#define CONFIG_SYS_BANK2_START 0x3ff00000 369#define CONFIG_SYS_BANK2_END 0x3fffffff 370#define CONFIG_SYS_BANK2_ENABLE 0 371#define CONFIG_SYS_BANK3_START 0x3ff00000 372#define CONFIG_SYS_BANK3_END 0x3fffffff 373#define CONFIG_SYS_BANK3_ENABLE 0 374#define CONFIG_SYS_BANK4_START 0x00000000 375#define CONFIG_SYS_BANK4_END 0x00000000 376#define CONFIG_SYS_BANK4_ENABLE 0 377#define CONFIG_SYS_BANK5_START 0x00000000 378#define CONFIG_SYS_BANK5_END 0x00000000 379#define CONFIG_SYS_BANK5_ENABLE 0 380#define CONFIG_SYS_BANK6_START 0x00000000 381#define CONFIG_SYS_BANK6_END 0x00000000 382#define CONFIG_SYS_BANK6_ENABLE 0 383#define CONFIG_SYS_BANK7_START 0x00000000 384#define CONFIG_SYS_BANK7_END 0x00000000 385#define CONFIG_SYS_BANK7_ENABLE 0 386/* 387 * Memory bank enable bitmask, specifying which of the banks defined above 388 are actually present. MSB is for bank #7, LSB is for bank #0. 389 */ 390#define CONFIG_SYS_BANK_ENABLE 0x01 391 392#define CONFIG_SYS_ODCR 0x75 /* configures line driver impedances, */ 393 /* see 8240 book for bit definitions */ 394#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */ 395 /* currently accessed page in memory */ 396 /* see 8240 book for details */ 397 398/* SDRAM 0 - 256MB */ 399#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 400#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 401 402/* stack in DCACHE @ 1GB (no backing mem) */ 403#if defined(USE_DINK32) 404#define CONFIG_SYS_IBAT1L (0x40000000 | BATL_PP_00 ) 405#define CONFIG_SYS_IBAT1U (0x40000000 | BATU_BL_128K ) 406#else 407#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) 408#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 409#endif 410 411/* PCI memory */ 412#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) 413#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) 414 415/* Flash, config addrs, etc */ 416#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) 417#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 418 419#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 420#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 421#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 422#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 423#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 424#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 425#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 426#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 427 428/* 429 * For booting Linux, the board info and command line data 430 * have to be in the first 8 MB of memory, since this is 431 * the maximum mapped by the Linux kernel during initialization. 432 */ 433#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 434/*----------------------------------------------------------------------- 435 * FLASH organization 436 */ 437#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 438#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 439 440#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 441#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 442 443/*----------------------------------------------------------------------- 444 * Cache Configuration 445 */ 446#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */ 447#if defined(CONFIG_CMD_KGDB) 448# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 449#endif 450 451/* values according to the manual */ 452 453#define CONFIG_DRAM_50MHZ 1 454#define CONFIG_SDRAM_50MHZ 455 456#define CONFIG_DISK_SPINUP_TIME 1000000 457 458#endif /* __CONFIG_H */ 459