LXR uboot/include/configs/inka4x0.h

   1/*
   2 * (C) Copyright 2009
   3 * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
   4 *
   5 * (C) Copyright 2003-2005
   6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   7 *
   8 * See file CREDITS for list of people who contributed to this
   9 * project.
  10 *
  11 * This program is free software; you can redistribute it and/or
  12 * modify it under the terms of the GNU General Public License as
  13 * published by the Free Software Foundation; either version 2 of
  14 * the License, or (at your option) any later version.
  15 *
  16 * This program is distributed in the hope that it will be useful,
  17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 * GNU General Public License for more details.
  20 *
  21 * You should have received a copy of the GNU General Public License
  22 * along with this program; if not, write to the Free Software
  23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24 * MA 02111-1307 USA
  25 */
  26
  27#ifndef __CONFIG_H
  28#define __CONFIG_H
  29
  30/*
  31 * High Level Configuration Options
  32 * (easy to change)
  33 */
  34
  35#define CONFIG_MPC5xxx          1       /* This is an MPC5xxx CPU               */
  36#define CONFIG_MPC5200          1       /* (more precisely an MPC5200 CPU)      */
  37#define CONFIG_INKA4X0          1       /* INKA4x0 board                        */
  38
  39/*
  40 * Valid values for CONFIG_SYS_TEXT_BASE are:
  41 * 0xFFE00000   boot low
  42 * 0x00100000   boot from RAM (for testing only)
  43 */
  44#ifndef CONFIG_SYS_TEXT_BASE
  45#define CONFIG_SYS_TEXT_BASE    0xFFE00000      /* Standard: boot low */
  46#endif
  47#define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds"
  48
  49#define CONFIG_SYS_MPC5XXX_CLKIN        33000000 /* ... running at 33.000000MHz         */
  50
  51#define CONFIG_MISC_INIT_F      1       /* Use misc_init_f()                    */
  52
  53#define CONFIG_HIGH_BATS        1       /* High BATs supported                  */
  54
  55/*
  56 * Serial console configuration
  57 */
  58#define CONFIG_PSC_CONSOLE      1       /* console is on PSC1   */
  59#define CONFIG_BAUDRATE         115200  /* ... at 115200 bps    */
  60#define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
  61
  62/*
  63 * PCI Mapping:
  64 * 0x40000000 - 0x4fffffff - PCI Memory
  65 * 0x50000000 - 0x50ffffff - PCI IO Space
  66 */
  67#define CONFIG_PCI              1
  68#define CONFIG_PCI_PNP          1
  69#define CONFIG_PCI_SCAN_SHOW    1
  70#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
  71
  72#define CONFIG_PCI_MEM_BUS      0x40000000
  73#define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  74#define CONFIG_PCI_MEM_SIZE     0x10000000
  75
  76#define CONFIG_PCI_IO_BUS       0x50000000
  77#define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
  78#define CONFIG_PCI_IO_SIZE      0x01000000
  79
  80#define CONFIG_SYS_XLB_PIPELINING       1
  81
  82/* Partitions */
  83#define CONFIG_MAC_PARTITION
  84#define CONFIG_DOS_PARTITION
  85#define CONFIG_ISO_PARTITION
  86
  87
  88/*
  89 * BOOTP options
  90 */
  91#define CONFIG_BOOTP_BOOTFILESIZE
  92#define CONFIG_BOOTP_BOOTPATH
  93#define CONFIG_BOOTP_GATEWAY
  94#define CONFIG_BOOTP_HOSTNAME
  95
  96
  97/*
  98 * Command line configuration.
  99 */
 100#include <config_cmd_default.h>
 101
 102#define CONFIG_CMD_DATE
 103#define CONFIG_CMD_DHCP
 104#define CONFIG_CMD_EXT2
 105#define CONFIG_CMD_FAT
 106#define CONFIG_CMD_IDE
 107#define CONFIG_CMD_NFS
 108#define CONFIG_CMD_PCI
 109#define CONFIG_CMD_PING
 110#define CONFIG_CMD_SNTP
 111#define CONFIG_CMD_USB
 112
 113#define CONFIG_TIMESTAMP        1       /* Print image info with timestamp */
 114
 115#if (CONFIG_SYS_TEXT_BASE == 0xFFE00000)                /* Boot low */
 116#   define CONFIG_SYS_LOWBOOT           1
 117#endif
 118
 119/*
 120 * Autobooting
 121 */
 122#define CONFIG_BOOTDELAY        1       /* autoboot after 1 second */
 123
 124#define CONFIG_PREBOOT  "echo;" \
 125        "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 126        "echo"
 127
 128#undef  CONFIG_BOOTARGS
 129
 130#define CONFIG_ETHADDR          00:a0:a4:03:00:00
 131#define CONFIG_OVERWRITE_ETHADDR_ONCE
 132
 133#define CONFIG_IPADDR           192.168.100.2
 134#define CONFIG_SERVERIP         192.168.100.1
 135#define CONFIG_NETMASK          255.255.255.0
 136#define HOSTNAME                inka4x0
 137#define CONFIG_BOOTFILE         "/tftpboot/inka4x0/uImage"
 138#define CONFIG_ROOTPATH         "/opt/eldk/ppc_6xx"
 139
 140#define CONFIG_EXTRA_ENV_SETTINGS                                       \
 141        "netdev=eth0\0"                                                 \
 142        "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 143                "nfsroot=${serverip}:${rootpath}\0"                     \
 144        "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 145        "addip=setenv bootargs ${bootargs} "                            \
 146                "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 147                ":${hostname}:${netdev}:off panic=1\0"                  \
 148        "addcons=setenv bootargs ${bootargs} "                          \
 149                "console=ttyS0,${baudrate}\0"                           \
 150        "flash_nfs=run nfsargs addip addcons;"                          \
 151                "bootm ${kernel_addr}\0"                                \
 152        "net_nfs=tftp 200000 ${bootfile};"                              \
 153                "run nfsargs addip addcons;bootm\0"                     \
 154        "enable_disp=mw.l 100000 04000000 1;"                           \
 155                "cp.l 100000 f0000b20 1;"                               \
 156                "cp.l 100000 f0000b28 1\0"                              \
 157        "ideargs=setenv bootargs root=/dev/hda1 rw\0"                   \
 158        "ide_boot=ext2load ide 0:1 200000 uImage;"                      \
 159                "run ideargs addip addcons enable_disp;bootm\0"         \
 160        "brightness=255\0"                                              \
 161        ""
 162
 163#define CONFIG_BOOTCOMMAND      "run ide_boot"
 164
 165/*
 166 * IPB Bus clocking configuration.
 167 */
 168#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK         /* define for 133MHz speed */
 169
 170/*
 171 * Flash configuration
 172 */
 173#define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant */
 174#define CONFIG_FLASH_CFI_DRIVER 1
 175#define CONFIG_SYS_FLASH_BASE           0xffe00000
 176#define CONFIG_SYS_FLASH_SIZE           0x00200000
 177#define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks */
 178#define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 179#define CONFIG_SYS_MAX_FLASH_SECT       128     /* max num of sects on one chip */
 180#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster) */
 181
 182/*
 183 * Environment settings
 184 */
 185#define CONFIG_ENV_IS_IN_FLASH  1
 186#define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x4000)
 187#define CONFIG_ENV_SIZE         0x2000
 188#define CONFIG_ENV_SECT_SIZE    0x2000
 189#define CONFIG_ENV_OVERWRITE    1
 190#define CONFIG_SYS_USE_PPCENV                   /* Environment embedded in sect .ppcenv */
 191
 192/*
 193 * Memory map
 194 */
 195#define CONFIG_SYS_MBAR         0xF0000000
 196#define CONFIG_SYS_SDRAM_BASE           0x00000000
 197#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
 198
 199/*
 200 * SDRAM controller configuration
 201 */
 202#undef CONFIG_SDR_MT48LC16M16A2
 203#undef CONFIG_DDR_MT46V16M16
 204#undef CONFIG_DDR_MT46V32M16
 205#undef CONFIG_DDR_HYB25D512160BF
 206#define CONFIG_DDR_K4H511638C
 207
 208/* Use ON-Chip SRAM until RAM will be available */
 209#define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 210
 211/* preserve space for the post_word at end of on-chip SRAM */
 212#define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)
 213
 214#ifdef CONFIG_POST
 215#define CONFIG_SYS_INIT_RAM_SIZE        MPC5XXX_SRAM_POST_SIZE
 216#else
 217#define CONFIG_SYS_INIT_RAM_SIZE        MPC5XXX_SRAM_SIZE
 218#endif
 219
 220#define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 221#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 222
 223#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
 224#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 225#   define CONFIG_SYS_RAMBOOT           1
 226#endif
 227
 228#define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 229#define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 230#define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 231
 232/*
 233 * Ethernet configuration
 234 */
 235#define CONFIG_MPC5xxx_FEC      1
 236#define CONFIG_MPC5xxx_FEC_MII100
 237/*
 238 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
 239 */
 240/* #define CONFIG_MPC5xxx_FEC_MII10 */
 241#define CONFIG_PHY_ADDR         0x00
 242#define CONFIG_MII
 243
 244/*
 245 * GPIO configuration
 246 *
 247 * use CS1 as gpio_wkup_6 output
 248 *      Bit 0 (mask: 0x80000000): 0
 249 * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
 250 *      00 -> No Alternatives, I2C1 is used for onboard EEPROM
 251 *      01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard
 252 *            EEPROM
 253 * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
 254 * use PSC2 as UART: Bits 24-27 (mask: 0x00000070): 0100
 255 * use PSC3 as UART: Bits 20-23 (mask: 0x00000700): 0100
 256 * use PSC6 as UART: Bits  9-11 (mask: 0x00700000): 0101
 257 */
 258#define CONFIG_SYS_GPS_PORT_CONFIG      0x01501444
 259
 260/*
 261 * RTC configuration
 262 */
 263#define CONFIG_RTC_RTC4543      1       /* use external RTC */
 264
 265/*
 266 * Software (bit-bang) three wire serial configuration
 267 *
 268 * Note that we need the ifdefs because otherwise compilation of
 269 * mkimage.c fails.
 270 */
 271#define CONFIG_SOFT_TWS         1
 272
 273#ifdef TWS_IMPLEMENTATION
 274#include <mpc5xxx.h>
 275#include <asm/io.h>
 276
 277#define TWS_CE          MPC5XXX_GPIO_WKUP_PSC1_4 /* GPIO_WKUP_0 */
 278#define TWS_WR          MPC5XXX_GPIO_WKUP_PSC2_4 /* GPIO_WKUP_1 */
 279#define TWS_DATA        MPC5XXX_GPIO_SINT_PSC3_4 /* GPIO_SINT_0 */
 280#define TWS_CLK         MPC5XXX_GPIO_SINT_PSC3_5 /* GPIO_SINT_1 */
 281
 282static inline void tws_ce(unsigned bit)
 283{
 284        struct mpc5xxx_wu_gpio *wu_gpio =
 285                (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
 286        if (bit)
 287                setbits_8(&wu_gpio->dvo, TWS_CE);
 288        else
 289                clrbits_8(&wu_gpio->dvo, TWS_CE);
 290}
 291
 292static inline void tws_wr(unsigned bit)
 293{
 294        struct mpc5xxx_wu_gpio *wu_gpio =
 295                (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
 296        if (bit)
 297                setbits_8(&wu_gpio->dvo, TWS_WR);
 298        else
 299                clrbits_8(&wu_gpio->dvo, TWS_WR);
 300}
 301
 302static inline void tws_clk(unsigned bit)
 303{
 304        struct mpc5xxx_gpio *gpio =
 305                (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
 306        if (bit)
 307                setbits_8(&gpio->sint_dvo, TWS_CLK);
 308        else
 309                clrbits_8(&gpio->sint_dvo, TWS_CLK);
 310}
 311
 312static inline void tws_data(unsigned bit)
 313{
 314        struct mpc5xxx_gpio *gpio =
 315                (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
 316        if (bit)
 317                setbits_8(&gpio->sint_dvo, TWS_DATA);
 318        else
 319                clrbits_8(&gpio->sint_dvo, TWS_DATA);
 320}
 321
 322static inline unsigned tws_data_read(void)
 323{
 324        struct mpc5xxx_gpio *gpio =
 325                        (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
 326        return !!(in_8(&gpio->sint_ival) & TWS_DATA);
 327}
 328
 329static inline void tws_data_config_output(unsigned output)
 330{
 331        struct mpc5xxx_gpio *gpio =
 332                (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
 333        if (output)
 334                setbits_8(&gpio->sint_ddr, TWS_DATA);
 335        else
 336                clrbits_8(&gpio->sint_ddr, TWS_DATA);
 337}
 338#endif /* TWS_IMPLEMENTATION */
 339
 340/*
 341 * Miscellaneous configurable options
 342 */
 343#define CONFIG_SYS_LONGHELP                     /* undef to save memory     */
 344#define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt   */
 345#if defined(CONFIG_CMD_KGDB)
 346#define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size  */
 347#else
 348#define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size  */
 349#endif
 350#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 351#define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 352#define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 353
 354#define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC5xxx CPUs                     */
 355#if defined(CONFIG_CMD_KGDB)
 356#  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value        */
 357#endif
 358
 359/* Enable an alternate, more extensive memory test */
 360#define CONFIG_SYS_ALT_MEMTEST
 361
 362#define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on */
 363#define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 1 ... 15 MB in DRAM  */
 364
 365#define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 366
 367#define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 368
 369/*
 370 * Enable loopw command.
 371 */
 372#define CONFIG_LOOPW
 373
 374/*
 375 * Various low-level settings
 376 */
 377#define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 378#define CONFIG_SYS_HID0_FINAL           HID0_ICE
 379
 380#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
 381#define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 382#define CONFIG_SYS_BOOTCS_CFG           0x00087800 /* for pci_clk  = 66 MHz */
 383#define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 384#define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 385
 386/* 32Mbit SRAM @0x30000000 */
 387#define CONFIG_SYS_CS1_START            0x30000000
 388#define CONFIG_SYS_CS1_SIZE             0x00400000
 389#define CONFIG_SYS_CS1_CFG              0x31800 /* for pci_clk = 33 MHz */
 390
 391/* 2 quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
 392#define CONFIG_SYS_CS2_START            0x80000000
 393#define CONFIG_SYS_CS2_SIZE             0x0001000
 394#define CONFIG_SYS_CS2_CFG              0x21800  /* for pci_clk = 33 MHz */
 395
 396/* GPIO in @0x30400000 */
 397#define CONFIG_SYS_CS3_START            0x30400000
 398#define CONFIG_SYS_CS3_SIZE             0x00100000
 399#define CONFIG_SYS_CS3_CFG              0x31800 /* for pci_clk = 33 MHz */
 400
 401#define CONFIG_SYS_CS_BURST             0x00000000
 402#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
 403
 404/*-----------------------------------------------------------------------
 405 * USB stuff
 406 *-----------------------------------------------------------------------
 407 */
 408#define CONFIG_USB_OHCI
 409#define CONFIG_USB_CLOCK        0x00015555
 410#define CONFIG_USB_CONFIG       0x00001000
 411#define CONFIG_USB_STORAGE
 412
 413/*-----------------------------------------------------------------------
 414 * IDE/ATA stuff Supports IDE harddisk
 415 *-----------------------------------------------------------------------
 416 */
 417
 418#undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
 419
 420#undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 421#undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 422
 423#define CONFIG_IDE_PREINIT
 424
 425#define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 426#define CONFIG_SYS_IDE_MAXDEVICE        2       /* max. 1 drive per IDE bus     */
 427
 428#define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 429#define CONFIG_SYS_ATA_BASE_ADDR        MPC5XXX_ATA
 430#define CONFIG_SYS_ATA_DATA_OFFSET      0x0060  /* Offset for data I/O          */
 431#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) /* Offset for normal register accesses */
 432#define CONFIG_SYS_ATA_ALT_OFFSET       0x005C  /* Offset for alternate registers */
 433#define CONFIG_SYS_ATA_STRIDE          4        /* Interval between registers   */
 434
 435#define CONFIG_ATAPI            1
 436
 437#define CONFIG_SYS_BRIGHTNESS          0xFF     /* LCD Default Brightness (255 = off) */
 438
 439#endif /* __CONFIG_H */
 440