1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31
32
33
34
35
36
37#define CONFIG_460EX 1
38#ifdef CONFIG_DEVCONCENTER
39#define CONFIG_HOSTNAME devconcenter
40#define CONFIG_IDENT_STRING " devconcenter 0.06"
41#else
42#define CONFIG_HOSTNAME intip
43#define CONFIG_IDENT_STRING " intip 0.06"
44#endif
45#define CONFIG_440 1
46#define CONFIG_4xx 1
47
48#ifndef CONFIG_SYS_TEXT_BASE
49#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
50#endif
51
52
53
54
55#include "amcc-common.h"
56
57#define CONFIG_SYS_CLK_FREQ 66666667
58
59#define CONFIG_BOARD_EARLY_INIT_F 1
60#define CONFIG_BOARD_EARLY_INIT_R 1
61#define CONFIG_MISC_INIT_R 1
62#define CONFIG_BOARD_TYPES 1
63#define CONFIG_FIT
64#define CFG_ALT_MEMTEST
65
66#undef CONFIG_ZERO_BOOTDELAY_CHECK
67#define CONFIG_AUTOBOOT_KEYED
68#define CONFIG_AUTOBOOT_STOP_STR " "
69
70
71
72
73
74#define CONFIG_SYS_PCI_MEMBASE 0x80000000
75#define CONFIG_SYS_PCI_BASE 0xd0000000
76#define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
77
78
79#ifdef CONFIG_DEVCONCENTER
80#define CONFIG_SYS_FLASH_BASE 0xF8000000
81#define CONFIG_SYS_FLASH_SIZE (128 << 20)
82#else
83#define CONFIG_SYS_FLASH_BASE 0xFC000000
84#define CONFIG_SYS_FLASH_SIZE (64 << 20)
85#endif
86
87#define CONFIG_SYS_NVRAM_BASE 0xE0000000
88#define CONFIG_SYS_UART_BASE 0xE0100000
89#define CONFIG_SYS_IO_BASE 0xE0200000
90
91#define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000
92#define CONFIG_SYS_FLASH_BASE_PHYS_H 0x4
93#ifdef CONFIG_DEVCONCENTER
94#define CONFIG_SYS_FLASH_BASE_PHYS_L 0xC8000000
95#else
96#define CONFIG_SYS_FLASH_BASE_PHYS_L 0xCC000000
97#endif
98#define CONFIG_SYS_FLASH_BASE_PHYS \
99 (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) \
100 | (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
101
102#define CONFIG_SYS_OCM_BASE 0xE3000000
103#define CONFIG_SYS_SRAM_BASE 0xE8000000
104#define CONFIG_SYS_SRAM_SIZE (256 << 10)
105#define CONFIG_SYS_LOCAL_CONF_REGS 0xEF000000
106
107#define CONFIG_SYS_AHB_BASE 0xE2000000
108
109
110
111
112#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE
113#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
114#define CONFIG_SYS_GBL_DATA_OFFSET \
115 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
116#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
117
118
119
120
121#define CONFIG_CONS_INDEX 1
122
123
124
125
126
127
128
129#define CONFIG_ENV_IS_IN_FLASH 1
130#define CONFIG_SYS_NOR_CS 0
131
132
133
134
135#define CONFIG_SYS_FLASH_CFI
136#define CONFIG_FLASH_CFI_DRIVER
137#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
138
139#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
140#define CONFIG_SYS_MAX_FLASH_BANKS 1
141#ifdef CONFIG_DEVCONCENTER
142#define CONFIG_SYS_MAX_FLASH_SECT 1024
143#else
144#define CONFIG_SYS_MAX_FLASH_SECT 512
145#endif
146
147#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
148#define CONFIG_SYS_FLASH_WRITE_TOUT 500
149
150#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
151#define CONFIG_SYS_FLASH_EMPTY_INFO
152
153#ifdef CONFIG_ENV_IS_IN_FLASH
154#define CONFIG_ENV_SECT_SIZE 0x20000
155#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
156#define CONFIG_ENV_SIZE 0x4000
157
158
159#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
160#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
161#endif
162
163
164
165
166
167#define CONFIG_AUTOCALIB "silent\0"
168
169#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION
170#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION
171#undef CONFIG_PPC4xx_DDR_METHOD_A
172
173
174
175#define CONFIG_SYS_SDRAM_R0BAS 0x0000f800
176#define CONFIG_SYS_SDRAM_R1BAS 0x00000000
177#define CONFIG_SYS_SDRAM_R2BAS 0x00000000
178#define CONFIG_SYS_SDRAM_R3BAS 0x00000000
179#define CONFIG_SYS_SDRAM_PLBADDULL 0x00000000
180#define CONFIG_SYS_SDRAM_PLBADDUHB 0x00000008
181#define CONFIG_SYS_SDRAM_CONF1LL 0x80001C00
182#define CONFIG_SYS_SDRAM_CONF1HB 0x80001C80
183#define CONFIG_SYS_SDRAM_CONFPATHB 0x10a68000
184
185
186#define CONFIG_SYS_SDRAM0_MB0CF 0x00000201
187#define CONFIG_SYS_SDRAM0_MB1CF 0x00000000
188#define CONFIG_SYS_SDRAM0_MB2CF 0x00000000
189#define CONFIG_SYS_SDRAM0_MB3CF 0x00000000
190#define CONFIG_SYS_SDRAM0_MCOPT1 0x05120000
191#define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000
192#define CONFIG_SYS_SDRAM0_MODT0 0x00000000
193#define CONFIG_SYS_SDRAM0_MODT1 0x00000000
194#define CONFIG_SYS_SDRAM0_MODT2 0x00000000
195#define CONFIG_SYS_SDRAM0_MODT3 0x00000000
196#define CONFIG_SYS_SDRAM0_CODT 0x00000020
197#define CONFIG_SYS_SDRAM0_RTR 0x06180000
198#define CONFIG_SYS_SDRAM0_INITPLR0 0xA8380000
199#define CONFIG_SYS_SDRAM0_INITPLR1 0x81900400
200#define CONFIG_SYS_SDRAM0_INITPLR2 0x81020000
201#define CONFIG_SYS_SDRAM0_INITPLR3 0x81030000
202#define CONFIG_SYS_SDRAM0_INITPLR4 0x81010002
203#define CONFIG_SYS_SDRAM0_INITPLR5 0xE4000552
204#define CONFIG_SYS_SDRAM0_INITPLR6 0x81900400
205#define CONFIG_SYS_SDRAM0_INITPLR7 0x8A880000
206#define CONFIG_SYS_SDRAM0_INITPLR8 0x8A880000
207#define CONFIG_SYS_SDRAM0_INITPLR9 0x8A880000
208#define CONFIG_SYS_SDRAM0_INITPLR10 0x8A880000
209#define CONFIG_SYS_SDRAM0_INITPLR11 0x81000452
210#define CONFIG_SYS_SDRAM0_INITPLR12 0x81010382
211#define CONFIG_SYS_SDRAM0_INITPLR13 0x81010002
212#define CONFIG_SYS_SDRAM0_INITPLR14 0x00000000
213#define CONFIG_SYS_SDRAM0_INITPLR15 0x00000000
214#define CONFIG_SYS_SDRAM0_RQDC 0x80000038
215#define CONFIG_SYS_SDRAM0_RFDC 0x00000257
216#define CONFIG_SYS_SDRAM0_RDCC 0x40000000
217#define CONFIG_SYS_SDRAM0_DLCR 0x00000000
218#define CONFIG_SYS_SDRAM0_CLKTR 0x40000000
219#define CONFIG_SYS_SDRAM0_WRDTR 0x86000823
220#define CONFIG_SYS_SDRAM0_SDTR1 0x80201000
221#define CONFIG_SYS_SDRAM0_SDTR2 0x32204232
222#define CONFIG_SYS_SDRAM0_SDTR3 0x090C0D15
223#define CONFIG_SYS_SDRAM0_MMODE 0x00000452
224#define CONFIG_SYS_SDRAM0_MEMODE 0x00000002
225
226#define CONFIG_SYS_MBYTES_SDRAM 256
227
228
229
230
231#define CONFIG_SYS_I2C_SPEED 400000
232
233#define CONFIG_SYS_I2C_MULTI_EEPROMS
234#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
235#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
236#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
237#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
238
239
240#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x54
241#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
242#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
243
244
245#define CONFIG_DTT_LM63 1
246#define CONFIG_DTT_SENSORS { 0 }
247#define CONFIG_DTT_PWM_LOOKUPTABLE \
248 { { 40, 10 }, { 50, 20 }, { 60, 40 } }
249#define CONFIG_DTT_TACH_LIMIT 0xa10
250
251
252#define CONFIG_RTC_DS1337 1
253#define CONFIG_SYS_I2C_RTC_ADDR 0x68
254
255
256
257
258#define CONFIG_IBM_EMAC4_V4 1
259
260#define CONFIG_HAS_ETH0
261#define CONFIG_HAS_ETH1
262
263#define CONFIG_PHY_ADDR 2
264#define CONFIG_PHY1_ADDR 3
265
266#define CONFIG_PHY_RESET 1
267#define CONFIG_PHY_GIGE 1
268#define CONFIG_PHY_DYNAMIC_ANEG 1
269
270
271
272
273#define CONFIG_USB_OHCI_NEW
274#define CONFIG_USB_STORAGE
275#undef CONFIG_SYS_OHCI_BE_CONTROLLER
276#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
277#define CONFIG_SYS_OHCI_USE_NPS
278#define CONFIG_SYS_USB_OHCI_REGS_BASE (CONFIG_SYS_AHB_BASE | 0xd0000)
279#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440"
280#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
281
282
283
284
285#define CONFIG_EXTRA_ENV_SETTINGS \
286 CONFIG_AMCC_DEF_ENV \
287 CONFIG_AMCC_DEF_ENV_POWERPC \
288 CONFIG_AMCC_DEF_ENV_NOR_UPD \
289 "kernel_addr=fc000000\0" \
290 "fdt_addr=fc1e0000\0" \
291 "ramdisk_addr=fc200000\0" \
292 "pciconfighost=1\0" \
293 "pcie_mode=RP:RP\0" \
294 ""
295
296
297
298
299#define CONFIG_CMD_CHIP_CONFIG
300#define CONFIG_CMD_DATE
301#define CONFIG_CMD_DTT
302#define CONFIG_CMD_EXT2
303#define CONFIG_CMD_FAT
304#define CONFIG_CMD_PCI
305#define CONFIG_CMD_SDRAM
306#define CONFIG_CMD_SNTP
307#define CONFIG_CMD_USB
308
309
310#define CONFIG_MAC_PARTITION
311#define CONFIG_DOS_PARTITION
312#define CONFIG_ISO_PARTITION
313
314
315
316
317
318#define CONFIG_PCI
319#define CONFIG_PCI_PNP
320#define CONFIG_PCI_SCAN_SHOW
321#define CONFIG_PCI_CONFIG_HOST_BRIDGE
322#define CONFIG_PCI_DISABLE_PCIE
323
324
325#define CONFIG_SYS_PCI_TARGET_INIT
326#undef CONFIG_SYS_PCI_MASTER_INIT
327
328#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014
329#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348#define CONFIG_SYS_EBC_PB0AP 0x10055e00
349#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000)
350
351
352#define CONFIG_SYS_EBC_PB1AP 0x02815480
353
354#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_NVRAM_BASE | 0x18000)
355
356
357#define CONFIG_SYS_EBC_PB2AP 0x02815480
358
359#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_UART_BASE | 0x1A000)
360
361
362#define CONFIG_SYS_EBC_PB3AP 0x02815480
363
364#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_IO_BASE | 0x1A000)
365
366
367
368
369
370#define CONFIG_SYS_4xx_GPIO_TABLE { \
371{ \
372 \
373{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, \
374{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, \
375{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, \
376{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, \
377{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, \
378{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, \
379{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, \
380{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, \
381{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, \
382{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, \
383{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, \
384{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, \
385{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, \
386{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, \
387{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, \
388{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, \
389{GPIO0_BASE, GPIO_IN , GPIO_SEL, GPIO_OUT_0}, \
390{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
391{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
392{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, \
393{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
394{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
395{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
396{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
397{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
398{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
399{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
400{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
401{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
402{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
403{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, \
404{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, \
405}, \
406{ \
407 \
408{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, \
409{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, \
410{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, \
411{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, \
412{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, \
413{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, \
414{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, \
415{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, \
416{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
417{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
418{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
419{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
420{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, \
421{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, \
422{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
423{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
424{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
425{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
426{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
427{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, \
428{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, \
429{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
430{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, \
431{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, \
432{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, \
433{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
434{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
435{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
436{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
437{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, \
438{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, \
439{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
440} \
441}
442
443#endif
444