LXR uboot/include/configs/iocon.h

   1/*
   2 * (C) Copyright 2010
   3 * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24#ifndef __CONFIG_H
  25#define __CONFIG_H
  26
  27#define CONFIG_405EP            1       /* this is a PPC405 CPU */
  28#define CONFIG_4xx              1       /*  member of PPC4xx family */
  29#define CONFIG_IOCON            1       /*  on a IoCon board */
  30
  31#define CONFIG_SYS_TEXT_BASE    0xFFFC0000
  32
  33/*
  34 * Include common defines/options for all AMCC eval boards
  35 */
  36#define CONFIG_HOSTNAME         iocon
  37#define CONFIG_IDENT_STRING     " iocon 0.04"
  38#include "amcc-common.h"
  39
  40#define CONFIG_BOARD_EARLY_INIT_F
  41#define CONFIG_BOARD_EARLY_INIT_R
  42#define CONFIG_LAST_STAGE_INIT
  43
  44#define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
  45
  46/*
  47 * Configure PLL
  48 */
  49#define PLLMR0_DEFAULT PLLMR0_266_133_66
  50#define PLLMR1_DEFAULT PLLMR1_266_133_66
  51
  52#undef CONFIG_ZERO_BOOTDELAY_CHECK      /* ignore keypress on bootdelay==0 */
  53#define CONFIG_AUTOBOOT_KEYED           /* use key strings to stop autoboot */
  54#define CONFIG_AUTOBOOT_STOP_STR " "
  55
  56/* new uImage format support */
  57#define CONFIG_FIT
  58#define CONFIG_FIT_VERBOSE      /* enable fit_format_{error,warning}() */
  59
  60#define CONFIG_ENV_IS_IN_FLASH  /* use FLASH for environment vars */
  61
  62/*
  63 * Default environment variables
  64 */
  65#define CONFIG_EXTRA_ENV_SETTINGS                                       \
  66        CONFIG_AMCC_DEF_ENV                                             \
  67        CONFIG_AMCC_DEF_ENV_POWERPC                                     \
  68        CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
  69        "kernel_addr=fc000000\0"                                        \
  70        "fdt_addr=fc1e0000\0"                                           \
  71        "ramdisk_addr=fc200000\0"                                       \
  72        ""
  73
  74#define CONFIG_PHY_ADDR         4       /* PHY address                  */
  75#define CONFIG_HAS_ETH0
  76#define CONFIG_PHY_CLK_FREQ    EMAC_STACR_CLK_66MHZ
  77
  78/*
  79 * Commands additional to the ones defined in amcc-common.h
  80 */
  81#define CONFIG_CMD_CACHE
  82#undef CONFIG_CMD_EEPROM
  83
  84/*
  85 * SDRAM configuration (please see cpu/ppc/sdram.[ch])
  86 */
  87#define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0 */
  88
  89/* SDRAM timings used in datasheet */
  90#define CONFIG_SYS_SDRAM_CL             3       /* CAS latency */
  91#define CONFIG_SYS_SDRAM_tRP           20       /* PRECHARGE command period */
  92#define CONFIG_SYS_SDRAM_tRC           66       /* ACTIVE-to-ACTIVE period */
  93#define CONFIG_SYS_SDRAM_tRCD          20       /* ACTIVE-to-READ delay */
  94#define CONFIG_SYS_SDRAM_tRFC          66       /* Auto refresh period */
  95
  96/*
  97 * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
  98 * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
  99 * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
 100 * The Linux BASE_BAUD define should match this configuration.
 101 *    baseBaud = cpuClock/(uartDivisor*16)
 102 * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
 103 * set Linux BASE_BAUD to 403200.
 104 */
 105#define CONFIG_CONS_INDEX               1       /* Use UART0 */
 106#undef  CONFIG_SYS_EXT_SERIAL_CLOCK             /* external serial clock */
 107#undef  CONFIG_SYS_405_UART_ERRATA_59           /* 405GP/CR Rev. D silicon */
 108#define CONFIG_SYS_BASE_BAUD            691200
 109
 110/*
 111 * I2C stuff
 112 */
 113#define CONFIG_SYS_I2C_SPEED            400000
 114
 115/* enable I2C and select the hardware/software driver */
 116#undef  CONFIG_HARD_I2C                 /* I2C with hardware support    */
 117#define CONFIG_SOFT_I2C         1       /* I2C bit-banged               */
 118
 119/*
 120 * Software (bit-bang) I2C driver configuration
 121 */
 122
 123#ifndef __ASSEMBLY__
 124void fpga_gpio_set(int pin);
 125void fpga_gpio_clear(int pin);
 126int fpga_gpio_get(int pin);
 127#endif
 128
 129#define I2C_ACTIVE      { }
 130#define I2C_TRISTATE    { }
 131#define I2C_READ        fpga_gpio_get(0x0040) ? 1 : 0
 132#define I2C_SDA(bit)    if (bit) fpga_gpio_set(0x0040); \
 133                        else fpga_gpio_clear(0x0040)
 134#define I2C_SCL(bit)    if (bit) fpga_gpio_set(0x0020); \
 135                        else fpga_gpio_clear(0x0020)
 136#define I2C_DELAY       udelay(25)      /* 1/4 I2C clock duration */
 137
 138/*
 139 * OSD hardware
 140 */
 141#define CONFIG_SYS_MPC92469AC
 142#define CONFIG_SYS_CH7301
 143
 144/*
 145 * FLASH organization
 146 */
 147#define CONFIG_SYS_FLASH_CFI            /* The flash is CFI compatible  */
 148#define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver        */
 149
 150#define CONFIG_SYS_FLASH_BASE           0xFC000000
 151#define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 152
 153#define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks */
 154#define CONFIG_SYS_MAX_FLASH_SECT       512     /* max num of sectors per chip*/
 155
 156#define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase/ms */
 157#define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write/ms */
 158
 159#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buff'd writes */
 160#define CONFIG_SYS_FLASH_PROTECTION     1       /* use hardware flash protect */
 161
 162#define CONFIG_SYS_FLASH_EMPTY_INFO     /* 'E' for empty sector on flinfo */
 163#define CONFIG_SYS_FLASH_QUIET_TEST     1       /* no warn upon unknown flash */
 164
 165#ifdef CONFIG_ENV_IS_IN_FLASH
 166#define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector */
 167#define CONFIG_ENV_ADDR         ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
 168#define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector */
 169
 170/* Address and size of Redundant Environment Sector     */
 171#define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 172#define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 173#endif
 174
 175/*
 176 * PPC405 GPIO Configuration
 177 */
 178#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO     Alternate1      */ \
 179{ \
 180/* GPIO Core 0 */ \
 181{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0   PerBLast */ \
 182{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO1   TS1E */ \
 183{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO2   TS2E */ \
 184{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO3   TS1O */ \
 185{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO4   TS2O */ \
 186{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1      }, /* GPIO5   TS3 */ \
 187{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO6   TS4 */ \
 188{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO7   TS5 */ \
 189{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO8   TS6 */ \
 190{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO9   TrcClk */ \
 191{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10  PerCS1 */ \
 192{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11  PerCS2 */ \
 193{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12  PerCS3 */ \
 194{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13  PerCS4 */ \
 195{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14  PerAddr03 */ \
 196{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15  PerAddr04 */ \
 197{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16  PerAddr05 */ \
 198{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17  IRQ0 */ \
 199{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18  IRQ1 */ \
 200{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19  IRQ2 */ \
 201{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO20  IRQ3 */ \
 202{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO21  IRQ4 */ \
 203{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO22  IRQ5 */ \
 204{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO23  IRQ6 */ \
 205{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24  UART0_DCD */ \
 206{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25  UART0_DSR */ \
 207{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26  UART0_RI */ \
 208{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27  UART0_DTR */ \
 209{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28  UART1_Rx */ \
 210{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29  UART1_Tx */ \
 211{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO30  RejectPkt0 */ \
 212{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO31  RejectPkt1 */ \
 213} \
 214}
 215
 216/*
 217 * Definitions for initial stack pointer and data area (in data cache)
 218 */
 219/* use on chip memory (OCM) for temperary stack until sdram is tested */
 220#define CONFIG_SYS_TEMP_STACK_OCM        1
 221
 222/* On Chip Memory location */
 223#define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 224#define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 225#define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
 226#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
 227
 228#define CONFIG_SYS_GBL_DATA_SIZE        128  /* size/bytes res'd for init data*/
 229#define CONFIG_SYS_GBL_DATA_OFFSET \
 230        (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 231#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 232
 233/*
 234 * External Bus Controller (EBC) Setup
 235 */
 236
 237/* Memory Bank 0 (NOR-FLASH) initialization */
 238#define CONFIG_SYS_EBC_PB0AP            0xa382a880
 239#define CONFIG_SYS_EBC_PB0CR            0xFC0DA000
 240
 241/* Memory Bank 1 (NVRAM) initializatio */
 242#define CONFIG_SYS_EBC_PB1AP            0x92015480
 243#define CONFIG_SYS_EBC_PB1CR            0xFB858000
 244
 245/* Memory Bank 2 (FPGA0) initialization */
 246#define CONFIG_SYS_FPGA0_BASE           0x7f100000
 247#define CONFIG_SYS_EBC_PB2AP            0x02825080
 248#define CONFIG_SYS_EBC_PB2CR            (CONFIG_SYS_FPGA0_BASE | 0x1a000)
 249
 250#define CONFIG_SYS_FPGA_BASE(k)         CONFIG_SYS_FPGA0_BASE
 251#define CONFIG_SYS_FPGA_DONE(k)         0x0010
 252
 253#define CONFIG_SYS_FPGA_COUNT           1
 254
 255/* Memory Bank 3 (Latches) initialization */
 256#define CONFIG_SYS_LATCH_BASE           0x7f200000
 257#define CONFIG_SYS_EBC_PB3AP            0x02025080
 258#define CONFIG_SYS_EBC_PB3CR            0x7f21a000
 259
 260#define CONFIG_SYS_LATCH0_RESET         0xffef
 261#define CONFIG_SYS_LATCH0_BOOT          0xffff
 262#define CONFIG_SYS_LATCH1_RESET         0xffff
 263#define CONFIG_SYS_LATCH1_BOOT          0xffff
 264
 265/*
 266 * OSD Setup
 267 */
 268#define CONFIG_SYS_MPC92469AC
 269#define CONFIG_SYS_CH7301
 270#define CONFIG_SYS_OSD_SCREENS          CONFIG_SYS_FPGA_COUNT
 271
 272#endif  /* __CONFIG_H */
 273