1/* 2 * Copyright (C) 2006 Atmel Corporation 3 * 4 * Configuration settings for the AVR32 Network Gateway 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24#ifndef __CONFIG_H 25#define __CONFIG_H 26 27#include <asm/arch/hardware.h> 28 29#define CONFIG_AVR32 30#define CONFIG_AT32AP 31#define CONFIG_AT32AP7000 32#define CONFIG_MIMC200 33 34#define CONFIG_MIMC200_EXT_FLASH 35 36#define CONFIG_SYS_HZ 1000 37 38/* 39 * Set up the PLL to run at 140 MHz, the CPU to run at the PLL 40 * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency 41 * and the PBA bus to run at 1/4 the PLL frequency. 42 */ 43#define CONFIG_PLL 44#define CONFIG_SYS_POWER_MANAGER 45#define CONFIG_SYS_OSC0_HZ 10000000 46#define CONFIG_SYS_PLL0_DIV 1 47#define CONFIG_SYS_PLL0_MUL 15 48#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16 49#define CONFIG_SYS_CLKDIV_CPU 0 50#define CONFIG_SYS_CLKDIV_HSB 1 51#define CONFIG_SYS_CLKDIV_PBA 2 52#define CONFIG_SYS_CLKDIV_PBB 1 53 54/* Reserve VM regions for SDRAM, NOR flash and FRAM */ 55#define CONFIG_SYS_NR_VM_REGIONS 3 56 57/* 58 * The PLLOPT register controls the PLL like this: 59 * icp = PLLOPT<2> 60 * ivco = PLLOPT<1:0> 61 * 62 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). 63 */ 64#define CONFIG_SYS_PLL0_OPT 0x04 65 66#define CONFIG_USART_BASE ATMEL_BASE_USART1 67#define CONFIG_USART_ID 1 68 69#define CONFIG_MIMC200_DBGLINK 1 70 71/* User serviceable stuff */ 72#define CONFIG_DOS_PARTITION 73 74#define CONFIG_CMDLINE_TAG 75#define CONFIG_SETUP_MEMORY_TAGS 76#define CONFIG_INITRD_TAG 77 78#define CONFIG_STACKSIZE (2048) 79 80#define CONFIG_BAUDRATE 115200 81#define CONFIG_BOOTARGS \ 82 "root=/dev/mtdblock1 rootfstype=jffs2 fbmem=512k console=ttyS1" 83#define CONFIG_BOOTCOMMAND \ 84 "fsload boot/uImage; bootm" 85 86#define CONFIG_SILENT_CONSOLE /* enable silent startup */ 87#define CONFIG_DISABLE_CONSOLE /* disable console */ 88#define CONFIG_SYS_DEVICE_NULLDEV /* include nulldev device */ 89 90#define CONFIG_LCD 1 91 92/* 93 * Only interrupt autoboot if <space> is pressed. Otherwise, garbage 94 * data on the serial line may interrupt the boot sequence. 95 */ 96#define CONFIG_BOOTDELAY 0 97#define CONFIG_ZERO_BOOTDELAY_CHECK 98#define CONFIG_AUTOBOOT 99 100/* 101 * After booting the board for the first time, new ethernet addresses 102 * should be generated and assigned to the environment variables 103 * "ethaddr" and "eth1addr". This is normally done during production. 104 */ 105#define CONFIG_OVERWRITE_ETHADDR_ONCE 106 107/* 108 * BOOTP/DHCP options 109 */ 110#define CONFIG_BOOTP_SUBNETMASK 111#define CONFIG_BOOTP_GATEWAY 112 113/* 114 * Command line configuration. 115 */ 116#include <config_cmd_default.h> 117 118#define CONFIG_CMD_ASKENV 119#define CONFIG_CMD_DHCP 120#define CONFIG_CMD_EXT2 121#define CONFIG_CMD_FAT 122#define CONFIG_CMD_JFFS2 123#define CONFIG_CMD_MMC 124#define CONFIG_CMD_NET 125 126#define CONFIG_ATMEL_USART 127#define CONFIG_MACB 128#define CONFIG_PORTMUX_PIO 129#define CONFIG_SYS_NR_PIOS 5 130#define CONFIG_SYS_HSDRAMC 131#define CONFIG_MMC 132#define CONFIG_GENERIC_ATMEL_MCI 133#define CONFIG_GENERIC_MMC 134 135#if defined(CONFIG_LCD) 136#define CONFIG_CMD_BMP 137#define CONFIG_ATMEL_LCD 1 138#define LCD_BPP LCD_COLOR16 139#define CONFIG_BMP_16BPP 1 140#define CONFIG_FB_ADDR 0x10600000 141#define CONFIG_WHITE_ON_BLACK 1 142#define CONFIG_VIDEO_BMP_GZIP 1 143#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE 262144 144#define CONFIG_ATMEL_LCD_BGR555 1 145#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 146#define CONFIG_SPLASH_SCREEN 1 147#endif 148 149#define CONFIG_SYS_DCACHE_LINESZ 32 150#define CONFIG_SYS_ICACHE_LINESZ 32 151 152#define CONFIG_NR_DRAM_BANKS 1 153 154#define CONFIG_SYS_FLASH_CFI 155#define CONFIG_FLASH_CFI_DRIVER 156 157#define CONFIG_SYS_FLASH_BASE 0x00000000 158#define CONFIG_SYS_FLASH_SIZE 0x800000 159#define CONFIG_SYS_MAX_FLASH_BANKS 1 160#define CONFIG_SYS_MAX_FLASH_SECT 135 161 162#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 163#define CONFIG_SYS_TEXT_BASE 0x00000000 164 165#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE 166#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE 167#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE 168 169#define CONFIG_SYS_FRAM_BASE 0x08000000 170#define CONFIG_SYS_FRAM_SIZE 0x20000 171 172#define CONFIG_ENV_IS_IN_FLASH 173#define CONFIG_ENV_SIZE 65536 174#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE) 175 176#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE) 177 178#define CONFIG_SYS_MALLOC_LEN (1024*1024) 179#define CONFIG_SYS_DMA_ALLOC_LEN (16384) 180 181/* Allow 4MB for the kernel run-time image */ 182#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) 183#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024) 184 185/* Other configuration settings that shouldn't have to change all that often */ 186#define CONFIG_SYS_PROMPT "U-Boot> " 187#define CONFIG_SYS_CBSIZE 256 188#define CONFIG_SYS_MAXARGS 16 189#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 190#define CONFIG_SYS_LONGHELP 191 192#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE 193#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1f00000) 194 195#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } 196 197#endif /* __CONFIG_H */ 198