1/* 2 * (C) Copyright 2002 3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 4 * Marius Groeger <mgroeger@sysgo.de> 5 * Gary Jennejohn <gj@denx.de> 6 * David Mueller <d.mueller@elsoft.ch> 7 * 8 * (C) Copyright 2009-2010 9 * Michel Pollet <buserror@gmail.com> 10 * 11 * (C) Copyright 2012 12 * Gabriel Huau <contact@huau-gabriel.fr> 13 * 14 * Configuation settings for the MINI2440 board. 15 * 16 * See file CREDITS for list of people who contributed to this 17 * project. 18 * 19 * This program is free software; you can redistribute it and/or 20 * modify it under the terms of the GNU General Public License as 21 * published by the Free Software Foundation; either version 2 of 22 * the License, or (at your option) any later version. 23 * 24 * This program is distributed in the hope that it will be useful, 25 * but WITHOUT ANY WARRANTY; without even the implied warranty of 26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 27 * GNU General Public License for more details. 28 * 29 * You should have received a copy of the GNU General Public License 30 * along with this program; if not, write to the Free Software 31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 32 * MA 02111-1307 USA 33 */ 34 35#ifndef __CONFIG_H 36#define __CONFIG_H 37 38#define CONFIG_SYS_TEXT_BASE 0x0 39#define CONFIG_S3C2440_GPIO 40 41/* 42 * High Level Configuration Options 43 */ 44#define CONFIG_ARM920T /* This is an ARM920T Core */ 45#define CONFIG_S3C24X0 /* in a SAMSUNG S3C24X0 SoC */ 46#define CONFIG_S3C2440 /* in a SAMSUNG S3C2440 SoC */ 47#define CONFIG_MINI2440 /* on a MIN2440 Board */ 48 49#define MACH_TYPE_MINI2440 1999 50#define CONFIG_MACH_TYPE MACH_TYPE_MINI2440 51 52/* 53 * We don't use lowlevel_init 54 */ 55#define CONFIG_SKIP_LOWLEVEL_INIT 56#define CONFIG_BOARD_EARLY_INIT_F 57 58/* 59 * input clock of PLL 60 */ 61/* MINI2440 has 12.0000MHz input clock */ 62#define CONFIG_SYS_CLK_FREQ 12000000 63 64/* 65 * Size of malloc() pool 66 */ 67#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048*1024) 68 69/* 70 * Hardware drivers 71 */ 72#define CONFIG_DRIVER_DM9000 73#define CONFIG_DRIVER_DM9000_NO_EEPROM 74#define CONFIG_DM9000_BASE 0x20000300 75#define DM9000_IO CONFIG_DM9000_BASE 76#define DM9000_DATA (CONFIG_DM9000_BASE+4) 77 78/* 79 * select serial console configuration 80 */ 81#define CONFIG_S3C24X0_SERIAL 82#define CONFIG_SERIAL1 83 84/* 85 * allow to overwrite serial and ethaddr 86 */ 87#define CONFIG_ENV_OVERWRITE 88 89/* 90 * Command definition 91 */ 92#include <config_cmd_default.h> 93 94#define CONFIG_CMD_DHCP 95#define CONFIG_CMD_PORTIO 96#define CONFIG_CMD_REGINFO 97#define CONFIG_CMD_SAVES 98 99/* 100 * Miscellaneous configurable options 101 */ 102#define CONFIG_LONGHELP 103#define CONFIG_SYS_PROMPT "MINI2440 => " 104#define CONFIG_SYS_CBSIZE 256 105#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 106#define CONFIG_SYS_MAXARGS 32 107#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 108 109#define CONFIG_SYS_MEMTEST_START 0x30000000 110#define CONFIG_SYS_MEMTEST_END 0x34000000 /* 64MB in DRAM */ 111 112/* default load address */ 113#define CONFIG_SYS_LOAD_ADDR 0x32000000 114 115/* boot parameters address */ 116#define CONFIG_BOOT_PARAM_ADDR 0x30000100 117 118/* 119 * the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need 120 * it to wrap 100 times (total 1562500) to get 1 sec. 121 */ 122#define CONFIG_SYS_HZ 1562500 123 124/* 125 * valid baudrates 126 */ 127#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 128#define CONFIG_BAUDRATE 115200 129 130/* 131 * Stack sizes 132 * The stack sizes are set up in start.S using the settings below 133 */ 134#define CONFIG_STACKSIZE (128*1024) /* regular stack */ 135#ifdef CONFIG_USE_IRQ 136#define CONFIG_STACKSIZE_IRQ (8*1024) /* IRQ stack */ 137#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ 138#endif 139 140/* 141 * Physical Memory Map 142 */ 143#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ 144#define PHYS_SDRAM_SIZE (64*1024*1024) /* 64MB of DRAM */ 145#define CONFIG_SYS_SDRAM_BASE 0x30000000 146#define CONFIG_SYS_FLASH_BASE 0x0 147 148/* 149 * Stack should be on the SRAM because 150 * DRAM is not init 151 */ 152#define CONFIG_SYS_INIT_SP_ADDR (0x40001000 - GENERATED_GBL_DATA_SIZE) 153 154/* 155 * NOR FLASH organization 156 * Now uses the standard CFI interface 157 * FLASH and environment organization 158 */ 159#define CONFIG_SYS_FLASH_CFI 160#define CONFIG_FLASH_CFI_DRIVER 161#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 162#define CONFIG_SYS_MONITOR_BASE 0x0 163/* max number of memory banks */ 164#define CONFIG_SYS_MAX_FLASH_BANKS 1 165/* 512 * 4096 sectors, or 32 * 64k blocks */ 166#define CONFIG_SYS_MAX_FLASH_SECT 512 167#define CONFIG_FLASH_SHOW_PROGRESS 1 168 169/* 170 * Config for NOR flash 171 */ 172#define CONFIG_ENV_IS_IN_FLASH 173#define CONFIG_MY_ENV_OFFSET 0x40000 174/* addr of environment */ 175#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_MY_ENV_OFFSET) 176/* 16k Total Size of Environment Sector */ 177#define CONFIG_ENV_SIZE 0x4000 178 179/* ATAG configuration */ 180#define CONFIG_INITRD_TAG 181#define CONFIG_SETUP_MEMORY_TAGS 182#define CONFIG_CMDLINE_TAG 183#define CONFIG_CMDLINE_EDITING 184#define CONFIG_AUTO_COMPLETE 185 186#endif /* __CONFIG_H */ 187