1/* 2 * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com> 3 * 4 * (C) Copyright 2004 5 * Texas Instruments. 6 * Richard Woodruff <r-woodruff2@ti.com> 7 * Kshitij Gupta <kshitij@ti.com> 8 * 9 * Configuration settings for the Freescale i.MX31 PDK board. 10 * 11 * See file CREDITS for list of people who contributed to this 12 * project. 13 * 14 * This program is free software; you can redistribute it and/or 15 * modify it under the terms of the GNU General Public License as 16 * published by the Free Software Foundation; either version 2 of 17 * the License, or (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License 25 * along with this program; if not, write to the Free Software 26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 27 * MA 02111-1307 USA 28 */ 29 30#ifndef __CONFIG_H 31#define __CONFIG_H 32 33#include <asm/arch/imx-regs.h> 34 35/* High Level Configuration Options */ 36#define CONFIG_ARM1136 /* This is an arm1136 CPU core */ 37#define CONFIG_MX31 /* in a mx31 */ 38 39#define CONFIG_DISPLAY_CPUINFO 40#define CONFIG_DISPLAY_BOARDINFO 41 42#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 43#define CONFIG_SETUP_MEMORY_TAGS 44#define CONFIG_INITRD_TAG 45 46#define CONFIG_MACH_TYPE MACH_TYPE_MX31_3DS 47 48#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) 49#define CONFIG_SKIP_LOWLEVEL_INIT 50#endif 51 52/* 53 * Size of malloc() pool 54 */ 55#define CONFIG_SYS_MALLOC_LEN (2*CONFIG_ENV_SIZE + 2 * 128 * 1024) 56 57/* 58 * Hardware drivers 59 */ 60 61#define CONFIG_MXC_UART 62#define CONFIG_MXC_UART_BASE UART1_BASE 63#define CONFIG_HW_WATCHDOG 64#define CONFIG_IMX_WATCHDOG 65#define CONFIG_MXC_GPIO 66 67#define CONFIG_HARD_SPI 68#define CONFIG_MXC_SPI 69#define CONFIG_DEFAULT_SPI_BUS 1 70#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) 71 72/* PMIC Controller */ 73#define CONFIG_POWER 74#define CONFIG_POWER_SPI 75#define CONFIG_POWER_FSL 76#define CONFIG_FSL_PMIC_BUS 1 77#define CONFIG_FSL_PMIC_CS 2 78#define CONFIG_FSL_PMIC_CLK 1000000 79#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) 80#define CONFIG_FSL_PMIC_BITLEN 32 81#define CONFIG_RTC_MC13XXX 82 83/* allow to overwrite serial and ethaddr */ 84#define CONFIG_ENV_OVERWRITE 85#define CONFIG_CONS_INDEX 1 86#define CONFIG_BAUDRATE 115200 87 88/*********************************************************** 89 * Command definition 90 ***********************************************************/ 91 92#include <config_cmd_default.h> 93 94#define CONFIG_CMD_MII 95#define CONFIG_CMD_PING 96#define CONFIG_CMD_DHCP 97#define CONFIG_CMD_SPI 98#define CONFIG_CMD_DATE 99#define CONFIG_CMD_NAND 100#define CONFIG_CMD_BOOTZ 101 102/* 103 * Disabled due to compilation errors in cmd_bootm.c (IMLS seems to require 104 * that CFG_NO_FLASH is undefined). 105 */ 106#undef CONFIG_CMD_IMLS 107 108#define CONFIG_BOARD_LATE_INIT 109 110#define CONFIG_BOOTDELAY 1 111 112#define CONFIG_EXTRA_ENV_SETTINGS \ 113 "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \ 114 "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \ 115 "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \ 116 "bootcmd=run bootcmd_net\0" \ 117 "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \ 118 "tftpboot 0x81000000 uImage-mx31; bootm\0" \ 119 "prg_uboot=tftpboot 0x81000000 u-boot-nand.bin; " \ 120 "nand erase 0x0 0x40000; " \ 121 "nand write 0x81000000 0x0 0x40000\0" 122 123#define CONFIG_SMC911X 124#define CONFIG_SMC911X_BASE 0xB6000000 125#define CONFIG_SMC911X_32_BIT 126 127/* 128 * Miscellaneous configurable options 129 */ 130#define CONFIG_SYS_LONGHELP /* undef to save memory */ 131#define CONFIG_SYS_PROMPT "MX31PDK U-Boot > " 132#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 133/* Print Buffer Size */ 134#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 135 sizeof(CONFIG_SYS_PROMPT)+16) 136/* max number of command args */ 137#define CONFIG_SYS_MAXARGS 16 138/* Boot Argument Buffer Size */ 139#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 140 141/* memtest works on */ 142#define CONFIG_SYS_MEMTEST_START 0x80000000 143#define CONFIG_SYS_MEMTEST_END 0x80010000 144 145/* default load address */ 146#define CONFIG_SYS_LOAD_ADDR 0x81000000 147 148#define CONFIG_SYS_HZ 1000 149 150#define CONFIG_CMDLINE_EDITING 151 152/*----------------------------------------------------------------------- 153 * Physical Memory Map 154 */ 155#define CONFIG_NR_DRAM_BANKS 1 156#define PHYS_SDRAM_1 CSD0_BASE 157#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) 158#define CONFIG_BOARD_EARLY_INIT_F 159 160#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 161#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 162#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 163#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 164 GENERATED_GBL_DATA_SIZE) 165#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 166 CONFIG_SYS_GBL_DATA_OFFSET) 167 168/*----------------------------------------------------------------------- 169 * FLASH and environment organization 170 */ 171/* No NOR flash present */ 172#define CONFIG_SYS_NO_FLASH 173 174#define CONFIG_ENV_IS_IN_NAND 175#define CONFIG_ENV_OFFSET 0x40000 176#define CONFIG_ENV_OFFSET_REDUND 0x60000 177#define CONFIG_ENV_SIZE (128 * 1024) 178 179/* 180 * NAND driver 181 */ 182#define CONFIG_NAND_MXC 183#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR 184#define CONFIG_SYS_MAX_NAND_DEVICE 1 185#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR 186#define CONFIG_MXC_NAND_HWECC 187#define CONFIG_SYS_NAND_LARGEPAGE 188 189/* NAND configuration for the NAND_SPL */ 190 191/* Start copying real U-boot from the second page */ 192#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800 193#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x30000 194/* Load U-Boot to this address */ 195#define CONFIG_SYS_NAND_U_BOOT_DST 0x87f00000 196#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 197 198#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 199#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 200#define CONFIG_SYS_NAND_PAGE_COUNT 64 201#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) 202#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 203 204 205/* Configuration of lowlevel_init.S (clocks and SDRAM) */ 206#define CCM_CCMR_SETUP 0x074B0BF5 207#define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \ 208 PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | \ 209 PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | \ 210 PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0)) 211#define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \ 212 PLL_MFN(12)) 213 214#define ESDMISC_MDDR_SETUP 0x00000004 215#define ESDMISC_MDDR_RESET_DL 0x0000000c 216#define ESDCFG0_MDDR_SETUP 0x006ac73a 217 218#define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2)) 219#define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \ 220 ESDCTL_DSIZ(2) | ESDCTL_BL(1)) 221#define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE) 222#define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH) 223#define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG) 224#define ESDCTL_RW ESDCTL_SETTINGS 225 226#endif /* __CONFIG_H */ 227