1/* 2 * (C) Copyright 2004 3 * Texas Instruments. 4 * Richard Woodruff <r-woodruff2@ti.com> 5 * Kshitij Gupta <kshitij@ti.com> 6 * 7 * Configuration settings for the 242x TI H4 board. 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28#ifndef __CONFIG_H 29#define __CONFIG_H 30 31/* 32 * High Level Configuration Options 33 */ 34#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ 35#define CONFIG_OMAP 1 /* in a TI OMAP core */ 36#define CONFIG_OMAP2420 1 /* which is in a 2420 */ 37#define CONFIG_OMAP2420H4 1 /* and on a H4 board */ 38/*#define CONFIG_APTIX 1 #* define if on APTIX test chip */ 39/*#define CONFIG_VIRTIO 1 #* Using Virtio simulator */ 40 41#define CONFIG_STANDALONE_LOAD_ADDR 0x80300000 42 43/* Clock config to target*/ 44#define PRCM_CONFIG_II 1 45/* #define PRCM_CONFIG_III 1 */ 46 47#include <asm/arch/omap2420.h> /* get chip and board defs */ 48 49/* On H4, NOR and NAND flash are mutual exclusive. 50 Define this if you want to use NAND 51 */ 52/*#define CONFIG_SYS_NAND_BOOT */ 53 54#ifdef CONFIG_APTIX 55#define V_SCLK 1500000 56#else 57#define V_SCLK 12000000 58#endif 59 60/* input clock of PLL */ 61/* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */ 62#define CONFIG_SYS_CLK_FREQ V_SCLK 63 64#define CONFIG_MISC_INIT_R 65 66#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 67#define CONFIG_SETUP_MEMORY_TAGS 1 68#define CONFIG_INITRD_TAG 1 69#define CONFIG_REVISION_TAG 1 70 71/* 72 * Size of malloc() pool 73 */ 74#define CONFIG_ENV_SIZE SZ_128K /* Total Size of Environment Sector */ 75#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K) 76 77/* 78 * Hardware drivers 79 */ 80 81/* 82 * SMC91c96 Etherent 83 */ 84#define CONFIG_LAN91C96 85#define CONFIG_LAN91C96_BASE (H4_CS1_BASE+0x300) 86#define CONFIG_LAN91C96_EXT_PHY 87 88/* 89 * NS16550 Configuration 90 */ 91#ifdef CONFIG_APTIX 92#define V_NS16550_CLK (6000000) /* 6MHz in current MaxSet */ 93#else 94#define V_NS16550_CLK (48000000) /* 48MHz (APLL96/2) */ 95#endif 96 97#define CONFIG_SYS_NS16550 98#define CONFIG_SYS_NS16550_SERIAL 99#define CONFIG_SYS_NS16550_REG_SIZE (-4) 100#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK /* 3MHz (1.5MHz*2) */ 101#define CONFIG_SYS_NS16550_COM1 OMAP2420_UART1 102 103/* 104 * select serial console configuration 105 */ 106#define CONFIG_SERIAL1 1 /* UART1 on H4 */ 107 108 /* 109 * I2C configuration 110 */ 111#define CONFIG_HARD_I2C 112#define CONFIG_SYS_I2C_SPEED 100000 113#define CONFIG_SYS_I2C_SLAVE 1 114#define CONFIG_DRIVER_OMAP24XX_I2C 115 116/* allow to overwrite serial and ethaddr */ 117#define CONFIG_ENV_OVERWRITE 118#define CONFIG_CONS_INDEX 1 119#define CONFIG_BAUDRATE 115200 120 121/* 122 * Command line configuration. 123 */ 124#include <config_cmd_default.h> 125 126#ifdef CONFIG_SYS_NAND_BOOT 127 #define CONFIG_CMD_DHCP 128 #define CONFIG_CMD_I2C 129 #define CONFIG_CMD_NAND 130 #define CONFIG_CMD_JFFS2 131#else 132 #define CONFIG_CMD_DHCP 133 #define CONFIG_CMD_I2C 134 #define CONFIG_CMD_JFFS2 135 136 #undef CONFIG_CMD_SOURCE 137#endif 138 139 140/* 141 * BOOTP options 142 */ 143#define CONFIG_BOOTP_SUBNETMASK 144#define CONFIG_BOOTP_GATEWAY 145#define CONFIG_BOOTP_HOSTNAME 146#define CONFIG_BOOTP_BOOTPATH 147 148#define CONFIG_BOOTDELAY 3 149 150#ifdef NFS_BOOT_DEFAULTS 151#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw nfsroot=128.247.77.158:/home/a0384864/wtbu/rootfs ip=dhcp" 152#else 153#define CONFIG_BOOTARGS "root=/dev/ram0 rw mem=32M console=ttyS0,115200n8 initrd=0x80600000,8M ramdisk_size=8192" 154#endif 155 156#define CONFIG_NETMASK 255.255.254.0 157#define CONFIG_IPADDR 128.247.77.90 158#define CONFIG_SERVERIP 128.247.77.158 159#define CONFIG_BOOTFILE "uImage" 160 161/* 162 * Miscellaneous configurable options 163 */ 164#define CONFIG_SYS_LONGHELP /* undef to save memory */ 165#ifdef CONFIG_APTIX 166# define CONFIG_SYS_PROMPT "OMAP2420 Aptix # " 167#else 168# define CONFIG_SYS_PROMPT "OMAP242x H4 # " 169#endif 170#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 171/* Print Buffer Size */ 172#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 173#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 174#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 175 176#define CONFIG_SYS_MEMTEST_START (OMAP2420_SDRC_CS0) /* memtest works on */ 177#define CONFIG_SYS_MEMTEST_END (OMAP2420_SDRC_CS0+SZ_31M) 178 179#define CONFIG_SYS_LOAD_ADDR (OMAP2420_SDRC_CS0) /* default load address */ 180 181/* The 2420 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by 182 * 32KHz clk, or from external sig. This rate is divided by a local divisor. 183 */ 184#ifdef CONFIG_APTIX 185#define V_PTV 3 186#else 187#define V_PTV 7 /* use with 12MHz/128 */ 188#endif 189 190#define CONFIG_SYS_TIMERBASE OMAP2420_GPT2 191#define CONFIG_SYS_PTV V_PTV /* 2^(PTV+1) */ 192#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV)) 193 194/*----------------------------------------------------------------------- 195 * Physical Memory Map 196 */ 197#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 198#define PHYS_SDRAM_1 OMAP2420_SDRC_CS0 199#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ 200#define PHYS_SDRAM_2 OMAP2420_SDRC_CS1 201 202#define PHYS_FLASH_SECT_SIZE SZ_128K 203#define PHYS_FLASH_1 H4_CS0_BASE /* Flash Bank #1 */ 204#define PHYS_FLASH_SIZE_1 SZ_32M 205#define PHYS_FLASH_2 (H4_CS0_BASE+SZ_32M) /* same cs, 2 chips in series */ 206#define PHYS_FLASH_SIZE_2 SZ_32M 207 208#define PHYS_SRAM 0x4020F800 209/*----------------------------------------------------------------------- 210 * FLASH and environment organization 211 */ 212#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 213#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 214#define CONFIG_SYS_MAX_FLASH_SECT (259) /* max number of sectors on one chip */ 215#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */ 216#define CONFIG_SYS_MONITOR_LEN SZ_128K /* Reserve 1 sector */ 217#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SIZE_1 } 218 219#ifdef CONFIG_SYS_NAND_BOOT 220#define CONFIG_ENV_IS_IN_NAND 1 221#define CONFIG_ENV_OFFSET 0x80000 /* environment starts here */ 222#else 223#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + SZ_128K) 224#define CONFIG_ENV_IS_IN_FLASH 1 225#define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE 226#define CONFIG_ENV_OFFSET ( CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN ) /* Environment after Monitor */ 227#endif 228 229/*----------------------------------------------------------------------- 230 * CFI FLASH driver setup 231 */ 232#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */ 233#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */ 234#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ 235#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */ 236 237/* timeout values are in ticks */ 238#define CONFIG_SYS_FLASH_ERASE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ 239#define CONFIG_SYS_FLASH_WRITE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Write */ 240 241#define CONFIG_SYS_JFFS2_MEM_NAND 242 243/* 244 * JFFS2 partitions 245 */ 246/* No command line, one static partition, whole device */ 247#undef CONFIG_CMD_MTDPARTS 248#define CONFIG_JFFS2_DEV "nor1" 249#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF 250#define CONFIG_JFFS2_PART_OFFSET 0x00000000 251 252/* mtdparts command line support */ 253/* Note: fake mtd_id used, no linux mtd map file */ 254/* 255#define CONFIG_CMD_MTDPARTS 256#define MTDIDS_DEFAULT "nor1=omap2420-1" 257#define MTDPARTS_DEFAULT "mtdparts=omap2420-1:-(jffs2)" 258*/ 259 260#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 261#define CONFIG_SYS_INIT_SP_ADDR PHYS_SRAM 262 263#endif /* __CONFIG_H */ 264