1/* 2 * Copyright (C) 2003 ETC s.r.o. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation; either version 2 of 7 * the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 * MA 02111-1307 USA 18 * 19 * Written by Peter Figuli <peposh@etc.sk>, 2003. 20 * 21 * 2003/13/06 Initial MP10 Support copied from wepep250 22 */ 23 24#ifndef __CONFIG_H 25#define __CONFIG_H 26 27#define CONFIG_ARM920T 1 /* this is an ARM920T CPU */ 28#define CONFIG_IMX 1 /* in a Motorola MC9328MXL Chip */ 29#define CONFIG_SCB9328 1 /* on a scb9328tronix board */ 30 31#define CONFIG_IMX_SERIAL 32#define CONFIG_IMX_SERIAL1 33/* 34 * Select serial console configuration 35 */ 36 37/* 38 * BOOTP options 39 */ 40#define CONFIG_BOOTP_BOOTFILESIZE 41#define CONFIG_BOOTP_BOOTPATH 42#define CONFIG_BOOTP_GATEWAY 43#define CONFIG_BOOTP_HOSTNAME 44 45/* 46 * Command line configuration. 47 */ 48#include <config_cmd_default.h> 49 50#define CONFIG_CMD_NET 51#define CONFIG_CMD_PING 52#define CONFIG_CMD_DHCP 53 54#undef CONFIG_CMD_CONSOLE 55#undef CONFIG_CMD_LOADS 56#undef CONFIG_CMD_SOURCE 57 58/* 59 * Boot options. Setting delay to -1 stops autostart count down. 60 * NOTE: Sending parameters to kernel depends on kernel version and 61 * 2.4.19-rmk6-pxa1 patch used while my u-boot coding didn't accept 62 * parameters at all! Do not get confused by them so. 63 */ 64#define CONFIG_BOOTDELAY -1 65#define CONFIG_BOOTARGS "console=ttySMX0,115200n8 root=/dev/mtdblock3 rootfstype=jffs2 mtdparts=scb9328_flash:128k(U-boot)ro,128k(U-boot_env),1m(kernel),4m(root),4m(fs) eval_board=evk9328" 66#define CONFIG_BOOTCOMMAND "bootm 10040000" 67#define CONFIG_SHOW_BOOT_PROGRESS 68#define CONFIG_ETHADDR 80:81:82:83:84:85 69#define CONFIG_NETMASK 255.255.255.0 70#define CONFIG_IPADDR 10.10.10.9 71#define CONFIG_SERVERIP 10.10.10.10 72 73/* 74 * General options for u-boot. Modify to save memory foot print 75 */ 76#define CONFIG_SYS_LONGHELP /* undef saves memory */ 77#define CONFIG_SYS_PROMPT "scb9328> " /* prompt string */ 78#define CONFIG_SYS_CBSIZE 256 /* console I/O buffer */ 79#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* print buffer size */ 80#define CONFIG_SYS_MAXARGS 16 /* max command args */ 81#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot args buf size */ 82 83#define CONFIG_SYS_MEMTEST_START 0x08100000 /* memtest test area */ 84#define CONFIG_SYS_MEMTEST_END 0x08F00000 85 86#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */ 87#define CONFIG_SYS_CPUSPEED 0x141 /* core clock - register value */ 88 89#define CONFIG_BAUDRATE 115200 90/* 91 * Definitions related to passing arguments to kernel. 92 */ 93#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */ 94#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */ 95#define CONFIG_INITRD_TAG 1 /* send initrd params */ 96 97/* 98 * Malloc pool need to host env + 128 Kb reserve for other allocations. 99 */ 100#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128<<10) ) 101 102/* SDRAM Setup Values 1030x910a8300 Precharge Command CAS 3 1040x910a8200 Precharge Command CAS 2 105 1060xa10a8300 AutoRefresh Command CAS 3 1070xa10a8200 Set AutoRefresh Command CAS 2 */ 108 109#define PRECHARGE_CMD 0x910a8200 110#define AUTOREFRESH_CMD 0xa10a8200 111 112/* 113 * SDRAM Memory Map 114 */ 115/* SH FIXME */ 116#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */ 117#define SCB9328_SDRAM_1 0x08000000 /* SDRAM bank #1 */ 118#define SCB9328_SDRAM_1_SIZE 0x01000000 /* 16 MB */ 119 120#define CONFIG_SYS_TEXT_BASE 0x10000000 121 122#define CONFIG_SYS_SDRAM_BASE SCB9328_SDRAM_1 123#define CONFIG_SYS_INIT_SP_ADDR (SCB9328_SDRAM_1 + 0xf00000) 124 125/* 126 * Configuration for FLASH memory for the Synertronixx board 127 */ 128 129/* #define SCB9328_FLASH_32M */ 130 131/* 32MB */ 132#ifdef SCB9328_FLASH_32M 133#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/ 134#define CONFIG_SYS_MAX_FLASH_SECT 256 /* number of sector in FLASH bank */ 135#define SCB9328_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */ 136#define SCB9328_FLASH_INTERLEAVE 1 /* ... made of 1 chip */ 137#define SCB9328_FLASH_BANK_SIZE 0x02000000 /* size of one flash bank */ 138#define SCB9328_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */ 139#define SCB9328_FLASH_BASE 0x10000000 /* location of flash memory */ 140#define SCB9328_FLASH_UNLOCK 1 /* perform hw unlock first */ 141#else 142 143/* 16MB */ 144#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/ 145#define CONFIG_SYS_MAX_FLASH_SECT 128 /* number of sector in FLASH bank */ 146#define SCB9328_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */ 147#define SCB9328_FLASH_INTERLEAVE 1 /* ... made of 1 chip */ 148#define SCB9328_FLASH_BANK_SIZE 0x01000000 /* size of one flash bank */ 149#define SCB9328_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */ 150#define SCB9328_FLASH_BASE 0x10000000 /* location of flash memory */ 151#define SCB9328_FLASH_UNLOCK 1 /* perform hw unlock first */ 152#endif /* SCB9328_FLASH_32M */ 153 154/* This should be defined if CFI FLASH device is present. Actually benefit 155 is not so clear to me. In other words we can provide more informations 156 to user, but this expects more complex flash handling we do not provide 157 now.*/ 158#undef CONFIG_SYS_FLASH_CFI 159 160#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* timeout for Erase operation */ 161#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* timeout for Write operation */ 162 163#define CONFIG_SYS_FLASH_BASE SCB9328_FLASH_BASE 164 165/* 166 * This is setting for JFFS2 support in u-boot. 167 * Right now there is no gain for user, but later on booting kernel might be 168 * possible. Consider using XIP kernel running from flash to save RAM 169 * footprint. 170 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 171 */ 172#define CONFIG_SYS_JFFS2_FIRST_BANK 0 173#define CONFIG_SYS_JFFS2_FIRST_SECTOR 5 174#define CONFIG_SYS_JFFS2_NUM_BANKS 1 175 176/* 177 * Environment setup. Definitions of monitor location and size with 178 * definition of environment setup ends up in 2 possibilities. 179 * 1. Embeded environment - in u-boot code is space for environment 180 * 2. Environment is read from predefined sector of flash 181 * Right now we support 2. possiblity, but expecting no env placed 182 * on mentioned address right now. This also needs to provide whole 183 * sector for it - for us 256Kb is really waste of memory. U-boot uses 184 * default env. and until kernel parameters could be sent to kernel 185 * env. has no sense to us. 186 */ 187 188/* Setup for PA23 which is Reset Default PA23 but has to become 189 CS5 */ 190 191#define CONFIG_SYS_GPR_A_VAL 0x00800000 192#define CONFIG_SYS_GIUS_A_VAL 0x0043fffe 193 194#define CONFIG_SYS_MONITOR_BASE 0x10000000 195#define CONFIG_SYS_MONITOR_LEN 0x20000 /* 128b ( 1 flash sector ) */ 196#define CONFIG_ENV_IS_IN_FLASH 1 197#define CONFIG_ENV_ADDR 0x10020000 /* absolute address for now */ 198#define CONFIG_ENV_SIZE 0x20000 199 200#define CONFIG_ENV_OVERWRITE 1 /* env is not writable now */ 201 202/* 203 * CSxU_VAL: 204 * 63| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x|32 205 * |DTACK_SEL|0|BCD | BCS | PSZ|PME|SYNC| DOL | CNC| WSC | 0| WWS | EDC | 206 * 207 * CSxL_VAL: 208 * 31| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x| 0 209 * | OEA | OEN | WEA | WEN | CSA |EBC| DSZ | 0|SP|0|WP| 0 0|PA|CSEN| 210 */ 211 212#define CONFIG_SYS_CS0U_VAL 0x000F2000 213#define CONFIG_SYS_CS0L_VAL 0x11110d01 214#define CONFIG_SYS_CS1U_VAL 0x000F0a00 215#define CONFIG_SYS_CS1L_VAL 0x11110601 216#define CONFIG_SYS_CS2U_VAL 0x0 217#define CONFIG_SYS_CS2L_VAL 0x0 218 219#define CONFIG_SYS_CS3U_VAL 0x000FFFFF 220#define CONFIG_SYS_CS3L_VAL 0x00000303 221 222#define CONFIG_SYS_CS4U_VAL 0x000F0a00 223#define CONFIG_SYS_CS4L_VAL 0x11110301 224 225/* CNC == 3 too long 226 #define CONFIG_SYS_CS5U_VAL 0x0000C210 */ 227 228/* #define CONFIG_SYS_CS5U_VAL 0x00008400 229 mal laenger mahcen, ob der bei 150MHz laenger haelt dann und 230 kaum langsamer ist */ 231/* #define CONFIG_SYS_CS5U_VAL 0x00009400 232 #define CONFIG_SYS_CS5L_VAL 0x11010D03 */ 233 234#define CONFIG_SYS_CS5U_VAL 0x00008400 235#define CONFIG_SYS_CS5L_VAL 0x00000D03 236 237#define CONFIG_DRIVER_DM9000 1 238#define CONFIG_DM9000_BASE 0x16000000 239#define DM9000_IO CONFIG_DM9000_BASE 240#define DM9000_DATA (CONFIG_DM9000_BASE+4) 241 242/* f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1) 243 f_ref=16,777MHz 244 245 0x002a141f: 191,9944MHz 246 0x040b2007: 144MHz 247 0x042a141f: 96MHz 248 0x0811140d: 64MHz 249 0x040e200e: 150MHz 250 0x00321431: 200MHz 251 252 0x08001800: 64MHz mit 16er Quarz 253 0x04001800: 96MHz mit 16er Quarz 254 0x04002400: 144MHz mit 16er Quarz 255 256 31 |x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x| 0 257 |XXX|--PD---|-------MFD---------|XXX|--MFI--|-----MFN-----------| */ 258 259#define CPU200 260 261#ifdef CPU200 262#define CONFIG_SYS_MPCTL0_VAL 0x00321431 263#else 264#define CONFIG_SYS_MPCTL0_VAL 0x040e200e 265#endif 266 267/* #define BUS64 */ 268#define BUS72 269 270#ifdef BUS72 271#define CONFIG_SYS_SPCTL0_VAL 0x04002400 272#endif 273 274#ifdef BUS96 275#define CONFIG_SYS_SPCTL0_VAL 0x04001800 276#endif 277 278#ifdef BUS64 279#define CONFIG_SYS_SPCTL0_VAL 0x08001800 280#endif 281 282/* Das ist der BCLK Divider, der aus der System PLL 283 BCLK und HCLK erzeugt: 284 31 | xxxx xxxx xxxx xxxx xx10 11xx xxxx xxxx | 0 285 0x2f008403 : 192MHz/2=96MHz, 144MHz/2=72MHz PRESC=1->BCLKDIV=2 286 0x2f008803 : 192MHz/3=64MHz, 240MHz/3=80MHz PRESC=1->BCLKDIV=2 287 0x2f001003 : 192MHz/5=38,4MHz 288 0x2f000003 : 64MHz/1 289 Bit 22: SPLL Restart 290 Bit 21: MPLL Restart */ 291 292#ifdef BUS64 293#define CONFIG_SYS_CSCR_VAL 0x2f030003 294#endif 295 296#ifdef BUS72 297#define CONFIG_SYS_CSCR_VAL 0x2f030403 298#endif 299 300/* 301 * Well this has to be defined, but on the other hand it is used differently 302 * one may expect. For instance loadb command do not cares :-) 303 * So advice is - do not relay on this... 304 */ 305#define CONFIG_SYS_LOAD_ADDR 0x08400000 306 307#define MHZ16QUARZINUSE 308 309#ifdef MHZ16QUARZINUSE 310#define CONFIG_SYSPLL_CLK_FREQ 16000000 311#else 312#define CONFIG_SYSPLL_CLK_FREQ 16780000 313#endif 314 315#define CONFIG_SYS_CLK_FREQ 16780000 316 317/* FMCR Bit 0 becomes 0 to make CS3 CS3 :P */ 318#define CONFIG_SYS_FMCR_VAL 0x00000001 319 320/* Bit[0:3] contain PERCLK1DIV for UART 1 321 0x000b00b ->b<- -> 192MHz/12=16MHz 322 0x000b00b ->8<- -> 144MHz/09=16MHz 323 0x000b00b ->3<- -> 64MHz/4=16MHz */ 324 325#ifdef BUS96 326#define CONFIG_SYS_PCDR_VAL 0x000b00b5 327#endif 328 329#ifdef BUS64 330#define CONFIG_SYS_PCDR_VAL 0x000b00b3 331#endif 332 333#ifdef BUS72 334#define CONFIG_SYS_PCDR_VAL 0x000b00b8 335#endif 336 337#endif /* __CONFIG_H */ 338