LXR uboot/include/configs/trats.h

   1/*
   2 * Copyright (C) 2011 Samsung Electronics
   3 * Heungjun Kim <riverful.kim@samsung.com>
   4 *
   5 * Configuation settings for the SAMSUNG TRATS (EXYNOS4210) board.
   6 *
   7 * See file CREDITS for list of people who contributed to this
   8 * project.
   9 *
  10 * This program is free software; you can redistribute it and/or
  11 * modify it under the terms of the GNU General Public License as
  12 * published by the Free Software Foundation; either version 2 of
  13 * the License, or (at your option) any later version.
  14 *
  15 * This program is distributed in the hope that it will be useful,
  16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18 * GNU General Public License for more details.
  19 *
  20 * You should have received a copy of the GNU General Public License
  21 * along with this program; if not, write to the Free Software
  22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23 * MA 02111-1307 USA
  24 */
  25
  26#ifndef __CONFIG_H
  27#define __CONFIG_H
  28
  29/*
  30 * High Level Configuration Options
  31 * (easy to change)
  32 */
  33#define CONFIG_SAMSUNG          /* in a SAMSUNG core */
  34#define CONFIG_S5P              /* which is in a S5P Family */
  35#define CONFIG_EXYNOS4210       /* which is in a EXYNOS4210 */
  36#define CONFIG_TRATS            /* working with TRATS */
  37#define CONFIG_TIZEN            /* TIZEN lib */
  38
  39#include <asm/arch/cpu.h>       /* get chip and board defs */
  40
  41#define CONFIG_ARCH_CPU_INIT
  42#define CONFIG_DISPLAY_CPUINFO
  43#define CONFIG_DISPLAY_BOARDINFO
  44
  45#ifndef CONFIG_SYS_L2CACHE_OFF
  46#define CONFIG_SYS_L2_PL310
  47#define CONFIG_SYS_PL310_BASE   0x10502000
  48#endif
  49
  50#define CONFIG_SYS_SDRAM_BASE           0x40000000
  51#define CONFIG_SYS_TEXT_BASE            0x63300000
  52
  53/* input clock of PLL: TRATS has 24MHz input clock at EXYNOS4210 */
  54#define CONFIG_SYS_CLK_FREQ_C210        24000000
  55#define CONFIG_SYS_CLK_FREQ             CONFIG_SYS_CLK_FREQ_C210
  56
  57#define CONFIG_SETUP_MEMORY_TAGS
  58#define CONFIG_CMDLINE_TAG
  59#define CONFIG_REVISION_TAG
  60#define CONFIG_CMDLINE_EDITING
  61#define CONFIG_SKIP_LOWLEVEL_INIT
  62#define CONFIG_BOARD_EARLY_INIT_F
  63
  64/* MACH_TYPE_TRATS macro will be removed once added to mach-types */
  65#define MACH_TYPE_TRATS                 3928
  66#define CONFIG_MACH_TYPE                MACH_TYPE_TRATS
  67
  68/* Size of malloc() pool */
  69#define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + (1 << 20))
  70
  71/* select serial console configuration */
  72#define CONFIG_SERIAL2                  /* use SERIAL 2 */
  73#define CONFIG_BAUDRATE                 115200
  74
  75/* MMC */
  76#define CONFIG_GENERIC_MMC
  77#define CONFIG_MMC
  78#define CONFIG_S5P_SDHCI
  79#define CONFIG_SDHCI
  80#define CONFIG_MMC_SDMA
  81
  82/* PWM */
  83#define CONFIG_PWM
  84
  85/* It should define before config_cmd_default.h */
  86#define CONFIG_SYS_NO_FLASH
  87
  88/* Command definition */
  89#include <config_cmd_default.h>
  90
  91#undef CONFIG_CMD_FPGA
  92#undef CONFIG_CMD_MISC
  93#undef CONFIG_CMD_NET
  94#undef CONFIG_CMD_NFS
  95#undef CONFIG_CMD_XIMG
  96#undef CONFIG_CMD_CACHE
  97#undef CONFIG_CMD_ONENAND
  98#undef CONFIG_CMD_MTDPARTS
  99#define CONFIG_CMD_MMC
 100#define CONFIG_CMD_DFU
 101#define CONFIG_CMD_GPT
 102#define CONFIG_CMD_SETEXPR
 103
 104/* FAT */
 105#define CONFIG_CMD_FAT
 106#define CONFIG_FAT_WRITE
 107
 108/* USB Composite download gadget - g_dnl */
 109#define CONFIG_USBDOWNLOAD_GADGET
 110#define CONFIG_DFU_FUNCTION
 111#define CONFIG_DFU_MMC
 112
 113/* USB Samsung's IDs */
 114#define CONFIG_G_DNL_VENDOR_NUM 0x04E8
 115#define CONFIG_G_DNL_PRODUCT_NUM 0x6601
 116#define CONFIG_G_DNL_MANUFACTURER "Samsung"
 117
 118#define CONFIG_BOOTDELAY                1
 119#define CONFIG_ZERO_BOOTDELAY_CHECK
 120#define CONFIG_BOOTARGS                 "Please use defined boot"
 121#define CONFIG_BOOTCOMMAND              "run mmcboot"
 122
 123#define CONFIG_DEFAULT_CONSOLE          "console=ttySAC2,115200n8\0"
 124#define CONFIG_BOOTBLOCK                "10"
 125#define CONFIG_ENV_COMMON_BOOT          "${console} ${meminfo}"
 126
 127/* Tizen - partitions definitions */
 128#define PARTS_CSA               "csa-mmc"
 129#define PARTS_BOOTLOADER        "u-boot"
 130#define PARTS_BOOT              "boot"
 131#define PARTS_ROOT              "platform"
 132#define PARTS_DATA              "data"
 133#define PARTS_CSC               "csc"
 134#define PARTS_UMS               "ums"
 135
 136#define PARTS_DEFAULT \
 137        "uuid_disk=${uuid_gpt_disk};" \
 138        "name="PARTS_CSA",size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
 139        "name="PARTS_BOOTLOADER",size=60MiB," \
 140                "uuid=${uuid_gpt_"PARTS_BOOTLOADER"};" \
 141        "name="PARTS_BOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
 142        "name="PARTS_ROOT",size=1GiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
 143        "name="PARTS_DATA",size=3GiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
 144        "name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \
 145        "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \
 146
 147#define CONFIG_DFU_ALT \
 148        "u-boot mmc 80 400;" \
 149        "uImage ext4 0 2\0" \
 150
 151#define CONFIG_ENV_OVERWRITE
 152#define CONFIG_SYS_CONSOLE_INFO_QUIET
 153#define CONFIG_SYS_CONSOLE_IS_IN_ENV
 154
 155#define CONFIG_EXTRA_ENV_SETTINGS \
 156        "bootk=" \
 157                "run loaduimage; bootm 0x40007FC0\0" \
 158        "updatemmc=" \
 159                "mmc boot 0 1 1 1; mmc write 0 0x42008000 0 0x200;" \
 160                "mmc boot 0 1 1 0\0" \
 161        "updatebackup=" \
 162                "mmc boot 0 1 1 2; mmc write 0 0x42100000 0 0x200;" \
 163                "mmc boot 0 1 1 0\0" \
 164        "updatebootb=" \
 165                "mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \
 166        "lpj=lpj=3981312\0" \
 167        "nfsboot=" \
 168                "setenv bootargs root=/dev/nfs rw " \
 169                "nfsroot=${nfsroot},nolock,tcp " \
 170                "ip=${ipaddr}:${serverip}:${gatewayip}:" \
 171                "${netmask}:generic:usb0:off " CONFIG_ENV_COMMON_BOOT \
 172                "; run bootk\0" \
 173        "ramfsboot=" \
 174                "setenv bootargs root=/dev/ram0 rw rootfstype=ext2 " \
 175                "${console} ${meminfo} " \
 176                "initrd=0x43000000,8M ramdisk=8192\0" \
 177        "mmcboot=" \
 178                "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
 179                "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \
 180                "run loaduimage; bootm 0x40007FC0\0" \
 181        "bootchart=setenv opts init=/sbin/bootchartd; run bootcmd\0" \
 182        "boottrace=setenv opts initcall_debug; run bootcmd\0" \
 183        "mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \
 184        "verify=n\0" \
 185        "rootfstype=ext4\0" \
 186        "console=" CONFIG_DEFAULT_CONSOLE \
 187        "meminfo=crashkernel=32M@0x50000000\0" \
 188        "nfsroot=/nfsroot/arm\0" \
 189        "bootblock=" CONFIG_BOOTBLOCK "\0" \
 190        "loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \
 191        "mmcdev=0\0" \
 192        "mmcbootpart=2\0" \
 193        "mmcrootpart=5\0" \
 194        "opts=always_resume=1\0" \
 195        "partitions=" PARTS_DEFAULT \
 196        "dfu_alt_info=" CONFIG_DFU_ALT \
 197        "spladdr=0x40000100\0" \
 198        "splsize=0x200\0" \
 199        "splfile=falcon.bin\0" \
 200        "spl_export=" \
 201                   "setexpr spl_imgsize ${splsize} + 8 ;" \
 202                   "setexpr spl_imgaddr ${spladdr} - 8 ;" \
 203                   "setexpr spl_addr_tmp ${spladdr} - 4 ;" \
 204                   "mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \
 205                   "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
 206                   "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};" \
 207                   "spl export atags 0x40007FC0;" \
 208                   "crc32 ${spladdr} ${splsize} ${spl_imgaddr};" \
 209                   "mw.l ${spl_addr_tmp} ${splsize};" \
 210                   "ext4write mmc ${mmcdev}:${mmcbootpart}" \
 211                   " /${splfile} ${spl_imgaddr} ${spl_imgsize};" \
 212                   "setenv spl_imgsize;" \
 213                   "setenv spl_imgaddr;" \
 214                   "setenv spl_addr_tmp;\0"
 215
 216/* Miscellaneous configurable options */
 217#define CONFIG_SYS_LONGHELP             /* undef to save memory */
 218#define CONFIG_SYS_HUSH_PARSER          /* use "hush" command parser */
 219#define CONFIG_SYS_PROMPT               "TRATS # "
 220#define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
 221#define CONFIG_SYS_PBSIZE               384     /* Print Buffer Size */
 222#define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 223/* Boot Argument Buffer Size */
 224#define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 225/* memtest works on */
 226#define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE
 227#define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_SDRAM_BASE + 0x5000000)
 228#define CONFIG_SYS_LOAD_ADDR            (CONFIG_SYS_SDRAM_BASE + 0x4800000)
 229
 230#define CONFIG_SYS_HZ                   1000
 231
 232/* TRATS has 4 banks of DRAM */
 233#define CONFIG_NR_DRAM_BANKS    4
 234#define SDRAM_BANK_SIZE         (256UL << 20UL) /* 256 MB */
 235#define PHYS_SDRAM_1            CONFIG_SYS_SDRAM_BASE
 236#define PHYS_SDRAM_1_SIZE       SDRAM_BANK_SIZE
 237#define PHYS_SDRAM_2            (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
 238#define PHYS_SDRAM_2_SIZE       SDRAM_BANK_SIZE
 239#define PHYS_SDRAM_3            (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
 240#define PHYS_SDRAM_3_SIZE       SDRAM_BANK_SIZE
 241#define PHYS_SDRAM_4            (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
 242#define PHYS_SDRAM_4_SIZE       SDRAM_BANK_SIZE
 243
 244#define CONFIG_SYS_MEM_TOP_HIDE         (1 << 20)       /* ram console */
 245
 246#define CONFIG_SYS_MONITOR_BASE         0x00000000
 247#define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 2 sectors */
 248
 249#define CONFIG_ENV_IS_IN_MMC
 250#define CONFIG_SYS_MMC_ENV_DEV          0
 251#define CONFIG_ENV_SIZE                 4096
 252#define CONFIG_ENV_OFFSET               ((32 - 4) << 10) /* 32KiB - 4KiB */
 253
 254#define CONFIG_DOS_PARTITION
 255#define CONFIG_EFI_PARTITION
 256
 257/* EXT4 */
 258#define CONFIG_CMD_EXT4
 259#define CONFIG_CMD_EXT4_WRITE
 260/* Falcon mode definitions */
 261#define CONFIG_CMD_SPL
 262#define CONFIG_SYS_SPL_ARGS_ADDR        PHYS_SDRAM_1 + 0x100
 263
 264/* GPT */
 265#define CONFIG_EFI_PARTITION
 266#define CONFIG_PARTITION_UUIDS
 267
 268#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE)
 269#define CONFIG_SYS_CACHELINE_SIZE       32
 270
 271#define CONFIG_SOFT_I2C
 272#define CONFIG_SOFT_I2C_READ_REPEATED_START
 273#define CONFIG_SYS_I2C_INIT_BOARD
 274#define CONFIG_SYS_I2C_SPEED    50000
 275#define CONFIG_I2C_MULTI_BUS
 276#define CONFIG_SOFT_I2C_MULTI_BUS
 277#define CONFIG_SYS_MAX_I2C_BUS  15
 278
 279#include <asm/arch/gpio.h>
 280
 281/* I2C PMIC */
 282#define CONFIG_SOFT_I2C_I2C5_SCL exynos4_gpio_part1_get_nr(b, 7)
 283#define CONFIG_SOFT_I2C_I2C5_SDA exynos4_gpio_part1_get_nr(b, 6)
 284
 285/* I2C FG */
 286#define CONFIG_SOFT_I2C_I2C9_SCL exynos4_gpio_part2_get_nr(y4, 1)
 287#define CONFIG_SOFT_I2C_I2C9_SDA exynos4_gpio_part2_get_nr(y4, 0)
 288
 289#define CONFIG_SOFT_I2C_GPIO_SCL get_multi_scl_pin()
 290#define CONFIG_SOFT_I2C_GPIO_SDA get_multi_sda_pin()
 291#define I2C_INIT multi_i2c_init()
 292
 293#define CONFIG_POWER
 294#define CONFIG_POWER_I2C
 295#define CONFIG_POWER_MAX8997
 296
 297#define CONFIG_POWER_FG
 298#define CONFIG_POWER_FG_MAX17042
 299#define CONFIG_POWER_MUIC
 300#define CONFIG_POWER_MUIC_MAX8997
 301#define CONFIG_POWER_BATTERY
 302#define CONFIG_POWER_BATTERY_TRATS
 303#define CONFIG_USB_GADGET
 304#define CONFIG_USB_GADGET_S3C_UDC_OTG
 305#define CONFIG_USB_GADGET_DUALSPEED
 306#define CONFIG_USB_GADGET_VBUS_DRAW     2
 307
 308/* LCD */
 309#define CONFIG_EXYNOS_FB
 310#define CONFIG_LCD
 311#define CONFIG_CMD_BMP
 312#define CONFIG_BMP_32BPP
 313#define CONFIG_FB_ADDR          0x52504000
 314#define CONFIG_S6E8AX0
 315#define CONFIG_EXYNOS_MIPI_DSIM
 316#define CONFIG_VIDEO_BMP_GZIP
 317#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 120 * 4) + (1 << 12))
 318
 319#endif  /* __CONFIG_H */
 320