LXR uboot/include/configs/xpedite537x.h

   1/*
   2 * Copyright 2008 Extreme Engineering Solutions, Inc.
   3 * Copyright 2007-2008 Freescale Semiconductor, Inc.
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24/*
  25 * xpedite537x board configuration file
  26 */
  27#ifndef __CONFIG_H
  28#define __CONFIG_H
  29
  30/*
  31 * High Level Configuration Options
  32 */
  33#define CONFIG_BOOKE            1       /* BOOKE */
  34#define CONFIG_E500             1       /* BOOKE e500 family */
  35#define CONFIG_MPC85xx          1       /* MPC8540/60/55/41/48 */
  36#define CONFIG_MPC8572          1
  37#define CONFIG_XPEDITE5370      1
  38#define CONFIG_SYS_BOARD_NAME   "XPedite5370"
  39#define CONFIG_SYS_FORM_3U_VPX  1
  40#define CONFIG_BOARD_EARLY_INIT_R       /* Call board_pre_init */
  41
  42#ifndef CONFIG_SYS_TEXT_BASE
  43#define CONFIG_SYS_TEXT_BASE    0xfff80000
  44#endif
  45
  46#define CONFIG_PCI              1       /* Enable PCI/PCIE */
  47#define CONFIG_PCI_PNP          1       /* do pci plug-and-play */
  48#define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup */
  49#define CONFIG_PCIE1            1       /* PCIE controler 1 */
  50#define CONFIG_PCIE2            1       /* PCIE controler 2 */
  51#define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  52#define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  53#define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
  54#define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  55#define CONFIG_FSL_ELBC         1
  56
  57/*
  58 * Multicore config
  59 */
  60#define CONFIG_MP
  61#define CONFIG_BPTR_VIRT_ADDR   0xee000000      /* virt boot page address */
  62#define CONFIG_MPC8xxx_DISABLE_BPTR             /* Don't leave BPTR enabled */
  63
  64/*
  65 * DDR config
  66 */
  67#define CONFIG_FSL_DDR2
  68#undef CONFIG_FSL_DDR_INTERACTIVE
  69#define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
  70#define CONFIG_DDR_SPD
  71#define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  72#define SPD_EEPROM_ADDRESS1             0x54    /* Both channels use the */
  73#define SPD_EEPROM_ADDRESS2             0x54    /* same SPD data         */
  74#define SPD_EEPROM_OFFSET               0x200   /* OFFSET of SPD in EEPROM */
  75#define CONFIG_NUM_DDR_CONTROLLERS      2
  76#define CONFIG_DIMM_SLOTS_PER_CTLR      1
  77#define CONFIG_CHIP_SELECTS_PER_CTRL    1
  78#define CONFIG_DDR_ECC
  79#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  80#define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000 /* DDR is system memory*/
  81#define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  82#define CONFIG_VERY_BIG_RAM
  83
  84#ifndef __ASSEMBLY__
  85extern unsigned long get_board_sys_clk(unsigned long dummy);
  86extern unsigned long get_board_ddr_clk(unsigned long dummy);
  87#endif
  88
  89#define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0) /* sysclk for MPC85xx */
  90#define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk(0) /* ddrclk for MPC85xx */
  91
  92/*
  93 * These can be toggled for performance analysis, otherwise use default.
  94 */
  95#define CONFIG_L2_CACHE                 /* toggle L2 cache */
  96#define CONFIG_BTB                      /* toggle branch predition */
  97#define CONFIG_ENABLE_36BIT_PHYS        1
  98
  99#define CONFIG_SYS_CCSRBAR              0xef000000
 100#define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
 101
 102/*
 103 * Diagnostics
 104 */
 105#define CONFIG_SYS_ALT_MEMTEST
 106#define CONFIG_SYS_MEMTEST_START        0x10000000
 107#define CONFIG_SYS_MEMTEST_END          0x20000000
 108#define CONFIG_POST                     (CONFIG_SYS_POST_MEMORY | \
 109                                         CONFIG_SYS_POST_I2C)
 110#define I2C_ADDR_LIST                   {CONFIG_SYS_I2C_DS1621_ADDR,    \
 111                                         CONFIG_SYS_I2C_DS4510_ADDR,    \
 112                                         CONFIG_SYS_I2C_EEPROM_ADDR,    \
 113                                         CONFIG_SYS_I2C_LM90_ADDR,      \
 114                                         CONFIG_SYS_I2C_PCA953X_ADDR0,  \
 115                                         CONFIG_SYS_I2C_PCA953X_ADDR1,  \
 116                                         CONFIG_SYS_I2C_PCA953X_ADDR2,  \
 117                                         CONFIG_SYS_I2C_PCA953X_ADDR3,  \
 118                                         CONFIG_SYS_I2C_PEX8518_ADDR,   \
 119                                         CONFIG_SYS_I2C_RTC_ADDR}
 120/* The XPedite5370 can host an XMC which has an EEPROM at address 0x50 */
 121#define I2C_ADDR_IGNORE_LIST            {0x50}
 122
 123/*
 124 * Memory map
 125 * 0x0000_0000  0x7fff_ffff     DDR                     2G Cacheable
 126 * 0x8000_0000  0xbfff_ffff     PCIe1 Mem               1G non-cacheable
 127 * 0xc000_0000  0xcfff_ffff     PCIe2 Mem               256M non-cacheable
 128 * 0xe000_0000  0xe7ff_ffff     SRAM/SSRAM/L1 Cache     128M non-cacheable
 129 * 0xe800_0000  0xe87f_ffff     PCIe1 IO                8M non-cacheable
 130 * 0xe880_0000  0xe8ff_ffff     PCIe2 IO                8M non-cacheable
 131 * 0xee00_0000  0xee00_ffff     Boot page translation   4K non-cacheable
 132 * 0xef00_0000  0xef0f_ffff     CCSR/IMMR               1M non-cacheable
 133 * 0xef80_0000  0xef8f_ffff     NAND Flash              1M non-cacheable
 134 * 0xf000_0000  0xf7ff_ffff     NOR Flash 2             128M non-cacheable
 135 * 0xf800_0000  0xffff_ffff     NOR Flash 1             128M non-cacheable
 136 */
 137
 138#define CONFIG_SYS_LBC_LCRR     (LCRR_CLKDIV_8 | LCRR_EADC_3)
 139
 140/*
 141 * NAND flash configuration
 142 */
 143#define CONFIG_SYS_NAND_BASE            0xef800000
 144#define CONFIG_SYS_NAND_BASE2           0xef840000 /* Unused at this time */
 145#define CONFIG_SYS_NAND_BASE_LIST       {CONFIG_SYS_NAND_BASE, \
 146                                         CONFIG_SYS_NAND_BASE2}
 147#define CONFIG_SYS_MAX_NAND_DEVICE      2
 148#define CONFIG_MTD_NAND_VERIFY_WRITE
 149#define CONFIG_SYS_NAND_QUIET_TEST      /* 2nd NAND flash not always populated */
 150#define CONFIG_NAND_FSL_ELBC
 151
 152/*
 153 * NOR flash configuration
 154 */
 155#define CONFIG_SYS_FLASH_BASE           0xf8000000
 156#define CONFIG_SYS_FLASH_BASE2          0xf0000000
 157#define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
 158#define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 159#define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 160#define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Flash Erase Timeout (ms) */
 161#define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Flash Write Timeout (ms) */
 162#define CONFIG_FLASH_CFI_DRIVER
 163#define CONFIG_SYS_FLASH_CFI
 164#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 165#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST       { {0xfff40000, 0xc0000}, \
 166                                                  {0xf7f40000, 0xc0000} }
 167#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 168
 169/*
 170 * Chip select configuration
 171 */
 172/* NOR Flash 0 on CS0 */
 173#define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE  | \
 174                                 BR_PS_16               | \
 175                                 BR_V)
 176#define CONFIG_SYS_OR0_PRELIM   (OR_AM_128MB            | \
 177                                 OR_GPCM_CSNT           | \
 178                                 OR_GPCM_XACS           | \
 179                                 OR_GPCM_ACS_DIV2       | \
 180                                 OR_GPCM_SCY_8          | \
 181                                 OR_GPCM_TRLX           | \
 182                                 OR_GPCM_EHTR           | \
 183                                 OR_GPCM_EAD)
 184
 185/* NOR Flash 1 on CS1 */
 186#define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_FLASH_BASE2 | \
 187                                 BR_PS_16               | \
 188                                 BR_V)
 189#define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR0_PRELIM
 190
 191/* NAND flash on CS2 */
 192#define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_NAND_BASE   | \
 193                                 (2<<BR_DECC_SHIFT)     | \
 194                                 BR_PS_8                | \
 195                                 BR_MS_FCM              | \
 196                                 BR_V)
 197
 198/* NAND flash on CS2 */
 199#define CONFIG_SYS_OR2_PRELIM   (OR_AM_256KB    | \
 200                                 OR_FCM_PGS     | \
 201                                 OR_FCM_CSCT    | \
 202                                 OR_FCM_CST     | \
 203                                 OR_FCM_CHT     | \
 204                                 OR_FCM_SCY_1   | \
 205                                 OR_FCM_TRLX    | \
 206                                 OR_FCM_EHTR)
 207
 208/* NAND flash on CS3 */
 209#define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_NAND_BASE2  | \
 210                                 (2<<BR_DECC_SHIFT)     | \
 211                                 BR_PS_8                | \
 212                                 BR_MS_FCM              | \
 213                                 BR_V)
 214#define CONFIG_SYS_OR3_PRELIM   CONFIG_SYS_OR2_PRELIM
 215
 216/*
 217 * Use L1 as initial stack
 218 */
 219#define CONFIG_SYS_INIT_RAM_LOCK        1
 220#define CONFIG_SYS_INIT_RAM_ADDR        0xe0000000
 221#define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 222
 223#define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 224#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 225
 226#define CONFIG_SYS_MONITOR_LEN          (512 * 1024)    /* Reserve 512 KB for Mon */
 227#define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc */
 228
 229/*
 230 * Serial Port
 231 */
 232#define CONFIG_CONS_INDEX               1
 233#define CONFIG_SYS_NS16550
 234#define CONFIG_SYS_NS16550_SERIAL
 235#define CONFIG_SYS_NS16550_REG_SIZE     1
 236#define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 237#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 238#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 239#define CONFIG_SYS_BAUDRATE_TABLE       \
 240        {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 241#define CONFIG_BAUDRATE                 115200
 242#define CONFIG_LOADS_ECHO               1       /* echo on for serial download */
 243#define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 244
 245/*
 246 * Use the HUSH parser
 247 */
 248#define CONFIG_SYS_HUSH_PARSER
 249
 250/*
 251 * Pass open firmware flat tree
 252 */
 253#define CONFIG_OF_LIBFDT                1
 254#define CONFIG_OF_BOARD_SETUP           1
 255#define CONFIG_OF_STDOUT_VIA_ALIAS      1
 256
 257/*
 258 * I2C
 259 */
 260#define CONFIG_FSL_I2C                          /* Use FSL common I2C driver */
 261#define CONFIG_HARD_I2C                         /* I2C with hardware support */
 262#define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 263#define CONFIG_SYS_I2C_SLAVE            0x7F
 264#define CONFIG_SYS_I2C_OFFSET           0x3000
 265#define CONFIG_SYS_I2C2_OFFSET          0x3100
 266#define CONFIG_I2C_MULTI_BUS
 267
 268/* PEX8518 slave I2C interface */
 269#define CONFIG_SYS_I2C_PEX8518_ADDR     0x70
 270
 271/* I2C DS1631 temperature sensor */
 272#define CONFIG_SYS_I2C_DS1621_ADDR      0x48
 273#define CONFIG_DTT_DS1621
 274#define CONFIG_DTT_SENSORS              { 0 }
 275#define CONFIG_SYS_I2C_LM90_ADDR        0x4c
 276
 277/* I2C EEPROM - AT24C128B */
 278#define CONFIG_SYS_I2C_EEPROM_ADDR              0x54
 279#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 280#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       6       /* 64 byte pages */
 281#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* take up to 10 msec */
 282
 283/* I2C RTC */
 284#define CONFIG_RTC_M41T11               1
 285#define CONFIG_SYS_I2C_RTC_ADDR         0x68
 286#define CONFIG_SYS_M41T11_BASE_YEAR     2000
 287
 288/* GPIO/EEPROM/SRAM */
 289#define CONFIG_DS4510
 290#define CONFIG_SYS_I2C_DS4510_ADDR      0x51
 291
 292/* GPIO */
 293#define CONFIG_PCA953X
 294#define CONFIG_SYS_I2C_PCA953X_ADDR0    0x18
 295#define CONFIG_SYS_I2C_PCA953X_ADDR1    0x1c
 296#define CONFIG_SYS_I2C_PCA953X_ADDR2    0x1e
 297#define CONFIG_SYS_I2C_PCA953X_ADDR3    0x1f
 298#define CONFIG_SYS_I2C_PCA953X_ADDR     CONFIG_SYS_I2C_PCA953X_ADDR0
 299
 300/*
 301 * PU = pulled high, PD = pulled low
 302 * I = input, O = output, IO = input/output
 303 */
 304/* PCA9557 @ 0x18*/
 305#define CONFIG_SYS_PCA953X_C0_SER0_EN           0x01 /* PU; UART0 enable (1: enabled) */
 306#define CONFIG_SYS_PCA953X_C0_SER0_MODE         0x02 /* PU; UART0 serial mode select */
 307#define CONFIG_SYS_PCA953X_C0_SER1_EN           0x04 /* PU; UART1 enable (1: enabled) */
 308#define CONFIG_SYS_PCA953X_C0_SER1_MODE         0x08 /* PU; UART1 serial mode select */
 309#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS     0x10 /* PU; Boot flash CS select */
 310#define CONFIG_SYS_PCA953X_NVM_WP               0x20 /* PU; Set to 0 to enable NVM writing */
 311#define CONFIG_SYS_PCA953X_C0_VCORE_VID2        0x40 /* VID2 of ISL6262 */
 312#define CONFIG_SYS_PCA953X_C0_VCORE_VID3        0x80 /* VID3 of ISL6262 */
 313
 314/* PCA9557 @ 0x1c*/
 315#define CONFIG_SYS_PCA953X_XMC0_ROOT0           0x01 /* PU; Low if XMC is RC */
 316#define CONFIG_SYS_PCA953X_XMC0_MVMR0           0x02 /* XMC EEPROM write protect */
 317#define CONFIG_SYS_PCA953X_XMC0_WAKE            0x04 /* PU; XMC wake */
 318#define CONFIG_SYS_PCA953X_XMC0_BIST            0x08 /* PU; XMC built in self test */
 319#define CONFIG_SYS_PCA953X_XMC_PRESENT          0x10 /* PU; Low if XMC module installed */
 320#define CONFIG_SYS_PCA953X_PMC_PRESENT          0x20 /* PU; Low if PMC module installed */
 321#define CONFIG_SYS_PCA953X_PMC0_MONARCH         0x40 /* PMC monarch mode enable */
 322#define CONFIG_SYS_PCA953X_PMC0_EREADY          0x80 /* PU; PMC PCI eready */
 323
 324/* PCA9557 @ 0x1e*/
 325#define CONFIG_SYS_PCA953X_P0_GA0               0x01 /* PU; VPX Geographical address */
 326#define CONFIG_SYS_PCA953X_P0_GA1               0x02 /* PU; VPX Geographical address */
 327#define CONFIG_SYS_PCA953X_P0_GA2               0x04 /* PU; VPX Geographical address */
 328#define CONFIG_SYS_PCA953X_P0_GA3               0x08 /* PU; VPX Geographical address */
 329#define CONFIG_SYS_PCA953X_P0_GA4               0x10 /* PU; VPX Geographical address */
 330#define CONFIG_SYS_PCA953X_P0_GAP               0x20 /* PU; tied to VPX P0.GAP */
 331#define CONFIG_SYS_PCA953X_P1_SYSEN             0x80 /* PU; Pulled high; tied to VPX P1.SYSCON */
 332
 333/* PCA9557 @ 0x1f */
 334#define CONFIG_SYS_PCA953X_GPIO_VPX0            0x01 /* PU */
 335#define CONFIG_SYS_PCA953X_GPIO_VPX1            0x02 /* PU */
 336#define CONFIG_SYS_PCA953X_GPIO_VPX2            0x04 /* PU */
 337#define CONFIG_SYS_PCA953X_GPIO_VPX3            0x08 /* PU */
 338#define CONFIG_SYS_PCA953X_VPX_FRU_WRCTL        0x10 /* PD; I2C master source for FRU SEEPROM */
 339
 340/*
 341 * General PCI
 342 * Memory space is mapped 1-1, but I/O space must start from 0.
 343 */
 344/* PCIE1 - VPX P1 */
 345#define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 346#define CONFIG_SYS_PCIE1_MEM_PHYS       CONFIG_SYS_PCIE1_MEM_BUS
 347#define CONFIG_SYS_PCIE1_MEM_SIZE       0x40000000      /* 1G */
 348#define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 349#define CONFIG_SYS_PCIE1_IO_PHYS        0xe8000000
 350#define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000      /* 8M */
 351
 352/* PCIE2 - PEX8518 */
 353#define CONFIG_SYS_PCIE2_MEM_BUS        0xc0000000
 354#define CONFIG_SYS_PCIE2_MEM_PHYS       CONFIG_SYS_PCIE2_MEM_BUS
 355#define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 356#define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 357#define CONFIG_SYS_PCIE2_IO_PHYS        0xe8800000
 358#define CONFIG_SYS_PCIE2_IO_SIZE        0x00800000      /* 8M */
 359
 360/*
 361 * Networking options
 362 */
 363#define CONFIG_TSEC_ENET                /* tsec ethernet support */
 364#define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 365#define CONFIG_TSEC_TBI
 366#define CONFIG_MII              1       /* MII PHY management */
 367#define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 368#define CONFIG_ETHPRIME         "eTSEC2"
 369
 370/*
 371 * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force
 372 * 1000mbps SGMII link
 373 */
 374#define CONFIG_TSEC_TBICR_SETTINGS ( \
 375                TBICR_PHY_RESET \
 376                | TBICR_FULL_DUPLEX \
 377                | TBICR_SPEED1_SET \
 378                )
 379
 380#define CONFIG_TSEC1            1
 381#define CONFIG_TSEC1_NAME       "eTSEC1"
 382#define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 383#define TSEC1_PHY_ADDR          1
 384#define TSEC1_PHYIDX            0
 385#define CONFIG_HAS_ETH0
 386
 387#define CONFIG_TSEC2            1
 388#define CONFIG_TSEC2_NAME       "eTSEC2"
 389#define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 390#define TSEC2_PHY_ADDR          2
 391#define TSEC2_PHYIDX            0
 392#define CONFIG_HAS_ETH1
 393
 394/*
 395 * Command configuration.
 396 */
 397#include <config_cmd_default.h>
 398
 399#define CONFIG_CMD_ASKENV
 400#define CONFIG_CMD_DATE
 401#define CONFIG_CMD_DHCP
 402#define CONFIG_CMD_DS4510
 403#define CONFIG_CMD_DS4510_INFO
 404#define CONFIG_CMD_DTT
 405#define CONFIG_CMD_EEPROM
 406#define CONFIG_CMD_ELF
 407#define CONFIG_CMD_FLASH
 408#define CONFIG_CMD_I2C
 409#define CONFIG_CMD_JFFS2
 410#define CONFIG_CMD_MII
 411#define CONFIG_CMD_NAND
 412#define CONFIG_CMD_NET
 413#define CONFIG_CMD_PCA953X
 414#define CONFIG_CMD_PCA953X_INFO
 415#define CONFIG_CMD_PCI
 416#define CONFIG_CMD_PCI_ENUM
 417#define CONFIG_CMD_PING
 418#define CONFIG_CMD_SAVEENV
 419#define CONFIG_CMD_SNTP
 420#define CONFIG_CMD_REGINFO
 421
 422/*
 423 * Miscellaneous configurable options
 424 */
 425#define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 426#define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 427#define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 428#define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 429#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 430#define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 431#define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 432#define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 433#define CONFIG_CMDLINE_EDITING  1               /* add command line history     */
 434#define CONFIG_AUTO_COMPLETE    1               /* add autocompletion support */
 435#define CONFIG_LOADADDR         0x1000000       /* default location for tftp and bootm */
 436#define CONFIG_BOOTDELAY        3               /* -1 disables auto-boot */
 437#define CONFIG_PANIC_HANG                       /* do not reset board on panic */
 438#define CONFIG_PREBOOT                          /* enable preboot variable */
 439#define CONFIG_FIT              1
 440#define CONFIG_FIT_VERBOSE      1
 441#define CONFIG_INTEGRITY                        /* support booting INTEGRITY OS */
 442
 443/*
 444 * For booting Linux, the board info and command line data
 445 * have to be in the first 16 MB of memory, since this is
 446 * the maximum mapped by the Linux kernel during initialization.
 447 */
 448#define CONFIG_SYS_BOOTMAPSZ    (16 << 20)      /* Initial Memory map for Linux*/
 449#define CONFIG_SYS_BOOTM_LEN    (16 << 20)      /* Increase max gunzip size */
 450
 451/*
 452 * Environment Configuration
 453 */
 454#define CONFIG_ENV_IS_IN_FLASH  1
 455#define CONFIG_ENV_SECT_SIZE    0x20000         /* 128k (one sector) for env */
 456#define CONFIG_ENV_SIZE         0x8000
 457#define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
 458
 459/*
 460 * Flash memory map:
 461 * fff80000 - ffffffff     Pri U-Boot (512 KB)
 462 * fff40000 - fff7ffff     Pri U-Boot Environment (256 KB)
 463 * fff00000 - fff3ffff     Pri FDT (256KB)
 464 * fef00000 - ffefffff     Pri OS image (16MB)
 465 * f8000000 - feefffff     Pri OS Use/Filesystem (111MB)
 466 *
 467 * f7f80000 - f7ffffff     Sec U-Boot (512 KB)
 468 * f7f40000 - f7f7ffff     Sec U-Boot Environment (256 KB)
 469 * f7f00000 - f7f3ffff     Sec FDT (256KB)
 470 * f6f00000 - f7efffff     Sec OS image (16MB)
 471 * f0000000 - f6efffff     Sec OS Use/Filesystem (111MB)
 472 */
 473#define CONFIG_UBOOT1_ENV_ADDR  __stringify(0xfff80000)
 474#define CONFIG_UBOOT2_ENV_ADDR  __stringify(0xf7f80000)
 475#define CONFIG_FDT1_ENV_ADDR    __stringify(0xfff00000)
 476#define CONFIG_FDT2_ENV_ADDR    __stringify(0xf7f00000)
 477#define CONFIG_OS1_ENV_ADDR     __stringify(0xfef00000)
 478#define CONFIG_OS2_ENV_ADDR     __stringify(0xf6f00000)
 479
 480#define CONFIG_PROG_UBOOT1                                              \
 481        "$download_cmd $loadaddr $ubootfile; "                          \
 482        "if test $? -eq 0; then "                                       \
 483                "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; "         \
 484                "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; "               \
 485                "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; "       \
 486                "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; "          \
 487                "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; "      \
 488                "if test $? -ne 0; then "                               \
 489                        "echo PROGRAM FAILED; "                         \
 490                "else; "                                                \
 491                        "echo PROGRAM SUCCEEDED; "                      \
 492                "fi; "                                                  \
 493        "else; "                                                        \
 494                "echo DOWNLOAD FAILED; "                                \
 495        "fi;"
 496
 497#define CONFIG_PROG_UBOOT2                                              \
 498        "$download_cmd $loadaddr $ubootfile; "                          \
 499        "if test $? -eq 0; then "                                       \
 500                "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; "         \
 501                "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; "               \
 502                "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; "       \
 503                "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; "          \
 504                "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; "      \
 505                "if test $? -ne 0; then "                               \
 506                        "echo PROGRAM FAILED; "                         \
 507                "else; "                                                \
 508                        "echo PROGRAM SUCCEEDED; "                      \
 509                "fi; "                                                  \
 510        "else; "                                                        \
 511                "echo DOWNLOAD FAILED; "                                \
 512        "fi;"
 513
 514#define CONFIG_BOOT_OS_NET                                              \
 515        "$download_cmd $osaddr $osfile; "                               \
 516        "if test $? -eq 0; then "                                       \
 517                "if test -n $fdtaddr; then "                            \
 518                        "$download_cmd $fdtaddr $fdtfile; "             \
 519                        "if test $? -eq 0; then "                       \
 520                                "bootm $osaddr - $fdtaddr; "            \
 521                        "else; "                                        \
 522                                "echo FDT DOWNLOAD FAILED; "            \
 523                        "fi; "                                          \
 524                "else; "                                                \
 525                        "bootm $osaddr; "                               \
 526                "fi; "                                                  \
 527        "else; "                                                        \
 528                "echo OS DOWNLOAD FAILED; "                             \
 529        "fi;"
 530
 531#define CONFIG_PROG_OS1                                                 \
 532        "$download_cmd $osaddr $osfile; "                               \
 533        "if test $? -eq 0; then "                                       \
 534                "erase "CONFIG_OS1_ENV_ADDR" +$filesize; "              \
 535                "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "        \
 536                "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "       \
 537                "if test $? -ne 0; then "                               \
 538                        "echo OS PROGRAM FAILED; "                      \
 539                "else; "                                                \
 540                        "echo OS PROGRAM SUCCEEDED; "                   \
 541                "fi; "                                                  \
 542        "else; "                                                        \
 543                "echo OS DOWNLOAD FAILED; "                             \
 544        "fi;"
 545
 546#define CONFIG_PROG_OS2                                                 \
 547        "$download_cmd $osaddr $osfile; "                               \
 548        "if test $? -eq 0; then "                                       \
 549                "erase "CONFIG_OS2_ENV_ADDR" +$filesize; "              \
 550                "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "        \
 551                "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "       \
 552                "if test $? -ne 0; then "                               \
 553                        "echo OS PROGRAM FAILED; "                      \
 554                "else; "                                                \
 555                        "echo OS PROGRAM SUCCEEDED; "                   \
 556                "fi; "                                                  \
 557        "else; "                                                        \
 558                "echo OS DOWNLOAD FAILED; "                             \
 559        "fi;"
 560
 561#define CONFIG_PROG_FDT1                                                \
 562        "$download_cmd $fdtaddr $fdtfile; "                             \
 563        "if test $? -eq 0; then "                                       \
 564                "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;"              \
 565                "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "      \
 566                "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "     \
 567                "if test $? -ne 0; then "                               \
 568                        "echo FDT PROGRAM FAILED; "                     \
 569                "else; "                                                \
 570                        "echo FDT PROGRAM SUCCEEDED; "                  \
 571                "fi; "                                                  \
 572        "else; "                                                        \
 573                "echo FDT DOWNLOAD FAILED; "                            \
 574        "fi;"
 575
 576#define CONFIG_PROG_FDT2                                                \
 577        "$download_cmd $fdtaddr $fdtfile; "                             \
 578        "if test $? -eq 0; then "                                       \
 579                "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;"              \
 580                "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "      \
 581                "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "     \
 582                "if test $? -ne 0; then "                               \
 583                        "echo FDT PROGRAM FAILED; "                     \
 584                "else; "                                                \
 585                        "echo FDT PROGRAM SUCCEEDED; "                  \
 586                "fi; "                                                  \
 587        "else; "                                                        \
 588                "echo FDT DOWNLOAD FAILED; "                            \
 589        "fi;"
 590
 591#define CONFIG_EXTRA_ENV_SETTINGS                                       \
 592        "autoload=yes\0"                                                \
 593        "download_cmd=tftp\0"                                           \
 594        "console_args=console=ttyS0,115200\0"                           \
 595        "root_args=root=/dev/nfs rw\0"                                  \
 596        "misc_args=ip=on\0"                                             \
 597        "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
 598        "bootfile=/home/user/file\0"                                    \
 599        "osfile=/home/user/board.uImage\0"                              \
 600        "fdtfile=/home/user/board.dtb\0"                                \
 601        "ubootfile=/home/user/u-boot.bin\0"                             \
 602        "fdtaddr=c00000\0"                                              \
 603        "osaddr=0x1000000\0"                                            \
 604        "loadaddr=0x1000000\0"                                          \
 605        "prog_uboot1="CONFIG_PROG_UBOOT1"\0"                            \
 606        "prog_uboot2="CONFIG_PROG_UBOOT2"\0"                            \
 607        "prog_os1="CONFIG_PROG_OS1"\0"                                  \
 608        "prog_os2="CONFIG_PROG_OS2"\0"                                  \
 609        "prog_fdt1="CONFIG_PROG_FDT1"\0"                                \
 610        "prog_fdt2="CONFIG_PROG_FDT2"\0"                                \
 611        "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0"          \
 612        "bootcmd_flash1=run set_bootargs; "                             \
 613                "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
 614        "bootcmd_flash2=run set_bootargs; "                             \
 615                "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
 616        "bootcmd=run bootcmd_flash1\0"
 617#endif  /* __CONFIG_H */
 618