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30#ifndef __MPC8260_H__
31#define __MPC8260_H__
32
33#ifdef CONFIG_MPC8255
34#define CPU_ID_STR "MPC8255"
35#endif
36#ifndef CPU_ID_STR
37#if defined(CONFIG_MPC8272_FAMILY)
38#ifdef CONFIG_MPC8247
39#define CPU_ID_STR "MPC8247"
40#elif defined CONFIG_MPC8248
41#define CPU_ID_STR "MPC8248"
42#elif defined CONFIG_MPC8271
43#define CPU_ID_STR "MPC8271"
44#else
45#define CPU_ID_STR "MPC8272"
46#endif
47#else
48#define CPU_ID_STR "MPC8260"
49#endif
50#endif
51
52
53
54
55#define EXC_OFF_SYS_RESET 0x0100
56#define _START_OFFSET EXC_OFF_SYS_RESET
57
58
59
60
61#define BCR_EBM 0x80000000
62#define BCR_APD_MSK 0x70000000
63#define BCR_L2C 0x08000000
64#define BCR_L2D_MSK 0x07000000
65#define BCR_PLDP 0x00800000
66#define BCR_EAV 0x00400000
67#define BCR_ETM 0x00080000
68#define BCR_LETM 0x00040000
69#define BCR_EPAR 0x00020000
70#define BCR_LEPAR 0x00010000
71#define BCR_NPQM0 0x00008000
72#define BCR_NPQM1 0x00004000
73#define BCR_NPQM2 0x00002000
74#define BCR_EXDD 0x00000400
75#define BCR_ISPS 0x00000010
76
77
78
79
80
81#define PPC_ACR_DBGD 0x20
82#define PPC_ACR_EARB 0x10
83#define PPC_ACR_PRKM_MSK 0x0f
84
85#define PPC_ACR_PRKM_CPMH 0x00
86#define PPC_ACR_PRKM_CPMM 0x01
87#define PPC_ACR_PRKM_CPML 0x02
88#define PPC_ACR_PRKM_CORE 0x06
89#define PPC_ACR_PRKM_EXT1 0x07
90#define PPC_ACR_PRKM_EXT2 0x08
91#define PPC_ACR_PRKM_EXT3 0x09
92
93
94
95
96#define PPC_ALRH_PF0_MSK 0xf0000000
97#define PPC_ALRH_PF1_MSK 0x0f000000
98#define PPC_ALRH_PF2_MSK 0x00f00000
99#define PPC_ALRH_PF3_MSK 0x000f0000
100#define PPC_ALRH_PF4_MSK 0x0000f000
101#define PPC_ALRH_PF5_MSK 0x00000f00
102#define PPC_ALRH_PF6_MSK 0x000000f0
103#define PPC_ALRH_PF7_MSK 0x0000000f
104#define PPC_ALRL_PF8_MSK 0xf0000000
105#define PPC_ALRL_PF9_MSK 0x0f000000
106#define PPC_ALRL_PF10_MSK 0x00f00000
107#define PPC_ALRL_PF11_MSK 0x000f0000
108#define PPC_ALRL_PF12_MSK 0x0000f000
109#define PPC_ALRL_PF13_MSK 0x00000f00
110#define PPC_ALRL_PF14_MSK 0x000000f0
111#define PPC_ALRL_PF15_MSK 0x0000000f
112
113
114
115
116#define LCL_ACR_DBGD 0x20
117#define LCL_ACR_PRKM_MSK 0x0f
118
119#define LCL_ACR_PRKM_CPMH 0x00
120#define LCL_ACR_PRKM_CPMM 0x01
121#define LCL_ACR_PRKM_CPML 0x02
122#define LCL_ACR_PRKM_HOST 0x03
123
124
125
126
127#define LCL_ALRH_PF0_MSK 0xf0000000
128#define LCL_ALRH_PF1_MSK 0x0f000000
129#define LCL_ALRH_PF2_MSK 0x00f00000
130#define LCL_ALRH_PF3_MSK 0x000f0000
131#define LCL_ALRH_PF4_MSK 0x0000f000
132#define LCL_ALRH_PF5_MSK 0x00000f00
133#define LCL_ALRH_PF6_MSK 0x000000f0
134#define LCL_ALRH_PF7_MSK 0x0000000f
135#define LCL_ALRL_PF8_MSK 0xf0000000
136#define LCL_ALRL_PF9_MSK 0x0f000000
137#define LCL_ALRL_PF10_MSK 0x00f00000
138#define LCL_ALRL_PF11_MSK 0x000f0000
139#define LCL_ALRL_PF12_MSK 0x0000f000
140#define LCL_ALRL_PF13_MSK 0x00000f00
141#define LCL_ALRL_PF14_MSK 0x000000f0
142#define LCL_ALRL_PF15_MSK 0x0000000f
143
144
145
146
147#define SIUMCR_BBD 0x80000000
148#define SIUMCR_ESE 0x40000000
149#define SIUMCR_PBSE 0x20000000
150#define SIUMCR_CDIS 0x10000000
151#define SIUMCR_DPPC00 0x00000000
152#define SIUMCR_DPPC01 0x04000000
153#define SIUMCR_DPPC10 0x08000000
154#define SIUMCR_DPPC11 0x0c000000
155#define SIUMCR_L2CPC00 0x00000000
156#define SIUMCR_L2CPC01 0x01000000
157#define SIUMCR_L2CPC10 0x02000000
158#define SIUMCR_L2CPC11 0x03000000
159#define SIUMCR_LBPC00 0x00000000
160#define SIUMCR_LBPC01 0x00400000
161#define SIUMCR_LBPC10 0x00800000
162#define SIUMCR_LBPC11 0x00c00000
163#define SIUMCR_APPC00 0x00000000
164#define SIUMCR_APPC01 0x00100000
165#define SIUMCR_APPC10 0x00200000
166#define SIUMCR_APPC11 0x00300000
167#define SIUMCR_CS10PC00 0x00000000
168#define SIUMCR_CS10PC01 0x00040000
169#define SIUMCR_CS10PC10 0x00080000
170#define SIUMCR_CS10PC11 0x000c0000
171#define SIUMCR_BCTLC00 0x00000000
172#define SIUMCR_BCTLC01 0x00010000
173#define SIUMCR_BCTLC10 0x00020000
174#define SIUMCR_BCTLC11 0x00030000
175#define SIUMCR_MMR00 0x00000000
176#define SIUMCR_MMR01 0x00004000
177#define SIUMCR_MMR10 0x00008000
178#define SIUMCR_MMR11 0x0000c000
179#define SIUMCR_LPBSE 0x00002000
180#define SIUMCR_ABE 0x00000400
181
182
183
184
185#define IMMR_ISB_MSK 0xfffe0000
186#define IMMR_PARTNUM_MSK 0x0000ff00
187#define IMMR_MASKNUM_MSK 0x000000ff
188
189
190
191
192#define SYPCR_SWTC 0xffff0000
193#define SYPCR_BMT 0x0000ff00
194#define SYPCR_PBME 0x00000080
195#define SYPCR_LBME 0x00000040
196#define SYPCR_SWE 0x00000004
197#define SYPCR_SWRI 0x00000002
198#define SYPCR_SWP 0x00000001
199
200
201
202
203#define TMCNTSC_SEC 0x0080
204#define TMCNTSC_ALR 0x0040
205#define TMCNTSC_SIE 0x0008
206#define TMCNTSC_ALE 0x0004
207#define TMCNTSC_TCF 0x0002
208#define TMCNTSC_TCE 0x0001
209
210
211
212
213#if 0
214#define PISCR_PS 0x0080
215#define PISCR_PIE 0x0004
216#define PISCR_PTF 0x0002
217#define PISCR_PTE 0x0001
218#endif
219
220
221
222
223#define RSR_JTRS 0x00000020
224#define RSR_CSRS 0x00000010
225#define RSR_SWRS 0x00000008
226#define RSR_BMRS 0x00000004
227#define RSR_ESRS 0x00000002
228#define RSR_EHRS 0x00000001
229
230#define RSR_ALLBITS (RSR_JTRS|RSR_CSRS|RSR_SWRS|RSR_BMRS|RSR_ESRS|RSR_EHRS)
231
232
233
234
235#define RMR_CSRE 0x00000001
236
237
238
239
240#define HRCW_EARB 0x80000000
241#define HRCW_EXMC 0x40000000
242#define HRCW_CDIS 0x20000000
243#define HRCW_EBM 0x10000000
244#define HRCW_BPS00 0x00000000
245#define HRCW_BPS01 0x04000000
246#define HRCW_BPS10 0x08000000
247#define HRCW_BPS11 0x0c000000
248#define HRCW_CIP 0x02000000
249#define HRCW_ISPS 0x01000000
250#define HRCW_L2CPC00 0x00000000
251#define HRCW_L2CPC01 0x00400000
252#define HRCW_L2CPC10 0x00800000
253#define HRCW_L2CPC11 0x00c00000
254#define HRCW_DPPC00 0x00000000
255#define HRCW_DPPC01 0x00100000
256#define HRCW_DPPC10 0x00200000
257#define HRCW_DPPC11 0x00300000
258#define HRCW_reserved1 0x00080000
259#define HRCW_ISB000 0x00000000
260#define HRCW_ISB001 0x00010000
261#define HRCW_ISB010 0x00020000
262#define HRCW_ISB011 0x00030000
263#define HRCW_ISB100 0x00040000
264#define HRCW_ISB101 0x00050000
265#define HRCW_ISB110 0x00060000
266#define HRCW_ISB111 0x00070000
267#define HRCW_BMS 0x00008000
268#define HRCW_BBD 0x00004000
269#define HRCW_MMR00 0x00000000
270#define HRCW_MMR01 0x00001000
271#define HRCW_MMR10 0x00002000
272#define HRCW_MMR11 0x00003000
273#define HRCW_LBPC00 0x00000000
274#define HRCW_LBPC01 0x00000400
275#define HRCW_LBPC10 0x00000800
276#define HRCW_LBPC11 0x00000c00
277#define HRCW_APPC00 0x00000000
278#define HRCW_APPC01 0x00000100
279#define HRCW_APPC10 0x00000200
280#define HRCW_APPC11 0x00000300
281#define HRCW_CS10PC00 0x00000000
282#define HRCW_CS10PC01 0x00000040
283#define HRCW_CS10PC10 0x00000080
284#define HRCW_CS10PC11 0x000000c0
285#define HRCW_MODCK_H0000 0x00000000
286#define HRCW_MODCK_H0001 0x00000001
287#define HRCW_MODCK_H0010 0x00000002
288#define HRCW_MODCK_H0011 0x00000003
289#define HRCW_MODCK_H0100 0x00000004
290#define HRCW_MODCK_H0101 0x00000005
291#define HRCW_MODCK_H0110 0x00000006
292#define HRCW_MODCK_H0111 0x00000007
293#define HRCW_MODCK_H1000 0x00000008
294#define HRCW_MODCK_H1001 0x00000009
295#define HRCW_MODCK_H1010 0x0000000a
296#define HRCW_MODCK_H1011 0x0000000b
297#define HRCW_MODCK_H1100 0x0000000c
298#define HRCW_MODCK_H1101 0x0000000d
299#define HRCW_MODCK_H1110 0x0000000e
300#define HRCW_MODCK_H1111 0x0000000f
301
302
303
304
305#define SCCR_PCI_MODE 0x00000100
306#define SCCR_PCI_MODCK 0x00000080
307#define SCCR_PCIDF_MSK 0x00000078
308#define SCCR_PCIDF_SHIFT 3
309#define SCCR_CLPD 0x00000004
310#define SCCR_DFBRG_MSK 0x00000003
311#define SCCR_DFBRG_SHIFT 0
312
313#define SCCR_DFBRG00 0x00000000
314#define SCCR_DFBRG01 0x00000001
315#define SCCR_DFBRG10 0x00000002
316#define SCCR_DFBRG11 0x00000003
317
318
319
320
321#define SCMR_CORECNF_MSK 0x1f000000
322#define SCMR_CORECNF_SHIFT 24
323#define SCMR_BUSDF_MSK 0x00f00000
324#define SCMR_BUSDF_SHIFT 20
325#define SCMR_CPMDF_MSK 0x000f0000
326#define SCMR_CPMDF_SHIFT 16
327#define SCMR_PLLDF 0x00001000
328#define SCMR_PLLMF_MSK 0x00000fff
329#define SCMR_PLLMF_MSKH7 0x0000000f
330#define SCMR_PLLMF_SHIFT 0
331
332
333
334
335
336#define MxMR_BSEL 0x80000000
337#define MxMR_RFEN 0x40000000
338#define MxMR_OP_MSK 0x30000000
339#define MxMR_AMx_MSK 0x07000000
340#define MxMR_DSx_MSK 0x00c00000
341#define MxMR_G0CLx_MSK 0x00380000
342#define MxMR_GPL_x4DIS 0x00040000
343#define MxMR_RLFx_MSK 0x0003c000
344#define MxMR_WLFx_MSK 0x00003c00
345#define MxMR_TLFx_MSK 0x000003c0
346#define MxMR_MAD_MSK 0x0000003f
347
348#define MxMR_OP_NORM 0x00000000
349#define MxMR_OP_WARR 0x10000000
350#define MxMR_OP_RARR 0x20000000
351#define MxMR_OP_RUNP 0x30000000
352
353#define MxMR_AMx_TYPE_0 0x00000000
354#define MxMR_AMx_TYPE_1 0x01000000
355#define MxMR_AMx_TYPE_2 0x02000000
356#define MxMR_AMx_TYPE_3 0x03000000
357#define MxMR_AMx_TYPE_4 0x04000000
358#define MxMR_AMx_TYPE_5 0x05000000
359
360#define MxMR_DSx_1_CYCL 0x00000000
361#define MxMR_DSx_2_CYCL 0x00400000
362#define MxMR_DSx_3_CYCL 0x00800000
363#define MxMR_DSx_4_CYCL 0x00c00000
364
365#define MxMR_G0CLx_A12 0x00000000
366#define MxMR_G0CLx_A11 0x00080000
367#define MxMR_G0CLx_A10 0x00100000
368#define MxMR_G0CLx_A9 0x00180000
369#define MxMR_G0CLx_A8 0x00200000
370#define MxMR_G0CLx_A7 0x00280000
371#define MxMR_G0CLx_A6 0x00300000
372#define MxMR_G0CLx_A5 0x00380000
373
374#define MxMR_RLFx_1X 0x00004000
375#define MxMR_RLFx_2X 0x00008000
376#define MxMR_RLFx_3X 0x0000c000
377#define MxMR_RLFx_4X 0x00010000
378#define MxMR_RLFx_5X 0x00014000
379#define MxMR_RLFx_6X 0x00018000
380#define MxMR_RLFx_7X 0x0001c000
381#define MxMR_RLFx_8X 0x00020000
382#define MxMR_RLFx_9X 0x00024000
383#define MxMR_RLFx_10X 0x00028000
384#define MxMR_RLFx_11X 0x0002c000
385#define MxMR_RLFx_12X 0x00030000
386#define MxMR_RLFx_13X 0x00034000
387#define MxMR_RLFx_14X 0x00038000
388#define MxMR_RLFx_15X 0x0003c000
389#define MxMR_RLFx_16X 0x00000000
390
391#define MxMR_WLFx_1X 0x00000400
392#define MxMR_WLFx_2X 0x00000800
393#define MxMR_WLFx_3X 0x00000c00
394#define MxMR_WLFx_4X 0x00001000
395#define MxMR_WLFx_5X 0x00001400
396#define MxMR_WLFx_6X 0x00001800
397#define MxMR_WLFx_7X 0x00001c00
398#define MxMR_WLFx_8X 0x00002000
399#define MxMR_WLFx_9X 0x00002400
400#define MxMR_WLFx_10X 0x00002800
401#define MxMR_WLFx_11X 0x00002c00
402#define MxMR_WLFx_12X 0x00003000
403#define MxMR_WLFx_13X 0x00003400
404#define MxMR_WLFx_14X 0x00003800
405#define MxMR_WLFx_15X 0x00003c00
406#define MxMR_WLFx_16X 0x00000000
407
408#define MxMR_TLFx_1X 0x00000040
409#define MxMR_TLFx_2X 0x00000080
410#define MxMR_TLFx_3X 0x000000c0
411#define MxMR_TLFx_4X 0x00000100
412#define MxMR_TLFx_5X 0x00000140
413#define MxMR_TLFx_6X 0x00000180
414#define MxMR_TLFx_7X 0x000001c0
415#define MxMR_TLFx_8X 0x00000200
416#define MxMR_TLFx_9X 0x00000240
417#define MxMR_TLFx_10X 0x00000280
418#define MxMR_TLFx_11X 0x000002c0
419#define MxMR_TLFx_12X 0x00000300
420#define MxMR_TLFx_13X 0x00000340
421#define MxMR_TLFx_14X 0x00000380
422#define MxMR_TLFx_15X 0x000003c0
423#define MxMR_TLFx_16X 0x00000000
424
425
426
427
428
429#define BRx_BA_MSK 0xffff8000
430#define BRx_PS_MSK 0x00001800
431#define BRx_DECC_MSK 0x00000600
432#define BRx_WP 0x00000100
433#define BRx_MS_MSK 0x000000e0
434#define BRx_EMEMC 0x00000010
435#define BRx_ATOM_MSK 0x0000000c
436#define BRx_DR 0x00000002
437#define BRx_V 0x00000001
438
439#define BRx_PS_64 0x00000000
440#define BRx_PS_8 0x00000800
441#define BRx_PS_16 0x00001000
442#define BRx_PS_32 0x00001800
443
444#define BRx_DECC_NONE 0x00000000
445#define BRx_DECC_NORMAL 0x00000200
446#define BRx_DECC_RMWPC 0x00000400
447#define BRx_DECC_ECC 0x00000600
448
449#define BRx_MS_GPCM_P 0x00000000
450#define BRx_MS_GPCM_L 0x00000020
451#define BRx_MS_SDRAM_P 0x00000040
452#define BRx_MS_SDRAM_L 0x00000060
453#define BRx_MS_UPMA 0x00000080
454#define BRx_MS_UPMB 0x000000a0
455#define BRx_MS_UPMC 0x000000c0
456
457#define BRx_ATOM_RAWA 0x00000004
458#define BRx_ATOM_WARA 0x00000008
459
460
461
462
463#define ORxS_SDAM_MSK 0xfff00000
464#define ORxS_LSDAM_MSK 0x000f8000
465#define ORxS_BPD_MSK 0x00006000
466#define ORxS_ROWST_MSK 0x00001e00
467#define ORxS_NUMR_MSK 0x000001c0
468#define ORxS_PMSEL 0x00000020
469#define ORxS_IBID 0x00000010
470
471#define ORxS_BPD_2 0x00000000
472#define ORxS_BPD_4 0x00002000
473#define ORxS_BPD_8 0x00004000
474
475
476#define ORxS_ROWST_PBI0_A7 0x00000400
477#define ORxS_ROWST_PBI0_A8 0x00000800
478#define ORxS_ROWST_PBI0_A9 0x00000c00
479#define ORxS_ROWST_PBI0_A10 0x00001000
480#define ORxS_ROWST_PBI0_A11 0x00001400
481#define ORxS_ROWST_PBI0_A12 0x00001800
482#define ORxS_ROWST_PBI0_A13 0x00001c00
483
484
485#define ORxS_ROWST_PBI1_A0 0x00000000
486#define ORxS_ROWST_PBI1_A1 0x00000200
487#define ORxS_ROWST_PBI1_A2 0x00000400
488#define ORxS_ROWST_PBI1_A3 0x00000600
489#define ORxS_ROWST_PBI1_A4 0x00000800
490#define ORxS_ROWST_PBI1_A5 0x00000a00
491#define ORxS_ROWST_PBI1_A6 0x00000c00
492#define ORxS_ROWST_PBI1_A7 0x00000e00
493#define ORxS_ROWST_PBI1_A8 0x00001000
494#define ORxS_ROWST_PBI1_A9 0x00001200
495#define ORxS_ROWST_PBI1_A10 0x00001400
496#define ORxS_ROWST_PBI1_A11 0x00001600
497#define ORxS_ROWST_PBI1_A12 0x00001800
498
499#define ORxS_NUMR_9 0x00000000
500#define ORxS_NUMR_10 0x00000040
501#define ORxS_NUMR_11 0x00000080
502#define ORxS_NUMR_12 0x000000c0
503#define ORxS_NUMR_13 0x00000100
504#define ORxS_NUMR_14 0x00000140
505#define ORxS_NUMR_15 0x00000180
506#define ORxS_NUMR_16 0x000001c0
507
508
509#define ORxS_SIZE_TO_AM(s) ((~((s) - 1)) & 0xffff8000)
510
511
512
513
514#define ORxG_AM_MSK 0xffff8000
515#define ORxG_BCTLD 0x00001000
516#define ORxG_CSNT 0x00000800
517#define ORxG_ACS_MSK 0x00000600
518#define ORxG_SCY_MSK 0x000000f0
519#define ORxG_SETA 0x00000008
520#define ORxG_TRLX 0x00000004
521#define ORxG_EHTR 0x00000002
522
523#define ORxG_ACS_DIV1 0x00000000
524#define ORxG_ACS_DIV4 0x00000400
525#define ORxG_ACS_DIV2 0x00000600
526
527#define ORxG_SCY_0_CLK 0x00000000
528#define ORxG_SCY_1_CLK 0x00000010
529#define ORxG_SCY_2_CLK 0x00000020
530#define ORxG_SCY_3_CLK 0x00000030
531#define ORxG_SCY_4_CLK 0x00000040
532#define ORxG_SCY_5_CLK 0x00000050
533#define ORxG_SCY_6_CLK 0x00000060
534#define ORxG_SCY_7_CLK 0x00000070
535#define ORxG_SCY_8_CLK 0x00000080
536#define ORxG_SCY_9_CLK 0x00000090
537#define ORxG_SCY_10_CLK 0x000000a0
538#define ORxG_SCY_11_CLK 0x000000b0
539#define ORxG_SCY_12_CLK 0x000000c0
540#define ORxG_SCY_13_CLK 0x000000d0
541#define ORxG_SCY_14_CLK 0x000000e0
542#define ORxG_SCY_15_CLK 0x000000f0
543
544
545
546
547#define ORxU_AM_MSK 0xffff8000
548#define ORxU_BCTLD 0x00001000
549#define ORxU_BI 0x00000100
550#define ORxU_EHTR_MSK 0x00000006
551
552#define ORxU_EHTR_NORM 0x00000000
553#define ORxU_EHTR_1IDLE 0x00000002
554#define ORxU_EHTR_4IDLE 0x00000004
555#define ORxU_EHTR_8IDLE 0x00000006
556
557
558
559#define P2SZ_TO_AM(s) ((~((s) - 1)) & 0xffff8000)
560#define MEG_TO_AM(m) P2SZ_TO_AM((m) << 20)
561
562
563
564
565
566#define PSDMR_PBI 0x80000000
567#define PSDMR_RFEN 0x40000000
568#define PSDMR_OP_MSK 0x38000000
569#define PSDMR_SDAM_MSK 0x07000000
570#define PSDMR_BSMA_MSK 0x00e00000
571#define PSDMR_SDA10_MSK 0x001c0000
572#define PSDMR_RFRC_MSK 0x00038000
573#define PSDMR_PRETOACT_MSK 0x00007000
574#define PSDMR_ACTTORW_MSK 0x00000e00
575#define PSDMR_BL 0x00000100
576#define PSDMR_LDOTOPRE_MSK 0x000000c0
577#define PSDMR_WRC_MSK 0x00000030
578#define PSDMR_EAMUX 0x00000008
579#define PSDMR_BUFCMD 0x00000004
580#define PSDMR_CL_MSK 0x00000003
581
582#define PSDMR_OP_NORM 0x00000000
583#define PSDMR_OP_CBRR 0x08000000
584#define PSDMR_OP_SELFR 0x10000000
585#define PSDMR_OP_MRW 0x18000000
586#define PSDMR_OP_PREB 0x20000000
587#define PSDMR_OP_PREA 0x28000000
588#define PSDMR_OP_ACTB 0x30000000
589#define PSDMR_OP_RW 0x38000000
590
591#define PSDMR_SDAM_A13_IS_A5 0x00000000
592#define PSDMR_SDAM_A14_IS_A5 0x01000000
593#define PSDMR_SDAM_A15_IS_A5 0x02000000
594#define PSDMR_SDAM_A16_IS_A5 0x03000000
595#define PSDMR_SDAM_A17_IS_A5 0x04000000
596#define PSDMR_SDAM_A18_IS_A5 0x05000000
597
598#define PSDMR_BSMA_A12_A14 0x00000000
599#define PSDMR_BSMA_A13_A15 0x00200000
600#define PSDMR_BSMA_A14_A16 0x00400000
601#define PSDMR_BSMA_A15_A17 0x00600000
602#define PSDMR_BSMA_A16_A18 0x00800000
603#define PSDMR_BSMA_A17_A19 0x00a00000
604#define PSDMR_BSMA_A18_A20 0x00c00000
605#define PSDMR_BSMA_A19_A21 0x00e00000
606
607
608#define PSDMR_SDA10_PBI0_A12 0x00000000
609#define PSDMR_SDA10_PBI0_A11 0x00040000
610#define PSDMR_SDA10_PBI0_A10 0x00080000
611#define PSDMR_SDA10_PBI0_A9 0x000c0000
612#define PSDMR_SDA10_PBI0_A8 0x00100000
613#define PSDMR_SDA10_PBI0_A7 0x00140000
614#define PSDMR_SDA10_PBI0_A6 0x00180000
615#define PSDMR_SDA10_PBI0_A5 0x001c0000
616
617
618#define PSDMR_SDA10_PBI1_A10 0x00000000
619#define PSDMR_SDA10_PBI1_A9 0x00040000
620#define PSDMR_SDA10_PBI1_A8 0x00080000
621#define PSDMR_SDA10_PBI1_A7 0x000c0000
622#define PSDMR_SDA10_PBI1_A6 0x00100000
623#define PSDMR_SDA10_PBI1_A5 0x00140000
624#define PSDMR_SDA10_PBI1_A4 0x00180000
625#define PSDMR_SDA10_PBI1_A3 0x001c0000
626
627#define PSDMR_RFRC_3_CLK 0x00008000
628#define PSDMR_RFRC_4_CLK 0x00010000
629#define PSDMR_RFRC_5_CLK 0x00018000
630#define PSDMR_RFRC_6_CLK 0x00020000
631#define PSDMR_RFRC_7_CLK 0x00028000
632#define PSDMR_RFRC_8_CLK 0x00030000
633#define PSDMR_RFRC_16_CLK 0x00038000
634
635#define PSDMR_PRETOACT_8W 0x00000000
636#define PSDMR_PRETOACT_1W 0x00001000
637#define PSDMR_PRETOACT_2W 0x00002000
638#define PSDMR_PRETOACT_3W 0x00003000
639#define PSDMR_PRETOACT_4W 0x00004000
640#define PSDMR_PRETOACT_5W 0x00005000
641#define PSDMR_PRETOACT_6W 0x00006000
642#define PSDMR_PRETOACT_7W 0x00007000
643
644#define PSDMR_ACTTORW_8W 0x00000000
645#define PSDMR_ACTTORW_1W 0x00000200
646#define PSDMR_ACTTORW_2W 0x00000400
647#define PSDMR_ACTTORW_3W 0x00000600
648#define PSDMR_ACTTORW_4W 0x00000800
649#define PSDMR_ACTTORW_5W 0x00000a00
650#define PSDMR_ACTTORW_6W 0x00000c00
651#define PSDMR_ACTTORW_7W 0x00000e00
652
653#define PSDMR_LDOTOPRE_0C 0x00000000
654#define PSDMR_LDOTOPRE_1C 0x00000040
655#define PSDMR_LDOTOPRE_2C 0x00000080
656
657#define PSDMR_WRC_4C 0x00000000
658#define PSDMR_WRC_1C 0x00000010
659#define PSDMR_WRC_2C 0x00000020
660#define PSDMR_WRC_3C 0x00000030
661
662#define PSDMR_CL_1 0x00000001
663#define PSDMR_CL_2 0x00000002
664#define PSDMR_CL_3 0x00000003
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681#define MPTPR_PTP_MSK 0xff00
682#define MPTPR_PTP_DIV2 0x2000
683#define MPTPR_PTP_DIV4 0x1000
684#define MPTPR_PTP_DIV8 0x0800
685#define MPTPR_PTP_DIV16 0x0400
686#define MPTPR_PTP_DIV32 0x0200
687#define MPTPR_PTP_DIV64 0x0100
688
689
690
691
692
693#define TGCR1_CAS2 0x80
694#define TGCR1_STP2 0x20
695#define TGCR1_RST2 0x10
696#define TGCR1_GM1 0x08
697#define TGCR1_STP1 0x02
698#define TGCR1_RST1 0x01
699#define TGCR2_CAS4 0x80
700#define TGCR2_STP4 0x20
701#define TGCR2_RST4 0x10
702#define TGCR2_GM2 0x08
703#define TGCR2_STP3 0x02
704#define TGCR2_RST3 0x01
705
706
707
708
709
710#define TMRx_PS_MSK 0xff00
711#define TMRx_CE_MSK 0x00c0
712#define TMRx_OM 0x0020
713#define TMRx_ORI 0x0010
714#define TMRx_FRR 0x0008
715#define TMRx_ICLK_MSK 0x0006
716#define TMRx_GE 0x0001
717
718#define TMRx_CE_INTR_DIS 0x0000
719#define TMRx_CE_RISING 0x0040
720#define TMRx_CE_FALLING 0x0080
721#define TMRx_CE_ANY 0x00c0
722
723#define TMRx_ICLK_IN_CAS 0x0000
724#define TMRx_ICLK_IN_GEN 0x0002
725#define TMRx_ICLK_IN_GEN_DIV16 0x0004
726#define TMRx_ICLK_TIN_PIN 0x0006
727
728
729
730
731
732#define CMXFCR_FC1 0x40000000
733#define CMXFCR_RF1CS_MSK 0x38000000
734#define CMXFCR_TF1CS_MSK 0x07000000
735#define CMXFCR_FC2 0x00400000
736#define CMXFCR_RF2CS_MSK 0x00380000
737#define CMXFCR_TF2CS_MSK 0x00070000
738#define CMXFCR_FC3 0x00004000
739#define CMXFCR_RF3CS_MSK 0x00003800
740#define CMXFCR_TF3CS_MSK 0x00000700
741
742#define CMXFCR_RF1CS_BRG5 0x00000000
743#define CMXFCR_RF1CS_BRG6 0x08000000
744#define CMXFCR_RF1CS_BRG7 0x10000000
745#define CMXFCR_RF1CS_BRG8 0x18000000
746#define CMXFCR_RF1CS_CLK9 0x20000000
747#define CMXFCR_RF1CS_CLK10 0x28000000
748#define CMXFCR_RF1CS_CLK11 0x30000000
749#define CMXFCR_RF1CS_CLK12 0x38000000
750
751#define CMXFCR_TF1CS_BRG5 0x00000000
752#define CMXFCR_TF1CS_BRG6 0x01000000
753#define CMXFCR_TF1CS_BRG7 0x02000000
754#define CMXFCR_TF1CS_BRG8 0x03000000
755#define CMXFCR_TF1CS_CLK9 0x04000000
756#define CMXFCR_TF1CS_CLK10 0x05000000
757#define CMXFCR_TF1CS_CLK11 0x06000000
758#define CMXFCR_TF1CS_CLK12 0x07000000
759
760#define CMXFCR_RF2CS_BRG5 0x00000000
761#define CMXFCR_RF2CS_BRG6 0x00080000
762#define CMXFCR_RF2CS_BRG7 0x00100000
763#define CMXFCR_RF2CS_BRG8 0x00180000
764#define CMXFCR_RF2CS_CLK13 0x00200000
765#define CMXFCR_RF2CS_CLK14 0x00280000
766#define CMXFCR_RF2CS_CLK15 0x00300000
767#define CMXFCR_RF2CS_CLK16 0x00380000
768
769#define CMXFCR_TF2CS_BRG5 0x00000000
770#define CMXFCR_TF2CS_BRG6 0x00010000
771#define CMXFCR_TF2CS_BRG7 0x00020000
772#define CMXFCR_TF2CS_BRG8 0x00030000
773#define CMXFCR_TF2CS_CLK13 0x00040000
774#define CMXFCR_TF2CS_CLK14 0x00050000
775#define CMXFCR_TF2CS_CLK15 0x00060000
776#define CMXFCR_TF2CS_CLK16 0x00070000
777
778#define CMXFCR_RF3CS_BRG5 0x00000000
779#define CMXFCR_RF3CS_BRG6 0x00000800
780#define CMXFCR_RF3CS_BRG7 0x00001000
781#define CMXFCR_RF3CS_BRG8 0x00001800
782#define CMXFCR_RF3CS_CLK13 0x00002000
783#define CMXFCR_RF3CS_CLK14 0x00002800
784#define CMXFCR_RF3CS_CLK15 0x00003000
785#define CMXFCR_RF3CS_CLK16 0x00003800
786
787#define CMXFCR_TF3CS_BRG5 0x00000000
788#define CMXFCR_TF3CS_BRG6 0x00000100
789#define CMXFCR_TF3CS_BRG7 0x00000200
790#define CMXFCR_TF3CS_BRG8 0x00000300
791#define CMXFCR_TF3CS_CLK13 0x00000400
792#define CMXFCR_TF3CS_CLK14 0x00000500
793#define CMXFCR_TF3CS_CLK15 0x00000600
794#define CMXFCR_TF3CS_CLK16 0x00000700
795
796
797
798
799#define CMXSCR_GR1 0x80000000
800#define CMXSCR_SC1 0x40000000
801#define CMXSCR_RS1CS_MSK 0x38000000
802#define CMXSCR_TS1CS_MSK 0x07000000
803#define CMXSCR_GR2 0x00800000
804#define CMXSCR_SC2 0x00400000
805#define CMXSCR_RS2CS_MSK 0x00380000
806#define CMXSCR_TS2CS_MSK 0x00070000
807#define CMXSCR_GR3 0x00008000
808#define CMXSCR_SC3 0x00004000
809#define CMXSCR_RS3CS_MSK 0x00003800
810#define CMXSCR_TS3CS_MSK 0x00000700
811#define CMXSCR_GR4 0x00000080
812#define CMXSCR_SC4 0x00000040
813#define CMXSCR_RS4CS_MSK 0x00000038
814#define CMXSCR_TS4CS_MSK 0x00000007
815
816#define CMXSCR_RS1CS_BRG1 0x00000000
817#define CMXSCR_RS1CS_BRG2 0x08000000
818#define CMXSCR_RS1CS_BRG3 0x10000000
819#define CMXSCR_RS1CS_BRG4 0x18000000
820#define CMXSCR_RS1CS_CLK11 0x20000000
821#define CMXSCR_RS1CS_CLK12 0x28000000
822#define CMXSCR_RS1CS_CLK3 0x30000000
823#define CMXSCR_RS1CS_CLK4 0x38000000
824
825#define CMXSCR_TS1CS_BRG1 0x00000000
826#define CMXSCR_TS1CS_BRG2 0x01000000
827#define CMXSCR_TS1CS_BRG3 0x02000000
828#define CMXSCR_TS1CS_BRG4 0x03000000
829#define CMXSCR_TS1CS_CLK11 0x04000000
830#define CMXSCR_TS1CS_CLK12 0x05000000
831#define CMXSCR_TS1CS_CLK3 0x06000000
832#define CMXSCR_TS1CS_CLK4 0x07000000
833
834#define CMXSCR_RS2CS_BRG1 0x00000000
835#define CMXSCR_RS2CS_BRG2 0x00080000
836#define CMXSCR_RS2CS_BRG3 0x00100000
837#define CMXSCR_RS2CS_BRG4 0x00180000
838#define CMXSCR_RS2CS_CLK11 0x00200000
839#define CMXSCR_RS2CS_CLK12 0x00280000
840#define CMXSCR_RS2CS_CLK3 0x00300000
841#define CMXSCR_RS2CS_CLK4 0x00380000
842
843#define CMXSCR_TS2CS_BRG1 0x00000000
844#define CMXSCR_TS2CS_BRG2 0x00010000
845#define CMXSCR_TS2CS_BRG3 0x00020000
846#define CMXSCR_TS2CS_BRG4 0x00030000
847#define CMXSCR_TS2CS_CLK11 0x00040000
848#define CMXSCR_TS2CS_CLK12 0x00050000
849#define CMXSCR_TS2CS_CLK3 0x00060000
850#define CMXSCR_TS2CS_CLK4 0x00070000
851
852#define CMXSCR_RS3CS_BRG1 0x00000000
853#define CMXSCR_RS3CS_BRG2 0x00000800
854#define CMXSCR_RS3CS_BRG3 0x00001000
855#define CMXSCR_RS3CS_BRG4 0x00001800
856#define CMXSCR_RS3CS_CLK5 0x00002000
857#define CMXSCR_RS3CS_CLK6 0x00002800
858#define CMXSCR_RS3CS_CLK7 0x00003000
859#define CMXSCR_RS3CS_CLK8 0x00003800
860
861#define CMXSCR_TS3CS_BRG1 0x00000000
862#define CMXSCR_TS3CS_BRG2 0x00000100
863#define CMXSCR_TS3CS_BRG3 0x00000200
864#define CMXSCR_TS3CS_BRG4 0x00000300
865#define CMXSCR_TS3CS_CLK5 0x00000400
866#define CMXSCR_TS3CS_CLK6 0x00000500
867#define CMXSCR_TS3CS_CLK7 0x00000600
868#define CMXSCR_TS3CS_CLK8 0x00000700
869
870#define CMXSCR_RS4CS_BRG1 0x00000000
871#define CMXSCR_RS4CS_BRG2 0x00000008
872#define CMXSCR_RS4CS_BRG3 0x00000010
873#define CMXSCR_RS4CS_BRG4 0x00000018
874#define CMXSCR_RS4CS_CLK5 0x00000020
875#define CMXSCR_RS4CS_CLK6 0x00000028
876#define CMXSCR_RS4CS_CLK7 0x00000030
877#define CMXSCR_RS4CS_CLK8 0x00000038
878
879#define CMXSCR_TS4CS_BRG1 0x00000000
880#define CMXSCR_TS4CS_BRG2 0x00000001
881#define CMXSCR_TS4CS_BRG3 0x00000002
882#define CMXSCR_TS4CS_BRG4 0x00000003
883#define CMXSCR_TS4CS_CLK5 0x00000004
884#define CMXSCR_TS4CS_CLK6 0x00000005
885#define CMXSCR_TS4CS_CLK7 0x00000006
886#define CMXSCR_TS4CS_CLK8 0x00000007
887
888
889
890
891#define CMXSMR_SMC1 0x80
892#define CMXSMR_SMC1CS_MSK 0x30
893#define CMXSMR_SMC2 0x08
894#define CMXSMR_SMC2CS_MSK 0x03
895
896#define CMXSMR_SMC1CS_BRG1 0x00
897#define CMXSMR_SMC1CS_BRG7 0x10
898#define CMXSMR_SMC1CS_CLK7 0x20
899#define CMXSMR_SMC1CS_CLK9 0x30
900
901#define CMXSMR_SMC2CS_BRG2 0x00
902#define CMXSMR_SMC2CS_BRG8 0x01
903#define CMXSMR_SMC2CS_CLK19 0x02
904#define CMXSMR_SMC2CS_CLK20 0x03
905
906
907
908
909
910#define UPMA 1
911#define UPMB 2
912#define UPMC 3
913
914#if !defined(__ASSEMBLY__) && defined(CONFIG_WATCHDOG)
915extern __inline__ void
916reset_8260_watchdog(volatile immap_t *immr)
917{
918 immr->im_siu_conf.sc_swsr = 0x556c;
919 immr->im_siu_conf.sc_swsr = 0xaa39;
920}
921#endif
922
923#endif
924