LXR uboot/arch/arm/cpu/armv7/omap4/hw

   1/*
   2 *
   3 * HW data initialization for OMAP4
   4 *
   5 * (C) Copyright 2013
   6 * Texas Instruments, <www.ti.com>
   7 *
   8 * Sricharan R <r.sricharan@ti.com>
   9 *
  10 * See file CREDITS for list of people who contributed to this
  11 * project.
  12 *
  13 * This program is free software; you can redistribute it and/or
  14 * modify it under the terms of the GNU General Public License as
  15 * published by the Free Software Foundation; either version 2 of
  16 * the License, or (at your option) any later version.
  17 *
  18 * This program is distributed in the hope that it will be useful,
  19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21 * GNU General Public License for more details.
  22 *
  23 * You should have received a copy of the GNU General Public License
  24 * along with this program; if not, write to the Free Software
  25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26 * MA 02111-1307 USA
  27 */
  28#include <common.h>
  29#include <asm/arch/omap.h>
  30#include <asm/arch/sys_proto.h>
  31#include <asm/omap_common.h>
  32#include <asm/arch/clocks.h>
  33#include <asm/omap_gpio.h>
  34#include <asm/io.h>
  35
  36struct prcm_regs const **prcm =
  37                        (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
  38struct dplls const **dplls_data =
  39                        (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
  40struct vcores_data const **omap_vcores =
  41                (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
  42struct omap_sys_ctrl_regs const **ctrl =
  43        (struct omap_sys_ctrl_regs const **)OMAP4_SRAM_SCRATCH_SYS_CTRL;
  44
  45/*
  46 * The M & N values in the following tables are created using the
  47 * following tool:
  48 * tools/omap/clocks_get_m_n.c
  49 * Please use this tool for creating the table for any new frequency.
  50 */
  51
  52/*
  53 * dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF
  54 * OMAP4460 OPP_NOM frequency
  55 */
  56static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = {
  57        {175, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 12 MHz   */
  58        {700, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
  59        {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 16.8 MHz */
  60        {401, 10, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 19.2 MHz */
  61        {350, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 26 MHz   */
  62        {700, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
  63        {638, 34, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}        /* 38.4 MHz */
  64};
  65
  66/*
  67 * dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430)
  68 * OMAP4430 OPP_TURBO frequency
  69 */
  70static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = {
  71        {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 12 MHz   */
  72        {800, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
  73        {619, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 16.8 MHz */
  74        {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 19.2 MHz */
  75        {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 26 MHz   */
  76        {800, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
  77        {125, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}         /* 38.4 MHz */
  78};
  79
  80/*
  81 * dpll locked at 1200 MHz - MPU clk at 600 MHz
  82 * OMAP4430 OPP_NOM frequency
  83 */
  84static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {
  85        {50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 12 MHz   */
  86        {600, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
  87        {250, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 16.8 MHz */
  88        {125, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 19.2 MHz */
  89        {300, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 26 MHz   */
  90        {200, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 27 MHz   */
  91        {125, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}         /* 38.4 MHz */
  92};
  93
  94/* OMAP4460 OPP_NOM frequency */
  95static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {
  96        {200, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},     /* 12 MHz   */
  97        {800, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},    /* 13 MHz   */
  98        {619, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},    /* 16.8 MHz */
  99        {125, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},     /* 19.2 MHz */
 100        {400, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},    /* 26 MHz   */
 101        {800, 26, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},    /* 27 MHz   */
 102        {125, 5, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}      /* 38.4 MHz */
 103};
 104
 105/* OMAP4430 ES1 OPP_NOM frequency */
 106static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = {
 107        {127, 1, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},     /* 12 MHz   */
 108        {762, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},    /* 13 MHz   */
 109        {635, 13, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},    /* 16.8 MHz */
 110        {635, 15, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},    /* 19.2 MHz */
 111        {381, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},    /* 26 MHz   */
 112        {254, 8, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},     /* 27 MHz   */
 113        {496, 24, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}     /* 38.4 MHz */
 114};
 115
 116/* OMAP4430 ES2.X OPP_NOM frequency */
 117static const struct dpll_params
 118                core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = {
 119        {200, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1},     /* 12 MHz   */
 120        {800, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1},    /* 13 MHz   */
 121        {619, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1},    /* 16.8 MHz */
 122        {125, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1},     /* 19.2 MHz */
 123        {400, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1},    /* 26 MHz   */
 124        {800, 26, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1},    /* 27 MHz   */
 125        {125, 5, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}      /* 38.4 MHz */
 126};
 127
 128static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = {
 129        {64, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1},     /* 12 MHz   */
 130        {768, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1},   /* 13 MHz   */
 131        {320, 6, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1},    /* 16.8 MHz */
 132        {40, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1},     /* 19.2 MHz */
 133        {384, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1},   /* 26 MHz   */
 134        {256, 8, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1},    /* 27 MHz   */
 135        {20, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}      /* 38.4 MHz */
 136};
 137
 138static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {
 139        {931, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1},        /* 12 MHz   */
 140        {931, 12, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1},        /* 13 MHz   */
 141        {665, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1},        /* 16.8 MHz */
 142        {727, 14, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1},        /* 19.2 MHz */
 143        {931, 25, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1},        /* 26 MHz   */
 144        {931, 26, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1},        /* 27 MHz   */
 145        {291, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}         /* 38.4 MHz */
 146};
 147
 148/* ABE M & N values with sys_clk as source */
 149static const struct dpll_params
 150                abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
 151        {49, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},  /* 12 MHz   */
 152        {68, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},  /* 13 MHz   */
 153        {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},  /* 16.8 MHz */
 154        {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},  /* 19.2 MHz */
 155        {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},  /* 26 MHz   */
 156        {29, 7, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},  /* 27 MHz   */
 157        {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}  /* 38.4 MHz */
 158};
 159
 160/* ABE M & N values with 32K clock as source */
 161static const struct dpll_params abe_dpll_params_32k_196608khz = {
 162        750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
 163};
 164
 165static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
 166        {80, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 12 MHz   */
 167        {960, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
 168        {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 16.8 MHz */
 169        {50, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 19.2 MHz */
 170        {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 26 MHz   */
 171        {320, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 27 MHz   */
 172        {25, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}          /* 38.4 MHz */
 173};
 174
 175struct dplls omap4430_dplls_es1 = {
 176        .mpu = mpu_dpll_params_1200mhz,
 177        .core = core_dpll_params_es1_1524mhz,
 178        .per = per_dpll_params_1536mhz,
 179        .iva = iva_dpll_params_1862mhz,
 180#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
 181        .abe = abe_dpll_params_sysclk_196608khz,
 182#else
 183        .abe = &abe_dpll_params_32k_196608khz,
 184#endif
 185        .usb = usb_dpll_params_1920mhz,
 186        .ddr = NULL
 187};
 188
 189struct dplls omap4430_dplls = {
 190        .mpu = mpu_dpll_params_1200mhz,
 191        .core = core_dpll_params_1600mhz,
 192        .per = per_dpll_params_1536mhz,
 193        .iva = iva_dpll_params_1862mhz,
 194#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
 195        .abe = abe_dpll_params_sysclk_196608khz,
 196#else
 197        .abe = &abe_dpll_params_32k_196608khz,
 198#endif
 199        .usb = usb_dpll_params_1920mhz,
 200        .ddr = NULL
 201};
 202
 203struct dplls omap4460_dplls = {
 204        .mpu = mpu_dpll_params_1400mhz,
 205        .core = core_dpll_params_1600mhz,
 206        .per = per_dpll_params_1536mhz,
 207        .iva = iva_dpll_params_1862mhz,
 208#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
 209        .abe = abe_dpll_params_sysclk_196608khz,
 210#else
 211        .abe = &abe_dpll_params_32k_196608khz,
 212#endif
 213        .usb = usb_dpll_params_1920mhz,
 214        .ddr = NULL
 215};
 216
 217struct pmic_data twl6030_4430es1 = {
 218        .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV,
 219        .step = 12660, /* 12.66 mV represented in uV */
 220        /* The code starts at 1 not 0 */
 221        .start_code = 1,
 222};
 223
 224struct pmic_data twl6030 = {
 225        .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV,
 226        .step = 12660, /* 12.66 mV represented in uV */
 227        /* The code starts at 1 not 0 */
 228        .start_code = 1,
 229};
 230
 231struct pmic_data tps62361 = {
 232        .base_offset = TPS62361_BASE_VOLT_MV,
 233        .step = 10000, /* 10 mV represented in uV */
 234        .start_code = 0,
 235        .gpio = TPS62361_VSEL0_GPIO,
 236        .gpio_en = 1
 237};
 238
 239struct vcores_data omap4430_volts_es1 = {
 240        .mpu.value = 1325,
 241        .mpu.addr = SMPS_REG_ADDR_VCORE1,
 242        .mpu.pmic = &twl6030_4430es1,
 243
 244        .core.value = 1200,
 245        .core.addr = SMPS_REG_ADDR_VCORE3,
 246        .core.pmic = &twl6030_4430es1,
 247
 248        .mm.value = 1200,
 249        .mm.addr = SMPS_REG_ADDR_VCORE2,
 250        .mm.pmic = &twl6030_4430es1,
 251};
 252
 253struct vcores_data omap4430_volts = {
 254        .mpu.value = 1325,
 255        .mpu.addr = SMPS_REG_ADDR_VCORE1,
 256        .mpu.pmic = &twl6030,
 257
 258        .core.value = 1200,
 259        .core.addr = SMPS_REG_ADDR_VCORE3,
 260        .core.pmic = &twl6030,
 261
 262        .mm.value = 1200,
 263        .mm.addr = SMPS_REG_ADDR_VCORE2,
 264        .mm.pmic = &twl6030,
 265};
 266
 267struct vcores_data omap4460_volts = {
 268        .mpu.value = 1203,
 269        .mpu.addr = TPS62361_REG_ADDR_SET1,
 270        .mpu.pmic = &tps62361,
 271
 272        .core.value = 1200,
 273        .core.addr = SMPS_REG_ADDR_VCORE1,
 274        .core.pmic = &twl6030,
 275
 276        .mm.value = 1200,
 277        .mm.addr = SMPS_REG_ADDR_VCORE2,
 278        .mm.pmic = &twl6030,
 279};
 280
 281/*
 282 * Enable essential clock domains, modules and
 283 * do some additional special settings needed
 284 */
 285void enable_basic_clocks(void)
 286{
 287        u32 const clk_domains_essential[] = {
 288                (*prcm)->cm_l4per_clkstctrl,
 289                (*prcm)->cm_l3init_clkstctrl,
 290                (*prcm)->cm_memif_clkstctrl,
 291                (*prcm)->cm_l4cfg_clkstctrl,
 292                0
 293        };
 294
 295        u32 const clk_modules_hw_auto_essential[] = {
 296                (*prcm)->cm_l3_gpmc_clkctrl,
 297                (*prcm)->cm_memif_emif_1_clkctrl,
 298                (*prcm)->cm_memif_emif_2_clkctrl,
 299                (*prcm)->cm_l4cfg_l4_cfg_clkctrl,
 300                (*prcm)->cm_wkup_gpio1_clkctrl,
 301                (*prcm)->cm_l4per_gpio2_clkctrl,
 302                (*prcm)->cm_l4per_gpio3_clkctrl,
 303                (*prcm)->cm_l4per_gpio4_clkctrl,
 304                (*prcm)->cm_l4per_gpio5_clkctrl,
 305                (*prcm)->cm_l4per_gpio6_clkctrl,
 306                0
 307        };
 308
 309        u32 const clk_modules_explicit_en_essential[] = {
 310                (*prcm)->cm_wkup_gptimer1_clkctrl,
 311                (*prcm)->cm_l3init_hsmmc1_clkctrl,
 312                (*prcm)->cm_l3init_hsmmc2_clkctrl,
 313                (*prcm)->cm_l4per_gptimer2_clkctrl,
 314                (*prcm)->cm_wkup_wdtimer2_clkctrl,
 315                (*prcm)->cm_l4per_uart3_clkctrl,
 316                0
 317        };
 318
 319        /* Enable optional additional functional clock for GPIO4 */
 320        setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
 321                        GPIO4_CLKCTRL_OPTFCLKEN_MASK);
 322
 323        /* Enable 96 MHz clock for MMC1 & MMC2 */
 324        setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
 325                        HSMMC_CLKCTRL_CLKSEL_MASK);
 326        setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
 327                        HSMMC_CLKCTRL_CLKSEL_MASK);
 328
 329        /* Select 32KHz clock as the source of GPTIMER1 */
 330        setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
 331                        GPTIMER1_CLKCTRL_CLKSEL_MASK);
 332
 333        /* Enable optional 48M functional clock for USB  PHY */
 334        setbits_le32((*prcm)->cm_l3init_usbphy_clkctrl,
 335                        USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK);
 336
 337        do_enable_clocks(clk_domains_essential,
 338                         clk_modules_hw_auto_essential,
 339                         clk_modules_explicit_en_essential,
 340                         1);
 341}
 342
 343void enable_basic_uboot_clocks(void)
 344{
 345        u32 const clk_domains_essential[] = {
 346                0
 347        };
 348
 349        u32 const clk_modules_hw_auto_essential[] = {
 350                (*prcm)->cm_l3init_hsusbotg_clkctrl,
 351                (*prcm)->cm_l3init_usbphy_clkctrl,
 352                (*prcm)->cm_l3init_usbphy_clkctrl,
 353                (*prcm)->cm_clksel_usb_60mhz,
 354                (*prcm)->cm_l3init_hsusbtll_clkctrl,
 355                0
 356        };
 357
 358        u32 const clk_modules_explicit_en_essential[] = {
 359                (*prcm)->cm_l4per_mcspi1_clkctrl,
 360                (*prcm)->cm_l4per_i2c1_clkctrl,
 361                (*prcm)->cm_l4per_i2c2_clkctrl,
 362                (*prcm)->cm_l4per_i2c3_clkctrl,
 363                (*prcm)->cm_l4per_i2c4_clkctrl,
 364                (*prcm)->cm_l3init_hsusbhost_clkctrl,
 365                0
 366        };
 367
 368        do_enable_clocks(clk_domains_essential,
 369                         clk_modules_hw_auto_essential,
 370                         clk_modules_explicit_en_essential,
 371                         1);
 372}
 373
 374/*
 375 * Enable non-essential clock domains, modules and
 376 * do some additional special settings needed
 377 */
 378void enable_non_essential_clocks(void)
 379{
 380        u32 const clk_domains_non_essential[] = {
 381                (*prcm)->cm_mpu_m3_clkstctrl,
 382                (*prcm)->cm_ivahd_clkstctrl,
 383                (*prcm)->cm_dsp_clkstctrl,
 384                (*prcm)->cm_dss_clkstctrl,
 385                (*prcm)->cm_sgx_clkstctrl,
 386                (*prcm)->cm1_abe_clkstctrl,
 387                (*prcm)->cm_c2c_clkstctrl,
 388                (*prcm)->cm_cam_clkstctrl,
 389                (*prcm)->cm_dss_clkstctrl,
 390                (*prcm)->cm_sdma_clkstctrl,
 391                0
 392        };
 393
 394        u32 const clk_modules_hw_auto_non_essential[] = {
 395                (*prcm)->cm_l3instr_l3_3_clkctrl,
 396                (*prcm)->cm_l3instr_l3_instr_clkctrl,
 397                (*prcm)->cm_l3instr_intrconn_wp1_clkctrl,
 398                (*prcm)->cm_l3init_hsi_clkctrl,
 399                0
 400        };
 401
 402        u32 const clk_modules_explicit_en_non_essential[] = {
 403                (*prcm)->cm1_abe_aess_clkctrl,
 404                (*prcm)->cm1_abe_pdm_clkctrl,
 405                (*prcm)->cm1_abe_dmic_clkctrl,
 406                (*prcm)->cm1_abe_mcasp_clkctrl,
 407                (*prcm)->cm1_abe_mcbsp1_clkctrl,
 408                (*prcm)->cm1_abe_mcbsp2_clkctrl,
 409                (*prcm)->cm1_abe_mcbsp3_clkctrl,
 410                (*prcm)->cm1_abe_slimbus_clkctrl,
 411                (*prcm)->cm1_abe_timer5_clkctrl,
 412                (*prcm)->cm1_abe_timer6_clkctrl,
 413                (*prcm)->cm1_abe_timer7_clkctrl,
 414                (*prcm)->cm1_abe_timer8_clkctrl,
 415                (*prcm)->cm1_abe_wdt3_clkctrl,
 416                (*prcm)->cm_l4per_gptimer9_clkctrl,
 417                (*prcm)->cm_l4per_gptimer10_clkctrl,
 418                (*prcm)->cm_l4per_gptimer11_clkctrl,
 419                (*prcm)->cm_l4per_gptimer3_clkctrl,
 420                (*prcm)->cm_l4per_gptimer4_clkctrl,
 421                (*prcm)->cm_l4per_hdq1w_clkctrl,
 422                (*prcm)->cm_l4per_mcbsp4_clkctrl,
 423                (*prcm)->cm_l4per_mcspi2_clkctrl,
 424                (*prcm)->cm_l4per_mcspi3_clkctrl,
 425                (*prcm)->cm_l4per_mcspi4_clkctrl,
 426                (*prcm)->cm_l4per_mmcsd3_clkctrl,
 427                (*prcm)->cm_l4per_mmcsd4_clkctrl,
 428                (*prcm)->cm_l4per_mmcsd5_clkctrl,
 429                (*prcm)->cm_l4per_uart1_clkctrl,
 430                (*prcm)->cm_l4per_uart2_clkctrl,
 431                (*prcm)->cm_l4per_uart4_clkctrl,
 432                (*prcm)->cm_wkup_keyboard_clkctrl,
 433                (*prcm)->cm_wkup_wdtimer2_clkctrl,
 434                (*prcm)->cm_cam_iss_clkctrl,
 435                (*prcm)->cm_cam_fdif_clkctrl,
 436                (*prcm)->cm_dss_dss_clkctrl,
 437                (*prcm)->cm_sgx_sgx_clkctrl,
 438                0
 439        };
 440
 441        /* Enable optional functional clock for ISS */
 442        setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
 443
 444        /* Enable all optional functional clocks of DSS */
 445        setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
 446
 447        do_enable_clocks(clk_domains_non_essential,
 448                         clk_modules_hw_auto_non_essential,
 449                         clk_modules_explicit_en_non_essential,
 450                         0);
 451
 452        /* Put camera module in no sleep mode */
 453        clrsetbits_le32((*prcm)->cm_cam_clkstctrl,
 454                        MODULE_CLKCTRL_MODULEMODE_MASK,
 455                        CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
 456                        MODULE_CLKCTRL_MODULEMODE_SHIFT);
 457}
 458
 459void hw_data_init(void)
 460{
 461        u32 omap_rev = omap_revision();
 462
 463        (*prcm) = &omap4_prcm;
 464
 465        switch (omap_rev) {
 466
 467        case OMAP4430_ES1_0:
 468        *dplls_data = &omap4430_dplls_es1;
 469        *omap_vcores = &omap4430_volts_es1;
 470        break;
 471
 472        case OMAP4430_ES2_0:
 473        case OMAP4430_ES2_1:
 474        case OMAP4430_ES2_2:
 475        case OMAP4430_ES2_3:
 476        *dplls_data = &omap4430_dplls;
 477        *omap_vcores = &omap4430_volts;
 478        break;
 479
 480        case OMAP4460_ES1_0:
 481        case OMAP4460_ES1_1:
 482        *dplls_data = &omap4460_dplls;
 483        *omap_vcores = &omap4460_volts;
 484        break;
 485
 486        default:
 487                printf("\n INVALID OMAP REVISION ");
 488        }
 489
 490        *ctrl = &omap4_ctrl;
 491}
 492