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6#ifndef __BFIN_DEF_ADSP_BF538_proc__
7#define __BFIN_DEF_ADSP_BF538_proc__
8
9#include "../mach-common/ADSP-EDN-core_def.h"
10
11#define PLL_CTL 0xFFC00000
12#define PLL_DIV 0xFFC00004
13#define VR_CTL 0xFFC00008
14#define PLL_STAT 0xFFC0000C
15#define PLL_LOCKCNT 0xFFC00010
16#define CHIPID 0xFFC00014
17#define SWRST 0xFFC00100
18#define SYSCR 0xFFC00104
19#define SIC_RVECT 0xFFC00108
20#define SIC_IMASK0 0xFFC0010C
21#define SIC_IMASK1 0xFFC00128
22#define SIC_ISR0 0xFFC00120
23#define SIC_ISR1 0xFFC0012C
24#define SIC_IWR0 0xFFC00124
25#define SIC_IWR1 0xFFC00130
26#define SIC_IAR0 0xFFC00110
27#define SIC_IAR1 0xFFC00114
28#define SIC_IAR2 0xFFC00118
29#define SIC_IAR3 0xFFC0011C
30#define SIC_IAR4 0xFFC00134
31#define SIC_IAR5 0xFFC00138
32#define SIC_IAR6 0xFFC0013C
33#define WDOG_CTL 0xFFC00200
34#define WDOG_CNT 0xFFC00204
35#define WDOG_STAT 0xFFC00208
36#define RTC_STAT 0xFFC00300
37#define RTC_ICTL 0xFFC00304
38#define RTC_ISTAT 0xFFC00308
39#define RTC_SWCNT 0xFFC0030C
40#define RTC_ALARM 0xFFC00310
41#define RTC_PREN 0xFFC00314
42#define UART0_THR 0xFFC00400
43#define UART0_RBR 0xFFC00400
44#define UART0_DLL 0xFFC00400
45#define UART0_DLH 0xFFC00404
46#define UART0_IER 0xFFC00404
47#define UART0_IIR 0xFFC00408
48#define UART0_LCR 0xFFC0040C
49#define UART0_MCR 0xFFC00410
50#define UART0_LSR 0xFFC00414
51#define UART0_SCR 0xFFC0041C
52#define UART0_GCTL 0xFFC00424
53#define UART1_THR 0xFFC02000
54#define UART1_RBR 0xFFC02000
55#define UART1_DLL 0xFFC02000
56#define UART1_DLH 0xFFC02004
57#define UART1_IER 0xFFC02004
58#define UART1_IIR 0xFFC02008
59#define UART1_LCR 0xFFC0200C
60#define UART1_MCR 0xFFC02010
61#define UART1_LSR 0xFFC02014
62#define UART1_SCR 0xFFC0201C
63#define UART1_GCTL 0xFFC02024
64#define UART2_THR 0xFFC02100
65#define UART2_RBR 0xFFC02100
66#define UART2_DLL 0xFFC02100
67#define UART2_DLH 0xFFC02104
68#define UART2_IER 0xFFC02104
69#define UART2_IIR 0xFFC02108
70#define UART2_LCR 0xFFC0210C
71#define UART2_MCR 0xFFC02110
72#define UART2_LSR 0xFFC02114
73#define UART2_SCR 0xFFC0211C
74#define UART2_GCTL 0xFFC02124
75#define SPI0_CTL 0xFFC00500
76#define SPI0_FLG 0xFFC00504
77#define SPI0_STAT 0xFFC00508
78#define SPI0_TDBR 0xFFC0050C
79#define SPI0_RDBR 0xFFC00510
80#define SPI0_BAUD 0xFFC00514
81#define SPI0_SHADOW 0xFFC00518
82#define SPI1_CTL 0xFFC02300
83#define SPI1_FLG 0xFFC02304
84#define SPI1_STAT 0xFFC02308
85#define SPI1_TDBR 0xFFC0230C
86#define SPI1_RDBR 0xFFC02310
87#define SPI1_BAUD 0xFFC02314
88#define SPI1_SHADOW 0xFFC02318
89#define SPI2_CTL 0xFFC02400
90#define SPI2_FLG 0xFFC02404
91#define SPI2_STAT 0xFFC02408
92#define SPI2_TDBR 0xFFC0240C
93#define SPI2_RDBR 0xFFC02410
94#define SPI2_BAUD 0xFFC02414
95#define SPI2_SHADOW 0xFFC02418
96#define TIMER0_CONFIG 0xFFC00600
97#define TIMER0_COUNTER 0xFFC00604
98#define TIMER0_PERIOD 0xFFC00608
99#define TIMER0_WIDTH 0xFFC0060C
100#define TIMER1_CONFIG 0xFFC00610
101#define TIMER1_COUNTER 0xFFC00614
102#define TIMER1_PERIOD 0xFFC00618
103#define TIMER1_WIDTH 0xFFC0061C
104#define TIMER2_CONFIG 0xFFC00620
105#define TIMER2_COUNTER 0xFFC00624
106#define TIMER2_PERIOD 0xFFC00628
107#define TIMER2_WIDTH 0xFFC0062C
108#define TIMER_ENABLE 0xFFC00640
109#define TIMER_DISABLE 0xFFC00644
110#define TIMER_STATUS 0xFFC00648
111#define SPORT0_TCR1 0xFFC00800
112#define SPORT0_TCR2 0xFFC00804
113#define SPORT0_TCLKDIV 0xFFC00808
114#define SPORT0_TFSDIV 0xFFC0080C
115#define SPORT0_TX 0xFFC00810
116#define SPORT0_RX 0xFFC00818
117#define SPORT0_RCR1 0xFFC00820
118#define SPORT0_RCR2 0xFFC00824
119#define SPORT0_RCLKDIV 0xFFC00828
120#define SPORT0_RFSDIV 0xFFC0082C
121#define SPORT0_STAT 0xFFC00830
122#define SPORT0_CHNL 0xFFC00834
123#define SPORT0_MCMC1 0xFFC00838
124#define SPORT0_MCMC2 0xFFC0083C
125#define SPORT0_MTCS0 0xFFC00840
126#define SPORT0_MTCS1 0xFFC00844
127#define SPORT0_MTCS2 0xFFC00848
128#define SPORT0_MTCS3 0xFFC0084C
129#define SPORT0_MRCS0 0xFFC00850
130#define SPORT0_MRCS1 0xFFC00854
131#define SPORT0_MRCS2 0xFFC00858
132#define SPORT0_MRCS3 0xFFC0085C
133#define SPORT1_TCR1 0xFFC00900
134#define SPORT1_TCR2 0xFFC00904
135#define SPORT1_TCLKDIV 0xFFC00908
136#define SPORT1_TFSDIV 0xFFC0090C
137#define SPORT1_TX 0xFFC00910
138#define SPORT1_RX 0xFFC00918
139#define SPORT1_RCR1 0xFFC00920
140#define SPORT1_RCR2 0xFFC00924
141#define SPORT1_RCLKDIV 0xFFC00928
142#define SPORT1_RFSDIV 0xFFC0092C
143#define SPORT1_STAT 0xFFC00930
144#define SPORT1_CHNL 0xFFC00934
145#define SPORT1_MCMC1 0xFFC00938
146#define SPORT1_MCMC2 0xFFC0093C
147#define SPORT1_MTCS0 0xFFC00940
148#define SPORT1_MTCS1 0xFFC00944
149#define SPORT1_MTCS2 0xFFC00948
150#define SPORT1_MTCS3 0xFFC0094C
151#define SPORT1_MRCS0 0xFFC00950
152#define SPORT1_MRCS1 0xFFC00954
153#define SPORT1_MRCS2 0xFFC00958
154#define SPORT1_MRCS3 0xFFC0095C
155#define SPORT2_TCR1 0xFFC02500
156#define SPORT2_TCR2 0xFFC02504
157#define SPORT2_TCLKDIV 0xFFC02508
158#define SPORT2_TFSDIV 0xFFC0250C
159#define SPORT2_TX 0xFFC02510
160#define SPORT2_RX 0xFFC02518
161#define SPORT2_RCR1 0xFFC02520
162#define SPORT2_RCR2 0xFFC02524
163#define SPORT2_RCLKDIV 0xFFC02528
164#define SPORT2_RFSDIV 0xFFC0252C
165#define SPORT2_STAT 0xFFC02530
166#define SPORT2_CHNL 0xFFC02534
167#define SPORT2_MCMC1 0xFFC02538
168#define SPORT2_MCMC2 0xFFC0253C
169#define SPORT2_MTCS0 0xFFC02540
170#define SPORT2_MTCS1 0xFFC02544
171#define SPORT2_MTCS2 0xFFC02548
172#define SPORT2_MTCS3 0xFFC0254C
173#define SPORT2_MRCS0 0xFFC02550
174#define SPORT2_MRCS1 0xFFC02554
175#define SPORT2_MRCS2 0xFFC02558
176#define SPORT2_MRCS3 0xFFC0255C
177#define SPORT3_TCR1 0xFFC02600
178#define SPORT3_TCR2 0xFFC02604
179#define SPORT3_TCLKDIV 0xFFC02608
180#define SPORT3_TFSDIV 0xFFC0260C
181#define SPORT3_TX 0xFFC02610
182#define SPORT3_RX 0xFFC02618
183#define SPORT3_RCR1 0xFFC02620
184#define SPORT3_RCR2 0xFFC02624
185#define SPORT3_RCLKDIV 0xFFC02628
186#define SPORT3_RFSDIV 0xFFC0262C
187#define SPORT3_STAT 0xFFC02630
188#define SPORT3_CHNL 0xFFC02634
189#define SPORT3_MCMC1 0xFFC02638
190#define SPORT3_MCMC2 0xFFC0263C
191#define SPORT3_MTCS0 0xFFC02640
192#define SPORT3_MTCS1 0xFFC02644
193#define SPORT3_MTCS2 0xFFC02648
194#define SPORT3_MTCS3 0xFFC0264C
195#define SPORT3_MRCS0 0xFFC02650
196#define SPORT3_MRCS1 0xFFC02654
197#define SPORT3_MRCS2 0xFFC02658
198#define SPORT3_MRCS3 0xFFC0265C
199#define PORTFIO 0xFFC00700
200#define PORTFIO_CLEAR 0xFFC00704
201#define PORTFIO_SET 0xFFC00708
202#define PORTFIO_TOGGLE 0xFFC0070C
203#define PORTFIO_MASKA 0xFFC00710
204#define PORTFIO_MASKA_CLEAR 0xFFC00714
205#define PORTFIO_MASKA_SET 0xFFC00718
206#define PORTFIO_MASKA_TOGGLE 0xFFC0071C
207#define PORTFIO_MASKB 0xFFC00720
208#define PORTFIO_MASKB_CLEAR 0xFFC00724
209#define PORTFIO_MASKB_SET 0xFFC00728
210#define PORTFIO_MASKB_TOGGLE 0xFFC0072C
211#define PORTFIO_DIR 0xFFC00730
212#define PORTFIO_POLAR 0xFFC00734
213#define PORTFIO_EDGE 0xFFC00738
214#define PORTFIO_BOTH 0xFFC0073C
215#define PORTFIO_INEN 0xFFC00740
216#define PORTCIO_FER 0xFFC01500
217#define PORTCIO 0xFFC01510
218#define PORTCIO_CLEAR 0xFFC01520
219#define PORTCIO_SET 0xFFC01530
220#define PORTCIO_TOGGLE 0xFFC01540
221#define PORTCIO_DIR 0xFFC01550
222#define PORTCIO_INEN 0xFFC01560
223#define PORTDIO_FER 0xFFC01504
224#define PORTDIO 0xFFC01514
225#define PORTDIO_CLEAR 0xFFC01524
226#define PORTDIO_SET 0xFFC01534
227#define PORTDIO_TOGGLE 0xFFC01544
228#define PORTDIO_DIR 0xFFC01554
229#define PORTDIO_INEN 0xFFC01564
230#define PORTEIO_FER 0xFFC01508
231#define PORTEIO 0xFFC01518
232#define PORTEIO_CLEAR 0xFFC01528
233#define PORTEIO_SET 0xFFC01538
234#define PORTEIO_TOGGLE 0xFFC01548
235#define PORTEIO_DIR 0xFFC01558
236#define PORTEIO_INEN 0xFFC01568
237#define EBIU_AMGCTL 0xFFC00A00
238#define EBIU_AMBCTL0 0xFFC00A04
239#define EBIU_AMBCTL1 0xFFC00A08
240#define EBIU_SDGCTL 0xFFC00A10
241#define EBIU_SDBCTL 0xFFC00A14
242#define EBIU_SDRRC 0xFFC00A18
243#define EBIU_SDSTAT 0xFFC00A1C
244#define DMA0_TC_PER 0xFFC00B0C
245#define DMA0_TC_CNT 0xFFC00B10
246#define DMA0_NEXT_DESC_PTR 0xFFC00C00
247#define DMA0_START_ADDR 0xFFC00C04
248#define DMA0_CONFIG 0xFFC00C08
249#define DMA0_X_COUNT 0xFFC00C10
250#define DMA0_X_MODIFY 0xFFC00C14
251#define DMA0_Y_COUNT 0xFFC00C18
252#define DMA0_Y_MODIFY 0xFFC00C1C
253#define DMA0_CURR_DESC_PTR 0xFFC00C20
254#define DMA0_CURR_ADDR 0xFFC00C24
255#define DMA0_IRQ_STATUS 0xFFC00C28
256#define DMA0_PERIPHERAL_MAP 0xFFC00C2C
257#define DMA0_CURR_X_COUNT 0xFFC00C30
258#define DMA0_CURR_Y_COUNT 0xFFC00C38
259#define DMA1_NEXT_DESC_PTR 0xFFC00C40
260#define DMA1_START_ADDR 0xFFC00C44
261#define DMA1_CONFIG 0xFFC00C48
262#define DMA1_X_COUNT 0xFFC00C50
263#define DMA1_X_MODIFY 0xFFC00C54
264#define DMA1_Y_COUNT 0xFFC00C58
265#define DMA1_Y_MODIFY 0xFFC00C5C
266#define DMA1_CURR_DESC_PTR 0xFFC00C60
267#define DMA1_CURR_ADDR 0xFFC00C64
268#define DMA1_IRQ_STATUS 0xFFC00C68
269#define DMA1_PERIPHERAL_MAP 0xFFC00C6C
270#define DMA1_CURR_X_COUNT 0xFFC00C70
271#define DMA1_CURR_Y_COUNT 0xFFC00C78
272#define DMA2_NEXT_DESC_PTR 0xFFC00C80
273#define DMA2_START_ADDR 0xFFC00C84
274#define DMA2_CONFIG 0xFFC00C88
275#define DMA2_X_COUNT 0xFFC00C90
276#define DMA2_X_MODIFY 0xFFC00C94
277#define DMA2_Y_COUNT 0xFFC00C98
278#define DMA2_Y_MODIFY 0xFFC00C9C
279#define DMA2_CURR_DESC_PTR 0xFFC00CA0
280#define DMA2_CURR_ADDR 0xFFC00CA4
281#define DMA2_IRQ_STATUS 0xFFC00CA8
282#define DMA2_PERIPHERAL_MAP 0xFFC00CAC
283#define DMA2_CURR_X_COUNT 0xFFC00CB0
284#define DMA2_CURR_Y_COUNT 0xFFC00CB8
285#define DMA3_NEXT_DESC_PTR 0xFFC00CC0
286#define DMA3_START_ADDR 0xFFC00CC4
287#define DMA3_CONFIG 0xFFC00CC8
288#define DMA3_X_COUNT 0xFFC00CD0
289#define DMA3_X_MODIFY 0xFFC00CD4
290#define DMA3_Y_COUNT 0xFFC00CD8
291#define DMA3_Y_MODIFY 0xFFC00CDC
292#define DMA3_CURR_DESC_PTR 0xFFC00CE0
293#define DMA3_CURR_ADDR 0xFFC00CE4
294#define DMA3_IRQ_STATUS 0xFFC00CE8
295#define DMA3_PERIPHERAL_MAP 0xFFC00CEC
296#define DMA3_CURR_X_COUNT 0xFFC00CF0
297#define DMA3_CURR_Y_COUNT 0xFFC00CF8
298#define DMA4_NEXT_DESC_PTR 0xFFC00D00
299#define DMA4_START_ADDR 0xFFC00D04
300#define DMA4_CONFIG 0xFFC00D08
301#define DMA4_X_COUNT 0xFFC00D10
302#define DMA4_X_MODIFY 0xFFC00D14
303#define DMA4_Y_COUNT 0xFFC00D18
304#define DMA4_Y_MODIFY 0xFFC00D1C
305#define DMA4_CURR_DESC_PTR 0xFFC00D20
306#define DMA4_CURR_ADDR 0xFFC00D24
307#define DMA4_IRQ_STATUS 0xFFC00D28
308#define DMA4_PERIPHERAL_MAP 0xFFC00D2C
309#define DMA4_CURR_X_COUNT 0xFFC00D30
310#define DMA4_CURR_Y_COUNT 0xFFC00D38
311#define DMA5_NEXT_DESC_PTR 0xFFC00D40
312#define DMA5_START_ADDR 0xFFC00D44
313#define DMA5_CONFIG 0xFFC00D48
314#define DMA5_X_COUNT 0xFFC00D50
315#define DMA5_X_MODIFY 0xFFC00D54
316#define DMA5_Y_COUNT 0xFFC00D58
317#define DMA5_Y_MODIFY 0xFFC00D5C
318#define DMA5_CURR_DESC_PTR 0xFFC00D60
319#define DMA5_CURR_ADDR 0xFFC00D64
320#define DMA5_IRQ_STATUS 0xFFC00D68
321#define DMA5_PERIPHERAL_MAP 0xFFC00D6C
322#define DMA5_CURR_X_COUNT 0xFFC00D70
323#define DMA5_CURR_Y_COUNT 0xFFC00D78
324#define DMA6_NEXT_DESC_PTR 0xFFC00D80
325#define DMA6_START_ADDR 0xFFC00D84
326#define DMA6_CONFIG 0xFFC00D88
327#define DMA6_X_COUNT 0xFFC00D90
328#define DMA6_X_MODIFY 0xFFC00D94
329#define DMA6_Y_COUNT 0xFFC00D98
330#define DMA6_Y_MODIFY 0xFFC00D9C
331#define DMA6_CURR_DESC_PTR 0xFFC00DA0
332#define DMA6_CURR_ADDR 0xFFC00DA4
333#define DMA6_IRQ_STATUS 0xFFC00DA8
334#define DMA6_PERIPHERAL_MAP 0xFFC00DAC
335#define DMA6_CURR_X_COUNT 0xFFC00DB0
336#define DMA6_CURR_Y_COUNT 0xFFC00DB8
337#define DMA7_NEXT_DESC_PTR 0xFFC00DC0
338#define DMA7_START_ADDR 0xFFC00DC4
339#define DMA7_CONFIG 0xFFC00DC8
340#define DMA7_X_COUNT 0xFFC00DD0
341#define DMA7_X_MODIFY 0xFFC00DD4
342#define DMA7_Y_COUNT 0xFFC00DD8
343#define DMA7_Y_MODIFY 0xFFC00DDC
344#define DMA7_CURR_DESC_PTR 0xFFC00DE0
345#define DMA7_CURR_ADDR 0xFFC00DE4
346#define DMA7_IRQ_STATUS 0xFFC00DE8
347#define DMA7_PERIPHERAL_MAP 0xFFC00DEC
348#define DMA7_CURR_X_COUNT 0xFFC00DF0
349#define DMA7_CURR_Y_COUNT 0xFFC00DF8
350#define DMA1_TC_PER 0xFFC01B0C
351#define DMA1_TC_CNT 0xFFC01B10
352#define DMA8_NEXT_DESC_PTR 0xFFC01C00
353#define DMA8_START_ADDR 0xFFC01C04
354#define DMA8_CONFIG 0xFFC01C08
355#define DMA8_X_COUNT 0xFFC01C10
356#define DMA8_X_MODIFY 0xFFC01C14
357#define DMA8_Y_COUNT 0xFFC01C18
358#define DMA8_Y_MODIFY 0xFFC01C1C
359#define DMA8_CURR_DESC_PTR 0xFFC01C20
360#define DMA8_CURR_ADDR 0xFFC01C24
361#define DMA8_IRQ_STATUS 0xFFC01C28
362#define DMA8_PERIPHERAL_MAP 0xFFC01C2C
363#define DMA8_CURR_X_COUNT 0xFFC01C30
364#define DMA8_CURR_Y_COUNT 0xFFC01C38
365#define DMA9_NEXT_DESC_PTR 0xFFC01C40
366#define DMA9_START_ADDR 0xFFC01C44
367#define DMA9_CONFIG 0xFFC01C48
368#define DMA9_X_COUNT 0xFFC01C50
369#define DMA9_X_MODIFY 0xFFC01C54
370#define DMA9_Y_COUNT 0xFFC01C58
371#define DMA9_Y_MODIFY 0xFFC01C5C
372#define DMA9_CURR_DESC_PTR 0xFFC01C60
373#define DMA9_CURR_ADDR 0xFFC01C64
374#define DMA9_IRQ_STATUS 0xFFC01C68
375#define DMA9_PERIPHERAL_MAP 0xFFC01C6C
376#define DMA9_CURR_X_COUNT 0xFFC01C70
377#define DMA9_CURR_Y_COUNT 0xFFC01C78
378#define DMA10_NEXT_DESC_PTR 0xFFC01C80
379#define DMA10_START_ADDR 0xFFC01C84
380#define DMA10_CONFIG 0xFFC01C88
381#define DMA10_X_COUNT 0xFFC01C90
382#define DMA10_X_MODIFY 0xFFC01C94
383#define DMA10_Y_COUNT 0xFFC01C98
384#define DMA10_Y_MODIFY 0xFFC01C9C
385#define DMA10_CURR_DESC_PTR 0xFFC01CA0
386#define DMA10_CURR_ADDR 0xFFC01CA4
387#define DMA10_IRQ_STATUS 0xFFC01CA8
388#define DMA10_PERIPHERAL_MAP 0xFFC01CAC
389#define DMA10_CURR_X_COUNT 0xFFC01CB0
390#define DMA10_CURR_Y_COUNT 0xFFC01CB8
391#define DMA11_NEXT_DESC_PTR 0xFFC01CC0
392#define DMA11_START_ADDR 0xFFC01CC4
393#define DMA11_CONFIG 0xFFC01CC8
394#define DMA11_X_COUNT 0xFFC01CD0
395#define DMA11_X_MODIFY 0xFFC01CD4
396#define DMA11_Y_COUNT 0xFFC01CD8
397#define DMA11_Y_MODIFY 0xFFC01CDC
398#define DMA11_CURR_DESC_PTR 0xFFC01CE0
399#define DMA11_CURR_ADDR 0xFFC01CE4
400#define DMA11_IRQ_STATUS 0xFFC01CE8
401#define DMA11_PERIPHERAL_MAP 0xFFC01CEC
402#define DMA11_CURR_X_COUNT 0xFFC01CF0
403#define DMA11_CURR_Y_COUNT 0xFFC01CF8
404#define DMA12_NEXT_DESC_PTR 0xFFC01D00
405#define DMA12_START_ADDR 0xFFC01D04
406#define DMA12_CONFIG 0xFFC01D08
407#define DMA12_X_COUNT 0xFFC01D10
408#define DMA12_X_MODIFY 0xFFC01D14
409#define DMA12_Y_COUNT 0xFFC01D18
410#define DMA12_Y_MODIFY 0xFFC01D1C
411#define DMA12_CURR_DESC_PTR 0xFFC01D20
412#define DMA12_CURR_ADDR 0xFFC01D24
413#define DMA12_IRQ_STATUS 0xFFC01D28
414#define DMA12_PERIPHERAL_MAP 0xFFC01D2C
415#define DMA12_CURR_X_COUNT 0xFFC01D30
416#define DMA12_CURR_Y_COUNT 0xFFC01D38
417#define DMA13_NEXT_DESC_PTR 0xFFC01D40
418#define DMA13_START_ADDR 0xFFC01D44
419#define DMA13_CONFIG 0xFFC01D48
420#define DMA13_X_COUNT 0xFFC01D50
421#define DMA13_X_MODIFY 0xFFC01D54
422#define DMA13_Y_COUNT 0xFFC01D58
423#define DMA13_Y_MODIFY 0xFFC01D5C
424#define DMA13_CURR_DESC_PTR 0xFFC01D60
425#define DMA13_CURR_ADDR 0xFFC01D64
426#define DMA13_IRQ_STATUS 0xFFC01D68
427#define DMA13_PERIPHERAL_MAP 0xFFC01D6C
428#define DMA13_CURR_X_COUNT 0xFFC01D70
429#define DMA13_CURR_Y_COUNT 0xFFC01D78
430#define DMA14_NEXT_DESC_PTR 0xFFC01D80
431#define DMA14_START_ADDR 0xFFC01D84
432#define DMA14_CONFIG 0xFFC01D88
433#define DMA14_X_COUNT 0xFFC01D90
434#define DMA14_X_MODIFY 0xFFC01D94
435#define DMA14_Y_COUNT 0xFFC01D98
436#define DMA14_Y_MODIFY 0xFFC01D9C
437#define DMA14_CURR_DESC_PTR 0xFFC01DA0
438#define DMA14_CURR_ADDR 0xFFC01DA4
439#define DMA14_IRQ_STATUS 0xFFC01DA8
440#define DMA14_PERIPHERAL_MAP 0xFFC01DAC
441#define DMA14_CURR_X_COUNT 0xFFC01DB0
442#define DMA14_CURR_Y_COUNT 0xFFC01DB8
443#define DMA15_NEXT_DESC_PTR 0xFFC01DC0
444#define DMA15_START_ADDR 0xFFC01DC4
445#define DMA15_CONFIG 0xFFC01DC8
446#define DMA15_X_COUNT 0xFFC01DD0
447#define DMA15_X_MODIFY 0xFFC01DD4
448#define DMA15_Y_COUNT 0xFFC01DD8
449#define DMA15_Y_MODIFY 0xFFC01DDC
450#define DMA15_CURR_DESC_PTR 0xFFC01DE0
451#define DMA15_CURR_ADDR 0xFFC01DE4
452#define DMA15_IRQ_STATUS 0xFFC01DE8
453#define DMA15_PERIPHERAL_MAP 0xFFC01DEC
454#define DMA15_CURR_X_COUNT 0xFFC01DF0
455#define DMA15_CURR_Y_COUNT 0xFFC01DF8
456#define DMA16_NEXT_DESC_PTR 0xFFC01E00
457#define DMA16_START_ADDR 0xFFC01E04
458#define DMA16_CONFIG 0xFFC01E08
459#define DMA16_X_COUNT 0xFFC01E10
460#define DMA16_X_MODIFY 0xFFC01E14
461#define DMA16_Y_COUNT 0xFFC01E18
462#define DMA16_Y_MODIFY 0xFFC01E1C
463#define DMA16_CURR_DESC_PTR 0xFFC01E20
464#define DMA16_CURR_ADDR 0xFFC01E24
465#define DMA16_IRQ_STATUS 0xFFC01E28
466#define DMA16_PERIPHERAL_MAP 0xFFC01E2C
467#define DMA16_CURR_X_COUNT 0xFFC01E30
468#define DMA16_CURR_Y_COUNT 0xFFC01E38
469#define DMA17_NEXT_DESC_PTR 0xFFC01E40
470#define DMA17_START_ADDR 0xFFC01E44
471#define DMA17_CONFIG 0xFFC01E48
472#define DMA17_X_COUNT 0xFFC01E50
473#define DMA17_X_MODIFY 0xFFC01E54
474#define DMA17_Y_COUNT 0xFFC01E58
475#define DMA17_Y_MODIFY 0xFFC01E5C
476#define DMA17_CURR_DESC_PTR 0xFFC01E60
477#define DMA17_CURR_ADDR 0xFFC01E64
478#define DMA17_IRQ_STATUS 0xFFC01E68
479#define DMA17_PERIPHERAL_MAP 0xFFC01E6C
480#define DMA17_CURR_X_COUNT 0xFFC01E70
481#define DMA17_CURR_Y_COUNT 0xFFC01E78
482#define DMA18_NEXT_DESC_PTR 0xFFC01E80
483#define DMA18_START_ADDR 0xFFC01E84
484#define DMA18_CONFIG 0xFFC01E88
485#define DMA18_X_COUNT 0xFFC01E90
486#define DMA18_X_MODIFY 0xFFC01E94
487#define DMA18_Y_COUNT 0xFFC01E98
488#define DMA18_Y_MODIFY 0xFFC01E9C
489#define DMA18_CURR_DESC_PTR 0xFFC01EA0
490#define DMA18_CURR_ADDR 0xFFC01EA4
491#define DMA18_IRQ_STATUS 0xFFC01EA8
492#define DMA18_PERIPHERAL_MAP 0xFFC01EAC
493#define DMA18_CURR_X_COUNT 0xFFC01EB0
494#define DMA18_CURR_Y_COUNT 0xFFC01EB8
495#define DMA19_NEXT_DESC_PTR 0xFFC01EC0
496#define DMA19_START_ADDR 0xFFC01EC4
497#define DMA19_CONFIG 0xFFC01EC8
498#define DMA19_X_COUNT 0xFFC01ED0
499#define DMA19_X_MODIFY 0xFFC01ED4
500#define DMA19_Y_COUNT 0xFFC01ED8
501#define DMA19_Y_MODIFY 0xFFC01EDC
502#define DMA19_CURR_DESC_PTR 0xFFC01EE0
503#define DMA19_CURR_ADDR 0xFFC01EE4
504#define DMA19_IRQ_STATUS 0xFFC01EE8
505#define DMA19_PERIPHERAL_MAP 0xFFC01EEC
506#define DMA19_CURR_X_COUNT 0xFFC01EF0
507#define DMA19_CURR_Y_COUNT 0xFFC01EF8
508#define MDMA0_D0_NEXT_DESC_PTR 0xFFC00E00
509#define MDMA0_D0_START_ADDR 0xFFC00E04
510#define MDMA0_D0_CONFIG 0xFFC00E08
511#define MDMA0_D0_X_COUNT 0xFFC00E10
512#define MDMA0_D0_X_MODIFY 0xFFC00E14
513#define MDMA0_D0_Y_COUNT 0xFFC00E18
514#define MDMA0_D0_Y_MODIFY 0xFFC00E1C
515#define MDMA0_D0_CURR_DESC_PTR 0xFFC00E20
516#define MDMA0_D0_CURR_ADDR 0xFFC00E24
517#define MDMA0_D0_IRQ_STATUS 0xFFC00E28
518#define MDMA0_D0_PERIPHERAL_MAP 0xFFC00E2C
519#define MDMA0_D0_CURR_X_COUNT 0xFFC00E30
520#define MDMA0_D0_CURR_Y_COUNT 0xFFC00E38
521#define MDMA0_S0_NEXT_DESC_PTR 0xFFC00E40
522#define MDMA0_S0_START_ADDR 0xFFC00E44
523#define MDMA0_S0_CONFIG 0xFFC00E48
524#define MDMA0_S0_X_COUNT 0xFFC00E50
525#define MDMA0_S0_X_MODIFY 0xFFC00E54
526#define MDMA0_S0_Y_COUNT 0xFFC00E58
527#define MDMA0_S0_Y_MODIFY 0xFFC00E5C
528#define MDMA0_S0_CURR_DESC_PTR 0xFFC00E60
529#define MDMA0_S0_CURR_ADDR 0xFFC00E64
530#define MDMA0_S0_IRQ_STATUS 0xFFC00E68
531#define MDMA0_S0_PERIPHERAL_MAP 0xFFC00E6C
532#define MDMA0_S0_CURR_X_COUNT 0xFFC00E70
533#define MDMA0_S0_CURR_Y_COUNT 0xFFC00E78
534#define MDMA0_D1_NEXT_DESC_PTR 0xFFC00E80
535#define MDMA0_D1_START_ADDR 0xFFC00E84
536#define MDMA0_D1_CONFIG 0xFFC00E88
537#define MDMA0_D1_X_COUNT 0xFFC00E90
538#define MDMA0_D1_X_MODIFY 0xFFC00E94
539#define MDMA0_D1_Y_COUNT 0xFFC00E98
540#define MDMA0_D1_Y_MODIFY 0xFFC00E9C
541#define MDMA0_D1_CURR_DESC_PTR 0xFFC00EA0
542#define MDMA0_D1_CURR_ADDR 0xFFC00EA4
543#define MDMA0_D1_IRQ_STATUS 0xFFC00EA8
544#define MDMA0_D1_PERIPHERAL_MAP 0xFFC00EAC
545#define MDMA0_D1_CURR_X_COUNT 0xFFC00EB0
546#define MDMA0_D1_CURR_Y_COUNT 0xFFC00EB8
547#define MDMA0_S1_NEXT_DESC_PTR 0xFFC00EC0
548#define MDMA0_S1_START_ADDR 0xFFC00EC4
549#define MDMA0_S1_CONFIG 0xFFC00EC8
550#define MDMA0_S1_X_COUNT 0xFFC00ED0
551#define MDMA0_S1_X_MODIFY 0xFFC00ED4
552#define MDMA0_S1_Y_COUNT 0xFFC00ED8
553#define MDMA0_S1_Y_MODIFY 0xFFC00EDC
554#define MDMA0_S1_CURR_DESC_PTR 0xFFC00EE0
555#define MDMA0_S1_CURR_ADDR 0xFFC00EE4
556#define MDMA0_S1_IRQ_STATUS 0xFFC00EE8
557#define MDMA0_S1_PERIPHERAL_MAP 0xFFC00EEC
558#define MDMA0_S1_CURR_X_COUNT 0xFFC00EF0
559#define MDMA0_S1_CURR_Y_COUNT 0xFFC00EF8
560#define MDMA1_D0_NEXT_DESC_PTR 0xFFC01F00
561#define MDMA1_D0_START_ADDR 0xFFC01F04
562#define MDMA1_D0_CONFIG 0xFFC01F08
563#define MDMA1_D0_X_COUNT 0xFFC01F10
564#define MDMA1_D0_X_MODIFY 0xFFC01F14
565#define MDMA1_D0_Y_COUNT 0xFFC01F18
566#define MDMA1_D0_Y_MODIFY 0xFFC01F1C
567#define MDMA1_D0_CURR_DESC_PTR 0xFFC01F20
568#define MDMA1_D0_CURR_ADDR 0xFFC01F24
569#define MDMA1_D0_IRQ_STATUS 0xFFC01F28
570#define MDMA1_D0_PERIPHERAL_MAP 0xFFC01F2C
571#define MDMA1_D0_CURR_X_COUNT 0xFFC01F30
572#define MDMA1_D0_CURR_Y_COUNT 0xFFC01F38
573#define MDMA1_S0_NEXT_DESC_PTR 0xFFC01F40
574#define MDMA1_S0_START_ADDR 0xFFC01F44
575#define MDMA1_S0_CONFIG 0xFFC01F48
576#define MDMA1_S0_X_COUNT 0xFFC01F50
577#define MDMA1_S0_X_MODIFY 0xFFC01F54
578#define MDMA1_S0_Y_COUNT 0xFFC01F58
579#define MDMA1_S0_Y_MODIFY 0xFFC01F5C
580#define MDMA1_S0_CURR_DESC_PTR 0xFFC01F60
581#define MDMA1_S0_CURR_ADDR 0xFFC01F64
582#define MDMA1_S0_IRQ_STATUS 0xFFC01F68
583#define MDMA1_S0_PERIPHERAL_MAP 0xFFC01F6C
584#define MDMA1_S0_CURR_X_COUNT 0xFFC01F70
585#define MDMA1_S0_CURR_Y_COUNT 0xFFC01F78
586#define MDMA1_D1_NEXT_DESC_PTR 0xFFC01F80
587#define MDMA1_D1_START_ADDR 0xFFC01F84
588#define MDMA1_D1_CONFIG 0xFFC01F88
589#define MDMA1_D1_X_COUNT 0xFFC01F90
590#define MDMA1_D1_X_MODIFY 0xFFC01F94
591#define MDMA1_D1_Y_COUNT 0xFFC01F98
592#define MDMA1_D1_Y_MODIFY 0xFFC01F9C
593#define MDMA1_D1_CURR_DESC_PTR 0xFFC01FA0
594#define MDMA1_D1_CURR_ADDR 0xFFC01FA4
595#define MDMA1_D1_IRQ_STATUS 0xFFC01FA8
596#define MDMA1_D1_PERIPHERAL_MAP 0xFFC01FAC
597#define MDMA1_D1_CURR_X_COUNT 0xFFC01FB0
598#define MDMA1_D1_CURR_Y_COUNT 0xFFC01FB8
599#define MDMA1_S1_NEXT_DESC_PTR 0xFFC01FC0
600#define MDMA1_S1_START_ADDR 0xFFC01FC4
601#define MDMA1_S1_CONFIG 0xFFC01FC8
602#define MDMA1_S1_X_COUNT 0xFFC01FD0
603#define MDMA1_S1_X_MODIFY 0xFFC01FD4
604#define MDMA1_S1_Y_COUNT 0xFFC01FD8
605#define MDMA1_S1_Y_MODIFY 0xFFC01FDC
606#define MDMA1_S1_CURR_DESC_PTR 0xFFC01FE0
607#define MDMA1_S1_CURR_ADDR 0xFFC01FE4
608#define MDMA1_S1_IRQ_STATUS 0xFFC01FE8
609#define MDMA1_S1_PERIPHERAL_MAP 0xFFC01FEC
610#define MDMA1_S1_CURR_X_COUNT 0xFFC01FF0
611#define MDMA1_S1_CURR_Y_COUNT 0xFFC01FF8
612#define PPI_CONTROL 0xFFC01000
613#define PPI_STATUS 0xFFC01004
614#define PPI_DELAY 0xFFC0100C
615#define PPI_COUNT 0xFFC01008
616#define PPI_FRAME 0xFFC01010
617#define TWI0_CLKDIV 0xFFC01400
618#define TWI0_CONTROL 0xFFC01404
619#define TWI0_SLAVE_CTRL 0xFFC01408
620#define TWI0_SLAVE_STAT 0xFFC0140C
621#define TWI0_SLAVE_ADDR 0xFFC01410
622#define TWI0_MASTER_CTL 0xFFC01414
623#define TWI0_MASTER_STAT 0xFFC01418
624#define TWI0_MASTER_ADDR 0xFFC0141C
625#define TWI0_INT_STAT 0xFFC01420
626#define TWI0_INT_MASK 0xFFC01424
627#define TWI0_FIFO_CTL 0xFFC01428
628#define TWI0_FIFO_STAT 0xFFC0142C
629#define TWI0_XMT_DATA8 0xFFC01480
630#define TWI0_XMT_DATA16 0xFFC01484
631#define TWI0_RCV_DATA8 0xFFC01488
632#define TWI0_RCV_DATA16 0xFFC0148C
633#define TWI1_CLKDIV 0xFFC02200
634#define TWI1_CONTROL 0xFFC02204
635#define TWI1_SLAVE_CTRL 0xFFC02208
636#define TWI1_SLAVE_STAT 0xFFC0220C
637#define TWI1_SLAVE_ADDR 0xFFC02210
638#define TWI1_MASTER_CTL 0xFFC02214
639#define TWI1_MASTER_STAT 0xFFC02218
640#define TWI1_MASTER_ADDR 0xFFC0221C
641#define TWI1_INT_STAT 0xFFC02220
642#define TWI1_INT_MASK 0xFFC02224
643#define TWI1_FIFO_CTL 0xFFC02228
644#define TWI1_FIFO_STAT 0xFFC0222C
645#define TWI1_XMT_DATA8 0xFFC02280
646#define TWI1_XMT_DATA16 0xFFC02284
647#define TWI1_RCV_DATA8 0xFFC02288
648#define TWI1_RCV_DATA16 0xFFC0228C
649#define CAN_MC1 0xFFC02A00
650#define CAN_MD1 0xFFC02A04
651#define CAN_TRS1 0xFFC02A08
652#define CAN_TRR1 0xFFC02A0C
653#define CAN_TA1 0xFFC02A10
654#define CAN_AA1 0xFFC02A14
655#define CAN_RMP1 0xFFC02A18
656#define CAN_RML1 0xFFC02A1C
657#define CAN_MBTIF1 0xFFC02A20
658#define CAN_MBRIF1 0xFFC02A24
659#define CAN_MBIM1 0xFFC02A28
660#define CAN_RFH1 0xFFC02A2C
661#define CAN_OPSS1 0xFFC02A30
662#define CAN_MC2 0xFFC02A40
663#define CAN_MD2 0xFFC02A44
664#define CAN_TRS2 0xFFC02A48
665#define CAN_TRR2 0xFFC02A4C
666#define CAN_TA2 0xFFC02A50
667#define CAN_AA2 0xFFC02A54
668#define CAN_RMP2 0xFFC02A58
669#define CAN_RML2 0xFFC02A5C
670#define CAN_MBTIF2 0xFFC02A60
671#define CAN_MBRIF2 0xFFC02A64
672#define CAN_MBIM2 0xFFC02A68
673#define CAN_RFH2 0xFFC02A6C
674#define CAN_OPSS2 0xFFC02A70
675#define CAN_CLOCK 0xFFC02A80
676#define CAN_TIMING 0xFFC02A84
677#define CAN_DEBUG 0xFFC02A88
678#define CAN_STATUS 0xFFC02A8C
679#define CAN_CEC 0xFFC02A90
680#define CAN_GIS 0xFFC02A94
681#define CAN_GIM 0xFFC02A98
682#define CAN_GIF 0xFFC02A9C
683#define CAN_CONTROL 0xFFC02AA0
684#define CAN_INTR 0xFFC02AA4
685#define CAN_VERSION 0xFFC02AA8
686#define CAN_MBTD 0xFFC02AAC
687#define CAN_EWR 0xFFC02AB0
688#define CAN_ESR 0xFFC02AB4
689#define CAN_UCREG 0xFFC02AC0
690#define CAN_UCCNT 0xFFC02AC4
691#define CAN_UCRC 0xFFC02AC8
692#define CAN_UCCNF 0xFFC02ACC
693#define CAN_VERSION2 0xFFC02AD4
694#define CAN_AM00L 0xFFC02B00
695#define CAN_AM00H 0xFFC02B04
696#define CAN_AM01L 0xFFC02B08
697#define CAN_AM01H 0xFFC02B0C
698#define CAN_AM02L 0xFFC02B10
699#define CAN_AM02H 0xFFC02B14
700#define CAN_AM03L 0xFFC02B18
701#define CAN_AM03H 0xFFC02B1C
702#define CAN_AM04L 0xFFC02B20
703#define CAN_AM04H 0xFFC02B24
704#define CAN_AM05L 0xFFC02B28
705#define CAN_AM05H 0xFFC02B2C
706#define CAN_AM06L 0xFFC02B30
707#define CAN_AM06H 0xFFC02B34
708#define CAN_AM07L 0xFFC02B38
709#define CAN_AM07H 0xFFC02B3C
710#define CAN_AM08L 0xFFC02B40
711#define CAN_AM08H 0xFFC02B44
712#define CAN_AM09L 0xFFC02B48
713#define CAN_AM09H 0xFFC02B4C
714#define CAN_AM10L 0xFFC02B50
715#define CAN_AM10H 0xFFC02B54
716#define CAN_AM11L 0xFFC02B58
717#define CAN_AM11H 0xFFC02B5C
718#define CAN_AM12L 0xFFC02B60
719#define CAN_AM12H 0xFFC02B64
720#define CAN_AM13L 0xFFC02B68
721#define CAN_AM13H 0xFFC02B6C
722#define CAN_AM14L 0xFFC02B70
723#define CAN_AM14H 0xFFC02B74
724#define CAN_AM15L 0xFFC02B78
725#define CAN_AM15H 0xFFC02B7C
726#define CAN_AM16L 0xFFC02B80
727#define CAN_AM16H 0xFFC02B84
728#define CAN_AM17L 0xFFC02B88
729#define CAN_AM17H 0xFFC02B8C
730#define CAN_AM18L 0xFFC02B90
731#define CAN_AM18H 0xFFC02B94
732#define CAN_AM19L 0xFFC02B98
733#define CAN_AM19H 0xFFC02B9C
734#define CAN_AM20L 0xFFC02BA0
735#define CAN_AM20H 0xFFC02BA4
736#define CAN_AM21L 0xFFC02BA8
737#define CAN_AM21H 0xFFC02BAC
738#define CAN_AM22L 0xFFC02BB0
739#define CAN_AM22H 0xFFC02BB4
740#define CAN_AM23L 0xFFC02BB8
741#define CAN_AM23H 0xFFC02BBC
742#define CAN_AM24L 0xFFC02BC0
743#define CAN_AM24H 0xFFC02BC4
744#define CAN_AM25L 0xFFC02BC8
745#define CAN_AM25H 0xFFC02BCC
746#define CAN_AM26L 0xFFC02BD0
747#define CAN_AM26H 0xFFC02BD4
748#define CAN_AM27L 0xFFC02BD8
749#define CAN_AM27H 0xFFC02BDC
750#define CAN_AM28L 0xFFC02BE0
751#define CAN_AM28H 0xFFC02BE4
752#define CAN_AM29L 0xFFC02BE8
753#define CAN_AM29H 0xFFC02BEC
754#define CAN_AM30L 0xFFC02BF0
755#define CAN_AM30H 0xFFC02BF4
756#define CAN_AM31L 0xFFC02BF8
757#define CAN_AM31H 0xFFC02BFC
758#define CAN_MB00_DATA0 0xFFC02C00
759#define CAN_MB00_DATA1 0xFFC02C04
760#define CAN_MB00_DATA2 0xFFC02C08
761#define CAN_MB00_DATA3 0xFFC02C0C
762#define CAN_MB00_LENGTH 0xFFC02C10
763#define CAN_MB00_TIMESTAMP 0xFFC02C14
764#define CAN_MB00_ID0 0xFFC02C18
765#define CAN_MB00_ID1 0xFFC02C1C
766#define CAN_MB01_DATA0 0xFFC02C20
767#define CAN_MB01_DATA1 0xFFC02C24
768#define CAN_MB01_DATA2 0xFFC02C28
769#define CAN_MB01_DATA3 0xFFC02C2C
770#define CAN_MB01_LENGTH 0xFFC02C30
771#define CAN_MB01_TIMESTAMP 0xFFC02C34
772#define CAN_MB01_ID0 0xFFC02C38
773#define CAN_MB01_ID1 0xFFC02C3C
774#define CAN_MB02_DATA0 0xFFC02C40
775#define CAN_MB02_DATA1 0xFFC02C44
776#define CAN_MB02_DATA2 0xFFC02C48
777#define CAN_MB02_DATA3 0xFFC02C4C
778#define CAN_MB02_LENGTH 0xFFC02C50
779#define CAN_MB02_TIMESTAMP 0xFFC02C54
780#define CAN_MB02_ID0 0xFFC02C58
781#define CAN_MB02_ID1 0xFFC02C5C
782#define CAN_MB03_DATA0 0xFFC02C60
783#define CAN_MB03_DATA1 0xFFC02C64
784#define CAN_MB03_DATA2 0xFFC02C68
785#define CAN_MB03_DATA3 0xFFC02C6C
786#define CAN_MB03_LENGTH 0xFFC02C70
787#define CAN_MB03_TIMESTAMP 0xFFC02C74
788#define CAN_MB03_ID0 0xFFC02C78
789#define CAN_MB03_ID1 0xFFC02C7C
790#define CAN_MB04_DATA0 0xFFC02C80
791#define CAN_MB04_DATA1 0xFFC02C84
792#define CAN_MB04_DATA2 0xFFC02C88
793#define CAN_MB04_DATA3 0xFFC02C8C
794#define CAN_MB04_LENGTH 0xFFC02C90
795#define CAN_MB04_TIMESTAMP 0xFFC02C94
796#define CAN_MB04_ID0 0xFFC02C98
797#define CAN_MB04_ID1 0xFFC02C9C
798#define CAN_MB05_DATA0 0xFFC02CA0
799#define CAN_MB05_DATA1 0xFFC02CA4
800#define CAN_MB05_DATA2 0xFFC02CA8
801#define CAN_MB05_DATA3 0xFFC02CAC
802#define CAN_MB05_LENGTH 0xFFC02CB0
803#define CAN_MB05_TIMESTAMP 0xFFC02CB4
804#define CAN_MB05_ID0 0xFFC02CB8
805#define CAN_MB05_ID1 0xFFC02CBC
806#define CAN_MB06_DATA0 0xFFC02CC0
807#define CAN_MB06_DATA1 0xFFC02CC4
808#define CAN_MB06_DATA2 0xFFC02CC8
809#define CAN_MB06_DATA3 0xFFC02CCC
810#define CAN_MB06_LENGTH 0xFFC02CD0
811#define CAN_MB06_TIMESTAMP 0xFFC02CD4
812#define CAN_MB06_ID0 0xFFC02CD8
813#define CAN_MB06_ID1 0xFFC02CDC
814#define CAN_MB07_DATA0 0xFFC02CE0
815#define CAN_MB07_DATA1 0xFFC02CE4
816#define CAN_MB07_DATA2 0xFFC02CE8
817#define CAN_MB07_DATA3 0xFFC02CEC
818#define CAN_MB07_LENGTH 0xFFC02CF0
819#define CAN_MB07_TIMESTAMP 0xFFC02CF4
820#define CAN_MB07_ID0 0xFFC02CF8
821#define CAN_MB07_ID1 0xFFC02CFC
822#define CAN_MB08_DATA0 0xFFC02D00
823#define CAN_MB08_DATA1 0xFFC02D04
824#define CAN_MB08_DATA2 0xFFC02D08
825#define CAN_MB08_DATA3 0xFFC02D0C
826#define CAN_MB08_LENGTH 0xFFC02D10
827#define CAN_MB08_TIMESTAMP 0xFFC02D14
828#define CAN_MB08_ID0 0xFFC02D18
829#define CAN_MB08_ID1 0xFFC02D1C
830#define CAN_MB09_DATA0 0xFFC02D20
831#define CAN_MB09_DATA1 0xFFC02D24
832#define CAN_MB09_DATA2 0xFFC02D28
833#define CAN_MB09_DATA3 0xFFC02D2C
834#define CAN_MB09_LENGTH 0xFFC02D30
835#define CAN_MB09_TIMESTAMP 0xFFC02D34
836#define CAN_MB09_ID0 0xFFC02D38
837#define CAN_MB09_ID1 0xFFC02D3C
838#define CAN_MB10_DATA0 0xFFC02D40
839#define CAN_MB10_DATA1 0xFFC02D44
840#define CAN_MB10_DATA2 0xFFC02D48
841#define CAN_MB10_DATA3 0xFFC02D4C
842#define CAN_MB10_LENGTH 0xFFC02D50
843#define CAN_MB10_TIMESTAMP 0xFFC02D54
844#define CAN_MB10_ID0 0xFFC02D58
845#define CAN_MB10_ID1 0xFFC02D5C
846#define CAN_MB11_DATA0 0xFFC02D60
847#define CAN_MB11_DATA1 0xFFC02D64
848#define CAN_MB11_DATA2 0xFFC02D68
849#define CAN_MB11_DATA3 0xFFC02D6C
850#define CAN_MB11_LENGTH 0xFFC02D70
851#define CAN_MB11_TIMESTAMP 0xFFC02D74
852#define CAN_MB11_ID0 0xFFC02D78
853#define CAN_MB11_ID1 0xFFC02D7C
854#define CAN_MB12_DATA0 0xFFC02D80
855#define CAN_MB12_DATA1 0xFFC02D84
856#define CAN_MB12_DATA2 0xFFC02D88
857#define CAN_MB12_DATA3 0xFFC02D8C
858#define CAN_MB12_LENGTH 0xFFC02D90
859#define CAN_MB12_TIMESTAMP 0xFFC02D94
860#define CAN_MB12_ID0 0xFFC02D98
861#define CAN_MB12_ID1 0xFFC02D9C
862#define CAN_MB13_DATA0 0xFFC02DA0
863#define CAN_MB13_DATA1 0xFFC02DA4
864#define CAN_MB13_DATA2 0xFFC02DA8
865#define CAN_MB13_DATA3 0xFFC02DAC
866#define CAN_MB13_LENGTH 0xFFC02DB0
867#define CAN_MB13_TIMESTAMP 0xFFC02DB4
868#define CAN_MB13_ID0 0xFFC02DB8
869#define CAN_MB13_ID1 0xFFC02DBC
870#define CAN_MB14_DATA0 0xFFC02DC0
871#define CAN_MB14_DATA1 0xFFC02DC4
872#define CAN_MB14_DATA2 0xFFC02DC8
873#define CAN_MB14_DATA3 0xFFC02DCC
874#define CAN_MB14_LENGTH 0xFFC02DD0
875#define CAN_MB14_TIMESTAMP 0xFFC02DD4
876#define CAN_MB14_ID0 0xFFC02DD8
877#define CAN_MB14_ID1 0xFFC02DDC
878#define CAN_MB15_DATA0 0xFFC02DE0
879#define CAN_MB15_DATA1 0xFFC02DE4
880#define CAN_MB15_DATA2 0xFFC02DE8
881#define CAN_MB15_DATA3 0xFFC02DEC
882#define CAN_MB15_LENGTH 0xFFC02DF0
883#define CAN_MB15_TIMESTAMP 0xFFC02DF4
884#define CAN_MB15_ID0 0xFFC02DF8
885#define CAN_MB15_ID1 0xFFC02DFC
886#define CAN_MB16_DATA0 0xFFC02E00
887#define CAN_MB16_DATA1 0xFFC02E04
888#define CAN_MB16_DATA2 0xFFC02E08
889#define CAN_MB16_DATA3 0xFFC02E0C
890#define CAN_MB16_LENGTH 0xFFC02E10
891#define CAN_MB16_TIMESTAMP 0xFFC02E14
892#define CAN_MB16_ID0 0xFFC02E18
893#define CAN_MB16_ID1 0xFFC02E1C
894#define CAN_MB17_DATA0 0xFFC02E20
895#define CAN_MB17_DATA1 0xFFC02E24
896#define CAN_MB17_DATA2 0xFFC02E28
897#define CAN_MB17_DATA3 0xFFC02E2C
898#define CAN_MB17_LENGTH 0xFFC02E30
899#define CAN_MB17_TIMESTAMP 0xFFC02E34
900#define CAN_MB17_ID0 0xFFC02E38
901#define CAN_MB17_ID1 0xFFC02E3C
902#define CAN_MB18_DATA0 0xFFC02E40
903#define CAN_MB18_DATA1 0xFFC02E44
904#define CAN_MB18_DATA2 0xFFC02E48
905#define CAN_MB18_DATA3 0xFFC02E4C
906#define CAN_MB18_LENGTH 0xFFC02E50
907#define CAN_MB18_TIMESTAMP 0xFFC02E54
908#define CAN_MB18_ID0 0xFFC02E58
909#define CAN_MB18_ID1 0xFFC02E5C
910#define CAN_MB19_DATA0 0xFFC02E60
911#define CAN_MB19_DATA1 0xFFC02E64
912#define CAN_MB19_DATA2 0xFFC02E68
913#define CAN_MB19_DATA3 0xFFC02E6C
914#define CAN_MB19_LENGTH 0xFFC02E70
915#define CAN_MB19_TIMESTAMP 0xFFC02E74
916#define CAN_MB19_ID0 0xFFC02E78
917#define CAN_MB19_ID1 0xFFC02E7C
918#define CAN_MB20_DATA0 0xFFC02E80
919#define CAN_MB20_DATA1 0xFFC02E84
920#define CAN_MB20_DATA2 0xFFC02E88
921#define CAN_MB20_DATA3 0xFFC02E8C
922#define CAN_MB20_LENGTH 0xFFC02E90
923#define CAN_MB20_TIMESTAMP 0xFFC02E94
924#define CAN_MB20_ID0 0xFFC02E98
925#define CAN_MB20_ID1 0xFFC02E9C
926#define CAN_MB21_DATA0 0xFFC02EA0
927#define CAN_MB21_DATA1 0xFFC02EA4
928#define CAN_MB21_DATA2 0xFFC02EA8
929#define CAN_MB21_DATA3 0xFFC02EAC
930#define CAN_MB21_LENGTH 0xFFC02EB0
931#define CAN_MB21_TIMESTAMP 0xFFC02EB4
932#define CAN_MB21_ID0 0xFFC02EB8
933#define CAN_MB21_ID1 0xFFC02EBC
934#define CAN_MB22_DATA0 0xFFC02EC0
935#define CAN_MB22_DATA1 0xFFC02EC4
936#define CAN_MB22_DATA2 0xFFC02EC8
937#define CAN_MB22_DATA3 0xFFC02ECC
938#define CAN_MB22_LENGTH 0xFFC02ED0
939#define CAN_MB22_TIMESTAMP 0xFFC02ED4
940#define CAN_MB22_ID0 0xFFC02ED8
941#define CAN_MB22_ID1 0xFFC02EDC
942#define CAN_MB23_DATA0 0xFFC02EE0
943#define CAN_MB23_DATA1 0xFFC02EE4
944#define CAN_MB23_DATA2 0xFFC02EE8
945#define CAN_MB23_DATA3 0xFFC02EEC
946#define CAN_MB23_LENGTH 0xFFC02EF0
947#define CAN_MB23_TIMESTAMP 0xFFC02EF4
948#define CAN_MB23_ID0 0xFFC02EF8
949#define CAN_MB23_ID1 0xFFC02EFC
950#define CAN_MB24_DATA0 0xFFC02F00
951#define CAN_MB24_DATA1 0xFFC02F04
952#define CAN_MB24_DATA2 0xFFC02F08
953#define CAN_MB24_DATA3 0xFFC02F0C
954#define CAN_MB24_LENGTH 0xFFC02F10
955#define CAN_MB24_TIMESTAMP 0xFFC02F14
956#define CAN_MB24_ID0 0xFFC02F18
957#define CAN_MB24_ID1 0xFFC02F1C
958#define CAN_MB25_DATA0 0xFFC02F20
959#define CAN_MB25_DATA1 0xFFC02F24
960#define CAN_MB25_DATA2 0xFFC02F28
961#define CAN_MB25_DATA3 0xFFC02F2C
962#define CAN_MB25_LENGTH 0xFFC02F30
963#define CAN_MB25_TIMESTAMP 0xFFC02F34
964#define CAN_MB25_ID0 0xFFC02F38
965#define CAN_MB25_ID1 0xFFC02F3C
966#define CAN_MB26_DATA0 0xFFC02F40
967#define CAN_MB26_DATA1 0xFFC02F44
968#define CAN_MB26_DATA2 0xFFC02F48
969#define CAN_MB26_DATA3 0xFFC02F4C
970#define CAN_MB26_LENGTH 0xFFC02F50
971#define CAN_MB26_TIMESTAMP 0xFFC02F54
972#define CAN_MB26_ID0 0xFFC02F58
973#define CAN_MB26_ID1 0xFFC02F5C
974#define CAN_MB27_DATA0 0xFFC02F60
975#define CAN_MB27_DATA1 0xFFC02F64
976#define CAN_MB27_DATA2 0xFFC02F68
977#define CAN_MB27_DATA3 0xFFC02F6C
978#define CAN_MB27_LENGTH 0xFFC02F70
979#define CAN_MB27_TIMESTAMP 0xFFC02F74
980#define CAN_MB27_ID0 0xFFC02F78
981#define CAN_MB27_ID1 0xFFC02F7C
982#define CAN_MB28_DATA0 0xFFC02F80
983#define CAN_MB28_DATA1 0xFFC02F84
984#define CAN_MB28_DATA2 0xFFC02F88
985#define CAN_MB28_DATA3 0xFFC02F8C
986#define CAN_MB28_LENGTH 0xFFC02F90
987#define CAN_MB28_TIMESTAMP 0xFFC02F94
988#define CAN_MB28_ID0 0xFFC02F98
989#define CAN_MB28_ID1 0xFFC02F9C
990#define CAN_MB29_DATA0 0xFFC02FA0
991#define CAN_MB29_DATA1 0xFFC02FA4
992#define CAN_MB29_DATA2 0xFFC02FA8
993#define CAN_MB29_DATA3 0xFFC02FAC
994#define CAN_MB29_LENGTH 0xFFC02FB0
995#define CAN_MB29_TIMESTAMP 0xFFC02FB4
996#define CAN_MB29_ID0 0xFFC02FB8
997#define CAN_MB29_ID1 0xFFC02FBC
998#define CAN_MB30_DATA0 0xFFC02FC0
999#define CAN_MB30_DATA1 0xFFC02FC4
1000#define CAN_MB30_DATA2 0xFFC02FC8
1001#define CAN_MB30_DATA3 0xFFC02FCC
1002#define CAN_MB30_LENGTH 0xFFC02FD0
1003#define CAN_MB30_TIMESTAMP 0xFFC02FD4
1004#define CAN_MB30_ID0 0xFFC02FD8
1005#define CAN_MB30_ID1 0xFFC02FDC
1006#define CAN_MB31_DATA0 0xFFC02FE0
1007#define CAN_MB31_DATA1 0xFFC02FE4
1008#define CAN_MB31_DATA2 0xFFC02FE8
1009#define CAN_MB31_DATA3 0xFFC02FEC
1010#define CAN_MB31_LENGTH 0xFFC02FF0
1011#define CAN_MB31_TIMESTAMP 0xFFC02FF4
1012#define CAN_MB31_ID0 0xFFC02FF8
1013#define CAN_MB31_ID1 0xFFC02FFC
1014
1015#define L1_DATA_A_SRAM 0xFF800000
1016#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1)
1017#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
1018#define L1_DATA_B_SRAM 0xFF900000
1019#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1)
1020#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE)
1021#define L1_INST_SRAM 0xFFA00000
1022#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1)
1023#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
1024
1025#endif
1026