LXR uboot/arch/mips/cpu/mips32/au1x00/au1x00

   1/* Only eth0 supported for now
   2 *
   3 * (C) Copyright 2003
   4 * Thomas.Lange@corelatus.se
   5 *
   6 * See file CREDITS for list of people who contributed to this
   7 * project.
   8 *
   9 * This program is free software; you can redistribute it and/or
  10 * modify it under the terms of the GNU General Public License as
  11 * published by the Free Software Foundation; either version 2 of
  12 * the License, or (at your option) any later version.
  13 *
  14 * This program is distributed in the hope that it will be useful,
  15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 * GNU General Public License for more details.
  18 *
  19 * You should have received a copy of the GNU General Public License
  20 * along with this program; if not, write to the Free Software
  21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22 * MA 02111-1307 USA
  23 */
  24#include <config.h>
  25
  26#if defined(CONFIG_SYS_DISCOVER_PHY)
  27#error "PHY not supported yet"
  28/* We just assume that we are running 100FD for now */
  29/* We all use switches, right? ;-) */
  30#endif
  31
  32/* I assume ethernet behaves like au1000 */
  33
  34#ifdef CONFIG_SOC_AU1000
  35/* Base address differ between cpu:s */
  36#define ETH0_BASE AU1000_ETH0_BASE
  37#define MAC0_ENABLE AU1000_MAC0_ENABLE
  38#else
  39#ifdef CONFIG_SOC_AU1100
  40#define ETH0_BASE AU1100_ETH0_BASE
  41#define MAC0_ENABLE AU1100_MAC0_ENABLE
  42#else
  43#ifdef CONFIG_SOC_AU1500
  44#define ETH0_BASE AU1500_ETH0_BASE
  45#define MAC0_ENABLE AU1500_MAC0_ENABLE
  46#else
  47#ifdef CONFIG_SOC_AU1550
  48#define ETH0_BASE AU1550_ETH0_BASE
  49#define MAC0_ENABLE AU1550_MAC0_ENABLE
  50#else
  51#error "No valid cpu set"
  52#endif
  53#endif
  54#endif
  55#endif
  56
  57#include <common.h>
  58#include <malloc.h>
  59#include <net.h>
  60#include <command.h>
  61#include <asm/io.h>
  62#include <asm/au1x00.h>
  63
  64#if defined(CONFIG_CMD_MII)
  65#include <miiphy.h>
  66#endif
  67
  68/* Ethernet Transmit and Receive Buffers */
  69#define DBUF_LENGTH  1520
  70#define PKT_MAXBUF_SIZE         1518
  71
  72static char txbuf[DBUF_LENGTH];
  73
  74static int next_tx;
  75static int next_rx;
  76
  77/* 4 rx and 4 tx fifos */
  78#define NO_OF_FIFOS 4
  79
  80typedef struct{
  81        u32 status;
  82        u32 addr;
  83        u32 len; /* Only used for tx */
  84        u32 not_used;
  85} mac_fifo_t;
  86
  87mac_fifo_t mac_fifo[NO_OF_FIFOS];
  88
  89#define MAX_WAIT 1000
  90
  91#if defined(CONFIG_CMD_MII)
  92int  au1x00_miiphy_read(const char *devname, unsigned char addr,
  93                unsigned char reg, unsigned short * value)
  94{
  95        volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
  96        volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
  97        u32 mii_control;
  98        unsigned int timedout = 20;
  99
 100        while (*mii_control_reg & MAC_MII_BUSY) {
 101                udelay(1000);
 102                if (--timedout == 0) {
 103                        printf("au1x00_eth: miiphy_read busy timeout!!\n");
 104                        return -1;
 105                }
 106        }
 107
 108        mii_control = MAC_SET_MII_SELECT_REG(reg) |
 109                MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_READ;
 110
 111        *mii_control_reg = mii_control;
 112
 113        timedout = 20;
 114        while (*mii_control_reg & MAC_MII_BUSY) {
 115                udelay(1000);
 116                if (--timedout == 0) {
 117                        printf("au1x00_eth: miiphy_read busy timeout!!\n");
 118                        return -1;
 119                }
 120        }
 121        *value = *mii_data_reg;
 122        return 0;
 123}
 124
 125int  au1x00_miiphy_write(const char *devname, unsigned char addr,
 126                unsigned char reg, unsigned short value)
 127{
 128        volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
 129        volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
 130        u32 mii_control;
 131        unsigned int timedout = 20;
 132
 133        while (*mii_control_reg & MAC_MII_BUSY) {
 134                udelay(1000);
 135                if (--timedout == 0) {
 136                        printf("au1x00_eth: miiphy_write busy timeout!!\n");
 137                        return -1;
 138                }
 139        }
 140
 141        mii_control = MAC_SET_MII_SELECT_REG(reg) |
 142                MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_WRITE;
 143
 144        *mii_data_reg = value;
 145        *mii_control_reg = mii_control;
 146        return 0;
 147}
 148#endif
 149
 150static int au1x00_send(struct eth_device *dev, void *packet, int length)
 151{
 152        volatile mac_fifo_t *fifo_tx =
 153                (volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
 154        int i;
 155        int res;
 156
 157        /* tx fifo should always be idle */
 158        fifo_tx[next_tx].len = length;
 159        fifo_tx[next_tx].addr = (virt_to_phys(packet))|TX_DMA_ENABLE;
 160        au_sync();
 161
 162        udelay(1);
 163        i=0;
 164        while(!(fifo_tx[next_tx].addr&TX_T_DONE)){
 165                if(i>MAX_WAIT){
 166                        printf("TX timeout\n");
 167                        break;
 168                }
 169                udelay(1);
 170                i++;
 171        }
 172
 173        /* Clear done bit */
 174        fifo_tx[next_tx].addr = 0;
 175        fifo_tx[next_tx].len = 0;
 176        au_sync();
 177
 178        res = fifo_tx[next_tx].status;
 179
 180        next_tx++;
 181        if(next_tx>=NO_OF_FIFOS){
 182                next_tx=0;
 183        }
 184        return(res);
 185}
 186
 187static int au1x00_recv(struct eth_device* dev){
 188        volatile mac_fifo_t *fifo_rx =
 189                (volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS);
 190
 191        int length;
 192        u32 status;
 193
 194        for(;;){
 195                if(!(fifo_rx[next_rx].addr&RX_T_DONE)){
 196                        /* Nothing has been received */
 197                        return(-1);
 198                }
 199
 200                status = fifo_rx[next_rx].status;
 201
 202                length = status&0x3FFF;
 203
 204                if(status&RX_ERROR){
 205                        printf("Rx error 0x%x\n", status);
 206                }
 207                else{
 208                        /* Pass the packet up to the protocol layers. */
 209                        NetReceive(NetRxPackets[next_rx], length - 4);
 210                }
 211
 212                fifo_rx[next_rx].addr = (virt_to_phys(NetRxPackets[next_rx]))|RX_DMA_ENABLE;
 213
 214                next_rx++;
 215                if(next_rx>=NO_OF_FIFOS){
 216                        next_rx=0;
 217                }
 218        } /* for */
 219
 220        return(0); /* Does anyone use this? */
 221}
 222
 223static int au1x00_init(struct eth_device* dev, bd_t * bd){
 224
 225        volatile u32 *macen = (volatile u32*)MAC0_ENABLE;
 226        volatile u32 *mac_ctrl = (volatile u32*)(ETH0_BASE+MAC_CONTROL);
 227        volatile u32 *mac_addr_high = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_HIGH);
 228        volatile u32 *mac_addr_low = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_LOW);
 229        volatile u32 *mac_mcast_high = (volatile u32*)(ETH0_BASE+MAC_MCAST_HIGH);
 230        volatile u32 *mac_mcast_low = (volatile u32*)(ETH0_BASE+MAC_MCAST_LOW);
 231        volatile mac_fifo_t *fifo_tx =
 232                (volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
 233        volatile mac_fifo_t *fifo_rx =
 234                (volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS);
 235        int i;
 236
 237        next_tx = TX_GET_DMA_BUFFER(fifo_tx[0].addr);
 238        next_rx = RX_GET_DMA_BUFFER(fifo_rx[0].addr);
 239
 240        /* We have to enable clocks before releasing reset */
 241        *macen = MAC_EN_CLOCK_ENABLE;
 242        udelay(10);
 243
 244        /* Enable MAC0 */
 245        /* We have to release reset before accessing registers */
 246        *macen = MAC_EN_CLOCK_ENABLE|MAC_EN_RESET0|
 247                MAC_EN_RESET1|MAC_EN_RESET2;
 248        udelay(10);
 249
 250        for(i=0;i<NO_OF_FIFOS;i++){
 251                fifo_tx[i].len = 0;
 252                fifo_tx[i].addr = virt_to_phys(&txbuf[0]);
 253                fifo_rx[i].addr = (virt_to_phys(NetRxPackets[i]))|RX_DMA_ENABLE;
 254        }
 255
 256        /* Put mac addr in little endian */
 257#define ea eth_get_dev()->enetaddr
 258        *mac_addr_high  =       (ea[5] <<  8) | (ea[4]      ) ;
 259        *mac_addr_low   =       (ea[3] << 24) | (ea[2] << 16) |
 260                (ea[1] <<  8) | (ea[0]      ) ;
 261#undef ea
 262        *mac_mcast_low = 0;
 263        *mac_mcast_high = 0;
 264
 265        /* Make sure the MAC buffer is in the correct endian mode */
 266#ifdef __LITTLE_ENDIAN
 267        *mac_ctrl = MAC_FULL_DUPLEX;
 268        udelay(1);
 269        *mac_ctrl = MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE;
 270#else
 271        *mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX;
 272        udelay(1);
 273        *mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE;
 274#endif
 275
 276        return(1);
 277}
 278
 279static void au1x00_halt(struct eth_device* dev){
 280        volatile u32 *macen = (volatile u32*)MAC0_ENABLE;
 281
 282        /* Put MAC0 in reset */
 283        *macen = 0;
 284}
 285
 286int au1x00_enet_initialize(bd_t *bis){
 287        struct eth_device* dev;
 288
 289        if ((dev = (struct eth_device*)malloc(sizeof *dev)) == NULL) {
 290                puts ("malloc failed\n");
 291                return -1;
 292        }
 293
 294        memset(dev, 0, sizeof *dev);
 295
 296        sprintf(dev->name, "Au1X00 ethernet");
 297        dev->iobase = 0;
 298        dev->priv   = 0;
 299        dev->init   = au1x00_init;
 300        dev->halt   = au1x00_halt;
 301        dev->send   = au1x00_send;
 302        dev->recv   = au1x00_recv;
 303
 304        eth_register(dev);
 305
 306#if defined(CONFIG_CMD_MII)
 307        miiphy_register(dev->name,
 308                au1x00_miiphy_read, au1x00_miiphy_write);
 309#endif
 310
 311        return 1;
 312}
 313