1/* 2 * (C) Copyright 2004, Freescale, Inc 3 * TsiChung Liew, Tsi-Chung.Liew@freescale.com. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 * 23 */ 24 25/* 26 * Minimal serial functions needed to use one of the PSC ports 27 * as serial console interface. 28 */ 29 30#include <common.h> 31#include <mpc8220.h> 32#include <serial.h> 33#include <linux/compiler.h> 34 35DECLARE_GLOBAL_DATA_PTR; 36 37#define PSC_BASE MMAP_PSC1 38 39#if defined(CONFIG_PSC_CONSOLE) 40static int mpc8220_serial_init(void) 41{ 42 volatile psc8220_t *psc = (psc8220_t *) PSC_BASE; 43 u32 counter; 44 45 /* write to SICR: SIM2 = uart mode,dcd does not affect rx */ 46 psc->cr = 0; 47 psc->ipcr_acr = 0; 48 psc->isr_imr = 0; 49 50 /* write to CSR: RX/TX baud rate from timers */ 51 psc->sr_csr = 0xdd000000; 52 53 psc->mr1_2 = PSC_MR1_BITS_CHAR_8 | PSC_MR1_NO_PARITY | PSC_MR2_STOP_BITS_1; 54 55 /* Setting up BaudRate */ 56 counter = ((gd->bus_clk / gd->baudrate)) >> 5; 57 counter++; 58 59 /* write to CTUR: divide counter upper byte */ 60 psc->ctur = ((counter & 0xff00) << 16); 61 /* write to CTLR: divide counter lower byte */ 62 psc->ctlr = ((counter & 0x00ff) << 24); 63 64 psc->cr = PSC_CR_RST_RX_CMD; 65 psc->cr = PSC_CR_RST_TX_CMD; 66 psc->cr = PSC_CR_RST_ERR_STS_CMD; 67 psc->cr = PSC_CR_RST_BRK_INT_CMD; 68 psc->cr = PSC_CR_RST_MR_PTR_CMD; 69 70 psc->cr = PSC_CR_RX_ENABLE | PSC_CR_TX_ENABLE; 71 return (0); 72} 73 74static void mpc8220_serial_putc(const char c) 75{ 76 volatile psc8220_t *psc = (psc8220_t *) PSC_BASE; 77 78 if (c == '\n') 79 serial_putc ('\r'); 80 81 /* Wait for last character to go. */ 82 while (!(psc->sr_csr & PSC_SR_TXRDY)); 83 84 psc->xmitbuf[0] = c; 85} 86 87static int mpc8220_serial_getc(void) 88{ 89 volatile psc8220_t *psc = (psc8220_t *) PSC_BASE; 90 91 /* Wait for a character to arrive. */ 92 while (!(psc->sr_csr & PSC_SR_RXRDY)); 93 return psc->xmitbuf[2]; 94} 95 96static int mpc8220_serial_tstc(void) 97{ 98 volatile psc8220_t *psc = (psc8220_t *) PSC_BASE; 99 100 return (psc->sr_csr & PSC_SR_RXRDY); 101} 102 103static void mpc8220_serial_setbrg(void) 104{ 105 volatile psc8220_t *psc = (psc8220_t *) PSC_BASE; 106 u32 counter; 107 108 counter = ((gd->bus_clk / gd->baudrate)) >> 5; 109 counter++; 110 111 /* write to CTUR: divide counter upper byte */ 112 psc->ctur = ((counter & 0xff00) << 16); 113 /* write to CTLR: divide counter lower byte */ 114 psc->ctlr = ((counter & 0x00ff) << 24); 115 116 psc->cr = PSC_CR_RST_RX_CMD; 117 psc->cr = PSC_CR_RST_TX_CMD; 118 119 psc->cr = PSC_CR_RX_ENABLE | PSC_CR_TX_ENABLE; 120} 121 122static struct serial_device mpc8220_serial_drv = { 123 .name = "mpc8220_serial", 124 .start = mpc8220_serial_init, 125 .stop = NULL, 126 .setbrg = mpc8220_serial_setbrg, 127 .putc = mpc8220_serial_putc, 128 .puts = default_serial_puts, 129 .getc = mpc8220_serial_getc, 130 .tstc = mpc8220_serial_tstc, 131}; 132 133void mpc8220_serial_initialize(void) 134{ 135 serial_register(&mpc8220_serial_drv); 136} 137 138__weak struct serial_device *default_serial_console(void) 139{ 140 return &mpc8220_serial_drv; 141} 142#endif /* CONFIG_PSC_CONSOLE */ 143