LXR uboot/arch/powerpc/cpu/mpc8260/cpu

   1/*
   2 * (C) Copyright 2000-2002
   3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24#include <common.h>
  25#include <mpc8260.h>
  26#include <asm/cpm_8260.h>
  27#include <ioports.h>
  28
  29DECLARE_GLOBAL_DATA_PTR;
  30
  31#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
  32extern unsigned long board_get_cpu_clk_f (void);
  33#endif
  34
  35static void config_8260_ioports (volatile immap_t * immr)
  36{
  37        int portnum;
  38
  39        for (portnum = 0; portnum < 4; portnum++) {
  40                uint pmsk = 0,
  41                     ppar = 0,
  42                     psor = 0,
  43                     pdir = 0,
  44                     podr = 0,
  45                     pdat = 0;
  46                iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
  47                iop_conf_t *eiopc = iopc + 32;
  48                uint msk = 1;
  49
  50                /*
  51                 * NOTE:
  52                 * index 0 refers to pin 31,
  53                 * index 31 refers to pin 0
  54                 */
  55                while (iopc < eiopc) {
  56                        if (iopc->conf) {
  57                                pmsk |= msk;
  58                                if (iopc->ppar)
  59                                        ppar |= msk;
  60                                if (iopc->psor)
  61                                        psor |= msk;
  62                                if (iopc->pdir)
  63                                        pdir |= msk;
  64                                if (iopc->podr)
  65                                        podr |= msk;
  66                                if (iopc->pdat)
  67                                        pdat |= msk;
  68                        }
  69
  70                        msk <<= 1;
  71                        iopc++;
  72                }
  73
  74                if (pmsk != 0) {
  75                        volatile ioport_t *iop = ioport_addr (immr, portnum);
  76                        uint tpmsk = ~pmsk;
  77
  78                        /*
  79                         * the (somewhat confused) paragraph at the
  80                         * bottom of page 35-5 warns that there might
  81                         * be "unknown behaviour" when programming
  82                         * PSORx and PDIRx, if PPARx = 1, so I
  83                         * decided this meant I had to disable the
  84                         * dedicated function first, and enable it
  85                         * last.
  86                         */
  87                        iop->ppar &= tpmsk;
  88                        iop->psor = (iop->psor & tpmsk) | psor;
  89                        iop->podr = (iop->podr & tpmsk) | podr;
  90                        iop->pdat = (iop->pdat & tpmsk) | pdat;
  91                        iop->pdir = (iop->pdir & tpmsk) | pdir;
  92                        iop->ppar |= ppar;
  93                }
  94        }
  95}
  96
  97#define SET_VAL_MASK(a, b, mask) ((a & mask) | (b & ~mask))
  98/*
  99 * Breath some life into the CPU...
 100 *
 101 * Set up the memory map,
 102 * initialize a bunch of registers,
 103 * initialize the UPM's
 104 */
 105void cpu_init_f (volatile immap_t * immr)
 106{
 107#if !defined(CONFIG_COGENT)             /* done in start.S for the cogent */
 108        uint sccr;
 109#endif
 110#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
 111        unsigned long cpu_clk;
 112#endif
 113        volatile memctl8260_t *memctl = &immr->im_memctl;
 114        extern void m8260_cpm_reset (void);
 115
 116        /* Pointer is writable since we allocated a register for it */
 117        gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
 118
 119        /* Clear initial global data */
 120        memset ((void *) gd, 0, sizeof (gd_t));
 121
 122        /* RSR - Reset Status Register - clear all status (5-4) */
 123        gd->arch.reset_status = immr->im_clkrst.car_rsr;
 124        immr->im_clkrst.car_rsr = RSR_ALLBITS;
 125
 126        /* RMR - Reset Mode Register - contains checkstop reset enable (5-5) */
 127        immr->im_clkrst.car_rmr = CONFIG_SYS_RMR;
 128
 129        /* BCR - Bus Configuration Register (4-25) */
 130#if defined(CONFIG_SYS_BCR_60x) && (CONFIG_SYS_BCR_SINGLE)
 131        if (immr->im_siu_conf.sc_bcr & BCR_EBM) {
 132                immr->im_siu_conf.sc_bcr = SET_VAL_MASK(immr->im_siu_conf.sc_bcr, CONFIG_SYS_BCR_60x, 0x80000010);
 133        } else {
 134                immr->im_siu_conf.sc_bcr = SET_VAL_MASK(immr->im_siu_conf.sc_bcr, CONFIG_SYS_BCR_SINGLE, 0x80000010);
 135        }
 136#else
 137        immr->im_siu_conf.sc_bcr = CONFIG_SYS_BCR;
 138#endif
 139
 140        /* SIUMCR - contains debug pin configuration (4-31) */
 141#if defined(CONFIG_SYS_SIUMCR_LOW) && (CONFIG_SYS_SIUMCR_HIGH)
 142        cpu_clk = board_get_cpu_clk_f ();
 143        if (cpu_clk >= 100000000) {
 144                immr->im_siu_conf.sc_siumcr = SET_VAL_MASK(immr->im_siu_conf.sc_siumcr, CONFIG_SYS_SIUMCR_HIGH, 0x9f3cc000);
 145        } else {
 146                immr->im_siu_conf.sc_siumcr = SET_VAL_MASK(immr->im_siu_conf.sc_siumcr, CONFIG_SYS_SIUMCR_LOW, 0x9f3cc000);
 147        }
 148#else
 149        immr->im_siu_conf.sc_siumcr = CONFIG_SYS_SIUMCR;
 150#endif
 151
 152        config_8260_ioports (immr);
 153
 154        /* initialize time counter status and control register (4-40) */
 155        immr->im_sit.sit_tmcntsc = CONFIG_SYS_TMCNTSC;
 156
 157        /* initialize the PIT (4-42) */
 158        immr->im_sit.sit_piscr = CONFIG_SYS_PISCR;
 159
 160#if !defined(CONFIG_COGENT)             /* done in start.S for the cogent */
 161        /* System clock control register (9-8) */
 162        sccr = immr->im_clkrst.car_sccr &
 163                (SCCR_PCI_MODE | SCCR_PCI_MODCK | SCCR_PCIDF_MSK);
 164        immr->im_clkrst.car_sccr = sccr |
 165                (CONFIG_SYS_SCCR & ~(SCCR_PCI_MODE | SCCR_PCI_MODCK | SCCR_PCIDF_MSK) );
 166#endif /* !CONFIG_COGENT */
 167
 168        /*
 169         * Memory Controller:
 170         */
 171
 172        /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
 173         * addresses - these have to be modified later when FLASH size
 174         * has been determined
 175         */
 176
 177#if defined(CONFIG_SYS_OR0_REMAP)
 178        memctl->memc_or0 = CONFIG_SYS_OR0_REMAP;
 179#endif
 180#if defined(CONFIG_SYS_OR1_REMAP)
 181        memctl->memc_or1 = CONFIG_SYS_OR1_REMAP;
 182#endif
 183
 184        /* now restrict to preliminary range */
 185        /* the PS came from the HRCW, don't change it */
 186        memctl->memc_br0 = SET_VAL_MASK(memctl->memc_br0 , CONFIG_SYS_BR0_PRELIM, BRx_PS_MSK);
 187        memctl->memc_or0 = CONFIG_SYS_OR0_PRELIM;
 188
 189#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
 190        memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
 191        memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
 192#endif
 193
 194#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
 195        memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
 196        memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
 197#endif
 198
 199#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
 200        memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
 201        memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
 202#endif
 203
 204#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
 205        memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM;
 206        memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM;
 207#endif
 208
 209#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
 210        memctl->memc_or5 = CONFIG_SYS_OR5_PRELIM;
 211        memctl->memc_br5 = CONFIG_SYS_BR5_PRELIM;
 212#endif
 213
 214#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
 215        memctl->memc_or6 = CONFIG_SYS_OR6_PRELIM;
 216        memctl->memc_br6 = CONFIG_SYS_BR6_PRELIM;
 217#endif
 218
 219#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
 220        memctl->memc_or7 = CONFIG_SYS_OR7_PRELIM;
 221        memctl->memc_br7 = CONFIG_SYS_BR7_PRELIM;
 222#endif
 223
 224#if defined(CONFIG_SYS_BR8_PRELIM) && defined(CONFIG_SYS_OR8_PRELIM)
 225        memctl->memc_or8 = CONFIG_SYS_OR8_PRELIM;
 226        memctl->memc_br8 = CONFIG_SYS_BR8_PRELIM;
 227#endif
 228
 229#if defined(CONFIG_SYS_BR9_PRELIM) && defined(CONFIG_SYS_OR9_PRELIM)
 230        memctl->memc_or9 = CONFIG_SYS_OR9_PRELIM;
 231        memctl->memc_br9 = CONFIG_SYS_BR9_PRELIM;
 232#endif
 233
 234#if defined(CONFIG_SYS_BR10_PRELIM) && defined(CONFIG_SYS_OR10_PRELIM)
 235        memctl->memc_or10 = CONFIG_SYS_OR10_PRELIM;
 236        memctl->memc_br10 = CONFIG_SYS_BR10_PRELIM;
 237#endif
 238
 239#if defined(CONFIG_SYS_BR11_PRELIM) && defined(CONFIG_SYS_OR11_PRELIM)
 240        memctl->memc_or11 = CONFIG_SYS_OR11_PRELIM;
 241        memctl->memc_br11 = CONFIG_SYS_BR11_PRELIM;
 242#endif
 243
 244        m8260_cpm_reset ();
 245}
 246
 247/*
 248 * initialize higher level parts of CPU like time base and timers
 249 */
 250int cpu_init_r (void)
 251{
 252        volatile immap_t *immr = (immap_t *) gd->bd->bi_immr_base;
 253
 254        immr->im_cpm.cp_rccr = CONFIG_SYS_RCCR;
 255
 256        return (0);
 257}
 258
 259/*
 260 * print out the reason for the reset
 261 */
 262int prt_8260_rsr (void)
 263{
 264        static struct {
 265                ulong mask;
 266                char *desc;
 267        } bits[] = {
 268                {
 269                RSR_JTRS, "JTAG"}, {
 270                RSR_CSRS, "Check Stop"}, {
 271                RSR_SWRS, "Software Watchdog"}, {
 272                RSR_BMRS, "Bus Monitor"}, {
 273                RSR_ESRS, "External Soft"}, {
 274                RSR_EHRS, "External Hard"}
 275        };
 276        static int n = sizeof bits / sizeof bits[0];
 277        ulong rsr = gd->arch.reset_status;
 278        int i;
 279        char *sep;
 280
 281        puts (CPU_ID_STR " Reset Status:");
 282
 283        sep = " ";
 284        for (i = 0; i < n; i++)
 285                if (rsr & bits[i].mask) {
 286                        printf ("%s%s", sep, bits[i].desc);
 287                        sep = ", ";
 288                }
 289
 290        puts ("\n\n");
 291        return (0);
 292}
 293